JPH0837207A - Semiconductor mounting method - Google Patents
Semiconductor mounting methodInfo
- Publication number
- JPH0837207A JPH0837207A JP6170706A JP17070694A JPH0837207A JP H0837207 A JPH0837207 A JP H0837207A JP 6170706 A JP6170706 A JP 6170706A JP 17070694 A JP17070694 A JP 17070694A JP H0837207 A JPH0837207 A JP H0837207A
- Authority
- JP
- Japan
- Prior art keywords
- bump forming
- forming body
- circuit board
- bump
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/072—Connecting or disconnecting of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W72/241—Dispositions, e.g. layouts
Landscapes
- Wire Bonding (AREA)
Abstract
(57)【要約】
【目的】 複数の部品を一括にCCB接合及びフリップ
チップ接合するための半導体実装方法を提供する。
【構成】 半導体素子1と回路基板9の双方に形成され
た凹凸のバンプ形成体8を組み合わせることにより仮固
定を行う。また、前記バンプ形成体8の形状は、半導体
素子1と回路基板9を接続するリフロー後、双方のバン
プ形成体8が溶融した一体のバンプとする。ここで、リ
フロー前即ち仮固定時の前記バンプ形成体8の面積は、
電極パタン2と同じである必要はないので、電極パタン
2より小さいバンプ形成体8と電極パタン2より大きい
バンプ形成体8の組み合せで仮固定を行いうる。
【効果】 光素子及びその他多数の光部品を一括してリ
フロー固定することが可能になり、作業量削減による低
コスト化が出来る。
(57) [Summary] [Object] To provide a semiconductor mounting method for CCB bonding and flip-chip bonding a plurality of components at once. [Structure] Temporary fixing is performed by combining bump forming bodies 8 having irregularities formed on both the semiconductor element 1 and the circuit board 9. Further, the bump forming body 8 is formed into an integral bump in which both the bump forming bodies 8 are melted after the reflow for connecting the semiconductor element 1 and the circuit board 9. Here, the area of the bump forming body 8 before reflow, that is, at the time of temporary fixing is
Since it does not have to be the same as the electrode pattern 2, the bump formation 8 smaller than the electrode pattern 2 and the bump formation 8 larger than the electrode pattern 2 can be temporarily fixed. [Effect] The optical element and many other optical components can be collectively reflow-fixed, and the cost can be reduced by reducing the work amount.
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体素子と回路基板の
実装に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mounting a semiconductor device and a circuit board.
【0002】[0002]
【従来の技術】計算機実装では、高速化を図るため、微
細はんだ接続を媒体としてLSIの配線長を短縮するC
CB実装法(E.M.Davis et al.,;Solid Logic Technolo
gy,IBMJ.Res.Develop.,8,2,pp.102-144(1964))がよく用
いられる。CCBプロセスは、LSI配線プロセスが終
了し、ウエハからチップ化する前に、(1)実装用保護
絶縁膜形成(2)はんだ下地電極形成(3)はんだ電極
形成を行い、回路基板との実装時に(4)フラックス塗
布(5)位置合わせ(6)リフロー(7)フラックス洗
浄を行うのが主な工程である。2. Description of the Related Art In computer mounting, in order to achieve a high speed, the wiring length of an LSI is shortened by using a fine solder connection as a medium.
CB mounting method (EMDavis et al.,; Solid Logic Technolo
gy, IBMJ.Res.Develop., 8,2, pp.102-144 (1964)) is often used. In the CCB process, before the LSI wiring process is completed and the wafer is made into a chip, (1) formation of a protective insulating film for mounting (2) formation of a solder base electrode (3) formation of a solder electrode, and at the time of mounting on a circuit board, (4) Flux application (5) Positioning (6) Reflow (7) Flux cleaning is the main process.
【0003】一方、光モジュールの低価格化のために、
光素子の実装をバンプの表面張力により電極パタン同士
が高精度で位置決めされるセルフアライメント効果を利
用して光軸の無調整化を図る検討が行われている。On the other hand, in order to reduce the price of optical modules,
For the mounting of the optical element, studies are being made to make the optical axis unadjusted by utilizing the self-alignment effect in which the electrode patterns are positioned with high accuracy by the surface tension of the bumps.
【0004】[0004]
【発明が解決しようとする課題】従来のCCB技術をそ
のまま光素子の実装に用いる場合、バンプの表面の酸化
膜の除去・酸化防止及び仮固定の役割を果たしているフ
ラックスが、光素子の特性を劣化させ、光モジュールの
信頼性を低下させる懸念がある。そこで、フラックスレ
スによるCCBが望ましい。フラックスレスによるCC
Bを行う場合、(1)バンプの酸化防止(2)半導体素
子の仮固定法について考慮する必要がある。When the conventional CCB technology is used as it is for mounting an optical element, the flux that plays a role of removing, preventing oxidation of the oxide film on the surface of the bump, and temporarily fixing the characteristic of the optical element. There is a concern that it may deteriorate and reduce the reliability of the optical module. Therefore, CCB without flux is desirable. CC by fluxless
When performing B, it is necessary to consider (1) prevention of bump oxidation and (2) temporary fixing method of semiconductor element.
【0005】本発明の目的は、複数の部品を一括にCC
B接合及びフリップチップ接合するための半導体実装方
法を提供することにある。An object of the present invention is to CC a plurality of parts at once.
It is to provide a semiconductor mounting method for B-bonding and flip-chip bonding.
【0006】[0006]
【課題を解決するための手段】上記課題を解決する為
に、本発明では、電極上に凸(又は凹)型のソルダから
成るバンプ形成体を持つ半導体素子と、同じく電極上に
前記バンプ形成体に合体する凹(又は凸)型のバンプ形
成体を持つ回路基板のバンプ形成体を重ね合わせて仮固
定する。この結果、半導体素子を回路基板に搭載してか
らリフローまでの間の位置ずれを防ぐ事が出来る。In order to solve the above problems, according to the present invention, a semiconductor element having a bump forming body made of a convex (or concave) type solder on an electrode, and the bump forming on the electrode as well. The bump forming body of the circuit board having the concave (or convex) type bump forming body to be integrated with the body is superposed and temporarily fixed. As a result, it is possible to prevent the positional deviation between the mounting of the semiconductor element on the circuit board and the reflow.
【0007】[0007]
【作用】半導体素子と回路基板の双方の電極を金属バン
プを介して接合させる半導体素子と回路基板の実装に於
いて、半導体素子と回路基板の双方に形成された凹凸の
バンプ形成体を組み合わせることにより仮固定を行う。
前記バンプ形成体の形状は、半導体素子と回路基板を接
続するリフロー後、双方のバンプ形成体が溶融した一体
のバンプとなる。ここで、リフロー前即ち仮固定時の前
記バンプ形成体の面積は、バンプ形成体下層の電極パタ
ンと同じである必要はないので、前記電極パタンより小
さいバンプ形成体と前記電極パタンより大きいバンプ形
成体の組み合せで仮固定時の位置合わせを容易にするこ
とが可能である。In the mounting of the semiconductor element and the circuit board in which the electrodes of both the semiconductor element and the circuit board are bonded through the metal bumps, the bump forming bodies having irregularities formed on both the semiconductor element and the circuit board are combined. Temporarily fix by.
The shape of the bump forming body becomes an integrated bump in which both bump forming bodies are melted after the reflow for connecting the semiconductor element and the circuit board. Here, since the area of the bump forming body before reflow, that is, at the time of temporary fixing does not need to be the same as the electrode pattern of the lower layer of the bump forming body, a bump forming body smaller than the electrode pattern and a bump forming larger than the electrode pattern are formed. It is possible to facilitate the positioning at the time of temporary fixing by combining the bodies.
【0008】[0008]
【実施例】次に図面を用いて本発明の実施例を説明す
る。Embodiments of the present invention will be described with reference to the drawings.
【0009】図1(a)における半導体素子1は寸法3
00×300×120tμmのInGaAsP基板からなり、T
i/Pt/Au/Moの電極パタン2が形成されている。電極パタ
ンが形成された半導体素子1に、絶縁膜3(SiO2)
をスパッタにより形成し(図1(b))、レジスト4を
マスクパタンとして(図1(c))、電極パタン2とバ
ンプ(Au/Sn)のコンタクトをとる開口5のSiO2とM
oをドライエッチングでエッチングする(図1
(d))。エッチング後、レジストを除去すると図1
(e))のようになる。この時の露出した電極パタン2
の表面は、Auとなる。The semiconductor element 1 shown in FIG.
Made of InGaAsP substrate of 00 × 300 × 120tμm, T
An electrode pattern 2 of i / Pt / Au / Mo is formed. An insulating film 3 (SiO2) is formed on the semiconductor element 1 on which the electrode pattern is formed.
Is formed by sputtering (FIG. 1 (b)), the resist 4 is used as a mask pattern (FIG. 1 (c)), and SiO2 and M in the opening 5 for making contact between the electrode pattern 2 and the bump (Au / Sn) are formed.
Etching o by dry etching (Fig. 1
(D)). After the etching, the resist is removed.
(E)). Exposed electrode pattern 2 at this time
The surface of Au becomes Au.
【0010】次に、図2を用いてリフトオフによるバン
プ形成体プロセスを説明する。図2(a)は、絶縁膜3
及び電極パタン2とバンプ(Au/Sn)のコンタクト
をとる開口5が形成された半導体素子1で、厚膜レジス
ト6をマスクパタンとして(図2(b))、その上から
Au/Sn7を蒸着し(図2(c))、蒸着後、厚膜レジス
ト6とパタン以外のAu/Sn7を除去しバンプ形成体8が
完成する(図2(d))。Next, a bump forming process by lift-off will be described with reference to FIG. FIG. 2A shows the insulating film 3
Also, in the semiconductor element 1 in which the opening 5 for making contact between the electrode pattern 2 and the bump (Au / Sn) is formed, the thick film resist 6 is used as a mask pattern (FIG. 2B), and from above.
Au / Sn 7 is vapor-deposited (FIG. 2C), and after vapor deposition, Au / Sn 7 other than the thick film resist 6 and the pattern is removed to complete the bump forming body 8 (FIG. 2D).
【0011】バンプ形成体8の下層にある電極パタン2
の直径は、半導体素子1、回路基板9ともにφ60μm
である。一方、図3に示したように、リフトオフ後の半
導体素子1のバンプ形成体8は直径φ20μm×t20
μmで電極パタン2の中央に位置する。また、図4に示
したように、回路基板9のバンプ形成体8は外周φ12
0μm・内周φ40μm×t20μmのドーナツの変形
した形状となっている。ここで、注意すべき点は、回路
基板9のバンプ形成体8は、リフトオフ時にドーナツの
中央部の厚膜レジスト6及びAu/Sn7が残ることを防ぐ
ために、完全なドーナツ型を避けている。An electrode pattern 2 under the bump forming body 8
Has a diameter of 60 μm for both the semiconductor element 1 and the circuit board 9.
Is. On the other hand, as shown in FIG. 3, the bump forming body 8 of the semiconductor element 1 after the lift-off has a diameter of 20 μm × t20.
It is located at the center of the electrode pattern 2 in μm. Further, as shown in FIG. 4, the bump forming body 8 of the circuit board 9 has an outer circumference φ12.
It has a deformed shape of a donut with 0 μm and an inner circumference φ40 μm × t20 μm. Here, it should be noted that the bump forming body 8 of the circuit board 9 avoids a perfect donut shape in order to prevent the thick film resist 6 and Au / Sn 7 in the central portion of the donut from remaining at the time of lift-off.
【0012】次に半導体素子1と回路基板9の接合を行
う。この過程は、素子搭載とリフローによる2段階で行
われる。まず、位置合わせ精度±10μm以上のアライ
メント機能を有するボンディング装置で、図5(a)に
示したように、回路基板9上のバンプ形成体8に半導体
素子1のバンプ形成体8を填め込むように搭載する。そ
の後、不活性雰囲気条件下又は水素ガスを用いた還元雰
囲気条件下でリフロー加熱する。この際、半導体素子1
及び回路基板9のバンプ形成体8は、溶融すると一体の
球となり(図5(b))、その時のバンプの表面張力に
より、半導体素子1及び回路基板9の電極パタン2同士
が自己整合するように移動し、Au/Sn凝固時(図5
(c))には、高精度で位置決めされる。Next, the semiconductor element 1 and the circuit board 9 are joined. This process is performed in two steps, that is, element mounting and reflow. First, as shown in FIG. 5A, the bump forming body 8 of the semiconductor element 1 is fitted into the bump forming body 8 on the circuit board 9 by using a bonding apparatus having an alignment function with an alignment accuracy of ± 10 μm or more. To be installed on. After that, reflow heating is performed under an inert atmosphere condition or a reducing atmosphere condition using hydrogen gas. At this time, the semiconductor element 1
The bump forming body 8 of the circuit board 9 becomes an integrated sphere when melted (FIG. 5B), and the surface tension of the bumps at that time causes the electrode patterns 2 of the semiconductor element 1 and the circuit board 9 to self-align. To Au / Sn solidification (Fig. 5
In (c), the positioning is performed with high accuracy.
【0013】本実施例では、バンプの材料としてAu/Sn
を用いたが、Pb/SnまたはAg/Snを用いても同様に実現で
きる。In this embodiment, Au / Sn is used as the bump material.
However, the same can be realized by using Pb / Sn or Ag / Sn.
【0014】本実施例は、基本的に実施例1と同じであ
るが、バンプ形成体の形状が異なる場合である。図6に
は半導体素子の形状を、図7には回路基板の形状を示
す。本実施例のように、バンプ形成体を非対称にするこ
とも可能である。This embodiment is basically the same as the first embodiment except that the bump forming body has a different shape. FIG. 6 shows the shape of the semiconductor element, and FIG. 7 shows the shape of the circuit board. It is also possible to make the bump forming body asymmetrical as in the present embodiment.
【0015】[0015]
【発明の効果】以上、述べた本発明によれば、フラック
スレスによるCCB接合、フリップチップ接合に於い
て、位置合わせからリフローするまでの仮固定を機械的
にホールドせずに行うことが出来る。そのため、光素子
及びその他多数の光部品を一括してリフロー固定するこ
とが可能になり、作業量削減による低コスト化が期待出
来る。According to the present invention described above, in CCB bonding and flip chip bonding by fluxless, temporary fixing from alignment to reflow can be performed without mechanical holding. Therefore, the optical element and many other optical components can be reflow-fixed at one time, and the cost can be expected to be reduced by reducing the work amount.
【図1】(a)−(e)実施例1における絶縁膜形成プ
ロセス断面図。1A to 1E are sectional views of an insulating film forming process in a first embodiment.
【図2】(a)−(d)実施例1におけるバンプ形成体
形成プロセス断面図。2A to 2D are sectional views of the bump forming body forming process in the first embodiment.
【図3】(a)実施例1におけるリフロー前の半導体素
子の平面図、(b)AA’における断面図。3A is a plan view of a semiconductor element before reflow in Example 1, and FIG. 3B is a sectional view taken along line AA ′.
【図4】(a)実施例1におけるリフロー前の回路基板
の平面図、(b)AA’における断面図。4A is a plan view of a circuit board before reflow in Embodiment 1, and FIG. 4B is a sectional view taken along line AA ′.
【図5】(a)実施例1におけるリフロー前のバンプ形
成体断面図、(b)Au/Sn溶融時のバンプ形成体断面
図、(c)Au/Sn凝固時のバンプ形成体断面図。5A is a sectional view of a bump-formed body before reflow in Example 1, FIG. 5B is a sectional view of a bump-formed body during melting of Au / Sn, and FIG. 5C is a sectional view of a bump-formed body during solidification of Au / Sn.
【図6】(a)実施例2におけるリフロー前の半導体素
子の平面図、(b)AA’における断面図。6A is a plan view of a semiconductor element before reflow in Example 2, and FIG. 6B is a sectional view taken along line AA ′.
【図7】(a)実施例2におけるリフロー前の回路基板
の平面図、(b)AA’における断面図。7A is a plan view of the circuit board before reflow in the second embodiment, and FIG. 7B is a cross-sectional view taken along line AA ′.
1…半導体素子、2…電極パタン、3…絶縁膜、4…レ
ジストパタン、5…電極パタンとバンプ形成体のコンタ
クトをとる開口、6…厚膜レジストパタン、7…Au/Sn
蒸着膜、8…バンプ形成体、9…回路基板。DESCRIPTION OF SYMBOLS 1 ... Semiconductor element, 2 ... Electrode pattern, 3 ... Insulating film, 4 ... Resist pattern, 5 ... Aperture for making contact between electrode pattern and bump forming body, 6 ... Thick film resist pattern, 7 ... Au / Sn
Deposition film, 8 ... Bump forming body, 9 ... Circuit board.
Claims (5)
接続に於いて、半導体素子と回路基板の双方に形成され
た凹凸のバンプ形成体を組み合わせることにより仮固定
を行う半導体実装方法。1. A semiconductor mounting method, wherein, in connection between a semiconductor element and a circuit board by means of metal bumps, temporary bumping is carried out by combining bump-shaped bump-formed bodies formed on both the semiconductor element and circuit board.
時に、半導体素子上のバンプ形成体と前記バンプ形成体
に接触する回路基板上のバンプ形成体が、溶融して一体
のバンプとなる請求項1記載の半導体実装方法。2. The bump forming body on the semiconductor element and the bump forming body on the circuit board which is in contact with the bump forming body are melted to form an integral bump at the time of reflow for connecting the semiconductor element and the circuit board. 1. The semiconductor mounting method described in 1.
ンプ形成体の面積を、前記半導体基板の電極及び前記回
路基板の電極と前記バンプ形成体が電気的コンタクトし
ている面積より拡大した請求項1又は2記載の半導体実
装方法。3. The area of the bump forming body before the bonding of the semiconductor substrate and the circuit board is made larger than the area where the electrodes of the semiconductor substrate and the electrodes of the circuit board and the bump forming body are in electrical contact with each other. 1. The semiconductor mounting method according to 1 or 2.
形成体を接着させる役割を持つメタライズ層と、前記半
導体素子と前記バンプ形成体を接着させないパシベーシ
ョン層を備えることを特徴としている半導体素子。4. A semiconductor device comprising a bump forming body, a metallization layer having a role of adhering the semiconductor element and the bump forming body, and a passivation layer which does not adhere the semiconductor element and the bump forming body.
成体を接着させる役割を持つメタライズ層と、前記回路
基板と前記バンプ形成体を接着させないパシベーション
層を備えることを特徴としている回路基板。5. A circuit board comprising a bump forming body, a metallization layer having a role of adhering the circuit board and the bump forming body, and a passivation layer that does not adhere the circuit board and the bump forming body.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6170706A JPH0837207A (en) | 1994-07-22 | 1994-07-22 | Semiconductor mounting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6170706A JPH0837207A (en) | 1994-07-22 | 1994-07-22 | Semiconductor mounting method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0837207A true JPH0837207A (en) | 1996-02-06 |
Family
ID=15909891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6170706A Pending JPH0837207A (en) | 1994-07-22 | 1994-07-22 | Semiconductor mounting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0837207A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006210591A (en) * | 2005-01-27 | 2006-08-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
-
1994
- 1994-07-22 JP JP6170706A patent/JPH0837207A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006210591A (en) * | 2005-01-27 | 2006-08-10 | Matsushita Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
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