JPH0837253A - Semiconductor device, manufacturing method thereof, and mounting method - Google Patents

Semiconductor device, manufacturing method thereof, and mounting method

Info

Publication number
JPH0837253A
JPH0837253A JP6171020A JP17102094A JPH0837253A JP H0837253 A JPH0837253 A JP H0837253A JP 6171020 A JP6171020 A JP 6171020A JP 17102094 A JP17102094 A JP 17102094A JP H0837253 A JPH0837253 A JP H0837253A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor chip
conductor layer
resin
sealing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6171020A
Other languages
Japanese (ja)
Other versions
JP3150253B2 (en
Inventor
Tetsuya Ueda
哲也 上田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP17102094A priority Critical patent/JP3150253B2/en
Priority to DE19526511A priority patent/DE19526511A1/en
Priority to KR1019950022303A priority patent/KR100201168B1/en
Publication of JPH0837253A publication Critical patent/JPH0837253A/en
Application granted granted Critical
Publication of JP3150253B2 publication Critical patent/JP3150253B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10Containers or parts thereof
    • H10W76/12Containers or parts thereof characterised by their shape
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • H10W70/411Chip-supporting parts, e.g. die pads
    • H10W70/415Leadframe inner leads serving as die pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/01Manufacture or treatment
    • H10W72/019Manufacture or treatment of bond pads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09Shape and layout
    • H05K2201/09209Shape and layout details of conductors
    • H05K2201/09654Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09709Staggered pads, lands or terminals; Parallel conductors in different planes
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10439Position of a single component
    • H05K2201/10454Vertically mounted
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431Details of mounted components
    • H05K2201/10568Integral adaptations of a component or an auxiliary PCB for mounting, e.g. integral spacer element
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10659Different types of terminals for the same component, e.g. solder balls combined with leads
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10696Single-in-line [SIL] package
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16Inspection; Monitoring; Aligning
    • H05K2203/167Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3421Leaded components
    • H05K3/3426Leaded components characterised by the leads
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40Leadframes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/20Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/541Dispositions of bond wires
    • H10W72/5453Dispositions of bond wires connecting between multiple bond pads on a chip, e.g. daisy chain
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/59Bond pads specially adapted therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/932Plan-view shape, i.e. in top view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/931Shapes of bond pads
    • H10W72/934Cross-sectional shape, i.e. in side view
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/90Bond pads, in general
    • H10W72/951Materials of bond pads
    • H10W72/952Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00Encapsulations, e.g. protective coatings
    • H10W74/10Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】 【目的】 耐湿性等信頼性が高くかつ高密度の実装が可
能な汎用性の優れた半導体装置およびその製造方法並び
に実装方法を得る。 【構成】 半導体チップ2上に設けられ、導体層10を
有するテープ9と、半導体チップ2上に設けられた電極
であるボンディングパッド3と導体層10とを電気的に
接続する金属細線11と、半導体チップ2、導体層1
0、テープ9および上記金属細線11を樹脂封止する封
止樹脂6と、この封止樹脂6に設けられた開口部12を
介して導体層10に接続された外部電極である半田バン
プ5とで構成する。
(57) [Abstract] [Purpose] To obtain a highly versatile semiconductor device having high reliability such as moisture resistance and capable of high-density mounting, a manufacturing method thereof, and a mounting method. [Structure] A tape 9 provided on a semiconductor chip 2 and having a conductor layer 10, a thin metal wire 11 for electrically connecting a bonding pad 3 which is an electrode provided on the semiconductor chip 2 and the conductor layer 10. Semiconductor chip 2, conductor layer 1
0, the tape 9 and the sealing resin 6 for sealing the metal thin wires 11 with a resin, and the solder bumps 5 which are external electrodes connected to the conductor layer 10 through the openings 12 provided in the sealing resin 6. It consists of.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体装置およびそ
の製造方法並びに実装方法に関し、特に高密度実装可能
な半導体装置の表面実装型パッケージに関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, and a method of mounting the same, and more particularly, to a surface mount type package of a semiconductor device capable of high density mounting.

【0002】[0002]

【従来の技術】近年、半導体装置の高密度実装化、表面
実装化が進んできており、それに関する技術も多数提案
されている。例えば、表面実装では、これまでのリード
を用いた実装に代わり、半導体チップを直接基板に実装
する際に用いられたバンプと呼ばれる金属突起状電極を
有し、これを再融(リフロー)して実装するという方法
を樹脂封止した半導体装置に適用しようとするものであ
る。
2. Description of the Related Art In recent years, high-density mounting and surface mounting of semiconductor devices have been advanced, and many technologies related thereto have been proposed. For example, in surface mounting, instead of mounting using leads up to now, there is a metal protruding electrode called a bump used when mounting a semiconductor chip directly on a substrate, and this is remelted (reflowed). The mounting method is applied to a resin-sealed semiconductor device.

【0003】このような表面実装の一例として、図28
は例えば特開平1−179334号公報に記載された従
来の半導体装置の一部断面を示す外観図であり、図29
は図28を線g−g′の部分で切断して示す断面図であ
る。図において、1は半導体装置、2は半導体チップ、
3は半導体チップ上に設けられた電極としてのボンディ
ングパッド、4は半導体チップ2に取り付けられた接続
用導体、5は導体4上に設けられた半田チップ、6は半
導体チップ2を周囲環境から守るために封止する封止樹
脂である。
As an example of such surface mounting, FIG.
29 is an external view showing a partial cross section of a conventional semiconductor device disclosed in, for example, Japanese Patent Laid-Open No. 1-179334.
FIG. 29 is a cross-sectional view showing FIG. 28 taken along the line gg ′. In the figure, 1 is a semiconductor device, 2 is a semiconductor chip,
3 is a bonding pad as an electrode provided on the semiconductor chip, 4 is a connecting conductor attached to the semiconductor chip 2, 5 is a solder chip provided on the conductor 4, and 6 is the semiconductor chip 2 protected from the ambient environment. This is a sealing resin for sealing.

【0004】この半導体装置1は半導体チップ2の周囲
を封止樹脂6で封止し、半導体チップ2を外界環境から
防御すると共に、封止樹脂6の厚さを極力薄くし、半導
体装置1の体積を小さくして高密度実装化を図るもので
ある。また、半導体装置をバンプを用いて実装するパッ
ケージとしてBGA(Bump・Grid・Array)と呼ばれるパ
ッケージがあり、現在日本電子機械工業会(EIAJ)
で標準化等が進められている。このBGAのパッケージ
として例えば米国テセラ社のものがあり、これは半導体
チップ上にバンプを格子状に配列した回路フイルムを接
着して電気的に接続したパッケージである(Tessera′s
Compliant Chip TM Technology参照)。
In this semiconductor device 1, the periphery of the semiconductor chip 2 is sealed with a sealing resin 6 to protect the semiconductor chip 2 from the external environment, and at the same time, the thickness of the sealing resin 6 is made as thin as possible. The volume is reduced to achieve high-density mounting. In addition, there is a package called BGA (Bump / Grid / Array) as a package for mounting a semiconductor device using bumps, which is currently the Japan Electronic Machinery Manufacturers Association (EIAJ).
Standardization is in progress. An example of this BGA package is that of Tessera, Inc. of the United States, which is a package in which a circuit film having bumps arranged in a grid pattern on a semiconductor chip is adhered and electrically connected (Tessera's).
See Compliant Chip TM Technology).

【0005】さらに、半導体装置、特にメモリICにお
ける高密度実装化の方法として、図30および図31に
示すようなZIP(Zigzag・In-like・Package)と呼ばれ
るパッケージがあり、実装面積当たりの実装密度をあげ
る手法として用いられていた。図30はZIPの外形
図、図31はその側面図であり、図において、7はボン
ディングパッド3と電気的に接続されるリードの内、封
止樹脂6より外側の部分にある外部リードである。
Further, as a method for high-density mounting in a semiconductor device, particularly a memory IC, there is a package called ZIP (Zigzag In-like Package) as shown in FIGS. 30 and 31, and mounting per mounting area is performed. It was used as a method of increasing the density. FIG. 30 is an external view of the ZIP, and FIG. 31 is a side view thereof. In the figure, 7 is an external lead outside the sealing resin 6 among the leads electrically connected to the bonding pad 3. .

【0006】ところが、ZIPは貫通孔実装タイプ(基
板に穴を開け、半導体装置の外部リードを挿入して実装
するタイプ)であるため、基板の両面への実装が不可能
であり、最近の表面実装化の流れにより使用されなくな
った。そして、このZIPに代わって新しく提案された
のが、図32〜図34に示すようなSVP(Saface・Ver
tical・Package)と呼ばれる直立表面実装型パッケージ
を有する半導体装置である。図32はSVPの外形図、
図33は図32においてh方向より見た側面図、図34
は図32において線jーj′の部分を切断して示す断面
図であり、図において、8はSVPを立てるために通常
の外部リード7より長く、かつこの外部リード7と同一
方向および逆方向に曲げられたスタンドリードである。
However, since the ZIP is a through-hole mounting type (a type in which a hole is formed in a board and external leads of a semiconductor device are inserted and mounted), it cannot be mounted on both sides of the board, and the recent surface It is no longer used due to the flow of implementation. Then, a new proposal in place of this ZIP is SVP (Saface Ver.) As shown in FIGS.
It is a semiconductor device having an upright surface mount type package called tical package. Figure 32 is an outline drawing of the SVP,
33 is a side view seen from the direction h in FIG. 32, and FIG.
32 is a cross-sectional view taken along the line j-j ′ in FIG. 32, in which 8 is longer than a normal external lead 7 for standing SVP, and is in the same direction as the external lead 7 and in the opposite direction. It is a bent stand lead.

【0007】また、従来の半導体装置の高密度化の手法
として例えば特開平5−309983号公報に記載され
た図35に示すような半導体装置がある。この半導体装
置はメモリカード用の半導体装置であり、ワイアボンデ
ィング法を用いているために、図35Bの上向リード付
き樹脂封止型半導体装置46の場合、上向リード47と
樹脂封止部43による半導体チップ40の樹脂封止面と
の段差は、半導体チップ40上のワイヤ42の高さ約2
00μm,ワイヤ42上の樹脂封止部43の樹脂の厚さ
最小50μm,パッケージの反り等による余裕度を約5
0μmと見積もっても、最小300μmとなる。
Further, as a conventional method for increasing the density of a semiconductor device, there is a semiconductor device as shown in FIG. 35, for example, disclosed in Japanese Patent Laid-Open No. 5-309983. Since this semiconductor device is a semiconductor device for a memory card and uses the wire bonding method, in the case of the resin-sealed semiconductor device 46 with the upward lead shown in FIG. 35B, the upward lead 47 and the resin-sealed portion 43. The height difference of the wire 42 on the semiconductor chip 40 from the resin sealing surface of the semiconductor chip 40 is about 2
00 μm, the minimum resin thickness of the resin sealing portion 43 on the wire 42 is 50 μm, and the margin due to warpage of the package is about 5
Even if it is estimated to be 0 μm, the minimum is 300 μm.

【0008】また、図35Aの下向リード付き樹脂封止
型半導体装置44の場合、ワイヤ42と半導体チップ4
0の端部の短絡を防ぐため、下向リード45はダイパッ
ド41より約200μm半導体チップ40の能動面(上
面)にシフトさせる必要がある。さらに、ダイパッド4
1の下部の樹脂封止部43の樹脂の厚さが200μm必
要であることから、下向リード45と樹脂封止部43に
よる半導体チップ40の樹脂封止面との段差は約400
μmとなり、図35Bの上向リード47の場合より大き
くなる。
Further, in the case of the resin-sealed semiconductor device 44 with the downward lead shown in FIG. 35A, the wire 42 and the semiconductor chip 4 are used.
In order to prevent a short circuit at the end of 0, the downward lead 45 needs to be shifted from the die pad 41 to the active surface (upper surface) of the semiconductor chip 40 by about 200 μm. Furthermore, die pad 4
Since the resin thickness of the resin sealing portion 43 below 1 is 200 μm, the step difference between the downward lead 45 and the resin sealing surface of the semiconductor chip 40 by the resin sealing portion 43 is about 400.
μm, which is larger than that of the upward lead 47 in FIG. 35B.

【0009】[0009]

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、以下のような問題点が
あった。すなわち、まず、特開平1−17933号公報
に示された半導体装置の場合(図28,図29)、半田
バンプ5と半導体チップ2上の電極であるボンディング
パッド3との距離が短く、また、封止樹脂6と半田バン
プ5,接続用導体4等の金属との接着性が悪いため、封
止樹脂6と半田バンプ5,接続用導体4との界面を通し
て水が侵入し、ボンディングパッド3を腐食し、半導体
装置1が不良になるという問題点があった。
Since the conventional semiconductor device is constructed as described above, it has the following problems. That is, first, in the case of the semiconductor device disclosed in Japanese Patent Application Laid-Open No. 1-17933 (FIGS. 28 and 29), the distance between the solder bump 5 and the bonding pad 3 which is an electrode on the semiconductor chip 2 is short, and Since the adhesion between the sealing resin 6 and the metal such as the solder bumps 5 and the connecting conductors 4 is poor, water penetrates through the interface between the sealing resin 6 and the solder bumps 5 and the connecting conductors 4, and the bonding pad 3 is removed. There is a problem that the semiconductor device 1 is corroded and becomes defective.

【0010】また、半田バンプ5とボンディングパッド
3とが1対1で対応するため、半田バンプ5を形成する
ための半田ボール(図示せず)の数がボンディングパッ
ド3の数だけ必要となり、例えば電源供給電極や接地電
極を共有したり、半導体装置1内での回路を形成するこ
とが不可能であるという問題点があった。さらに、基板
上の外部接続用リードパターン上に半導体素子上の電極
を接合させる場合、半導体素子とベース基板に挟まれた
リードパターンと半導体素子上の電極の位置合わせが困
難であるとういう問題点があった。
Further, since the solder bumps 5 and the bonding pads 3 correspond to each other on a one-to-one basis, the number of solder balls (not shown) for forming the solder bumps 5 must be the same as the number of the bonding pads 3. There is a problem in that it is impossible to share the power supply electrode or the ground electrode and to form a circuit in the semiconductor device 1. Further, when the electrodes on the semiconductor element are bonded to the external connection lead pattern on the substrate, it is difficult to align the lead pattern sandwiched between the semiconductor element and the base substrate with the electrodes on the semiconductor element. was there.

【0011】また、半導体チップ上にバンプを格子状に
配列した回路フイルムを接着して電気的に接続したBG
Aのパッケージの場合、半導体チップ上は回路フィルタ
を介して外界環境に接しており、封止樹脂で被膜されて
いないため、回路フィルタの材料、特に図示せずもエラ
ストマ(弾性体)と回路を構成する金属導体,PI(ポ
リイミド)フィルムとを接着する接着剤の純度を上げ、
ボンディングパッドを腐食させるような不純物(クロル
イオン等)を排除する必要がある。また、エラストマ,
PIフィルムは吸湿しやすいためこれらの材料の吸水率
を極力下げないと、半導体装置の実装時半田バンプをリ
フローする際に、エラストマ,PIフィルム中の水分が
爆発的に気化し、エラストマ層やPIフィルムに亀裂等
を生じたり、場合によっては、導体の断線も引き起こす
可能性もある等の問題点があった。
Further, a circuit film having bumps arranged in a grid pattern on a semiconductor chip is adhered and electrically connected to a BG.
In the case of the package A, since the semiconductor chip is in contact with the external environment through the circuit filter and is not coated with the sealing resin, the material of the circuit filter, especially the elastomer (elastic body) and the circuit (not shown) are Increase the purity of the adhesive that bonds the constituent metal conductors and PI (polyimide) film,
It is necessary to eliminate impurities (chlorine ions, etc.) that corrode the bonding pad. Also, the elastomer,
Since the PI film easily absorbs moisture, if the water absorption rate of these materials is not reduced as much as possible, when the solder bumps are reflowed during the mounting of the semiconductor device, the elastomer and the moisture in the PI film are explosively vaporized, and the elastomer layer and PI film There have been problems that the film may be cracked, or the conductor may be broken in some cases.

【0012】また、SVPを有する半導体装置の場合
(図32〜図34)、外部リード7により基板(図示せ
ず)に接続されるが、外部リード7の強度を必要とする
点から、そのリード厚さとして0.125mm、リード幅0.2
5mmが必要となり、その結果、リードピッチは0.5mm
以上が必要となり、特に多ピンパッケージ(多リードパ
ッケージ)の場合には半導体装置の外部リード7が外部
に出ている辺の長さは、そのリードの長さの制限を受け
て、半導体装置のサイズが大きくなる等の問題点があっ
た。また、SVPの外部リード7はパッケージ下面でL
字型に曲がっており、曲がった部分(図34のk部分)
の長さが0.65〜1.20mmとなっている。従って、この外
部リード7の長さがかなり長いので、半導体装置1がそ
の縦構造の偏心等により反った場合には、見かけ上リー
ド幅が増え、外部リード7のリードピッチを広くするこ
とが困難になる等の問題点があった。
Further, in the case of a semiconductor device having an SVP (FIGS. 32 to 34), it is connected to a substrate (not shown) by the external lead 7, but since the strength of the external lead 7 is required, the lead is required. Thickness is 0.125mm, lead width is 0.2
5mm required, resulting in a lead pitch of 0.5mm
The above is required, and particularly in the case of a multi-pin package (multi-lead package), the length of the side where the external lead 7 of the semiconductor device is exposed to the outside is limited by the length of the lead. There was a problem that the size became large. The external lead 7 of the SVP is L on the bottom surface of the package.
It is bent in a letter shape, and the bent part (part k in FIG. 34)
Has a length of 0.65 to 1.20 mm. Therefore, since the length of the external leads 7 is considerably long, when the semiconductor device 1 is warped due to the eccentricity of its vertical structure, the lead width is apparently increased, and it is difficult to widen the lead pitch of the external leads 7. There was a problem such as becoming.

【0013】また、通常表面実装型半導体装置を基板上
に実装する際には、スクリーン印刷法により半田ペース
トを印刷し、その半田ペーストと実装する表面実装型半
導体装置のリードとを粘着させた後リフローにより半田
ペースト内の半田を熔融させて接続するが、この場合に
は半田ペーストの厚みの最大値は、スクリーンマスクの
厚さにほぼ等しくなり、現在使用されているスクリーン
マスクが厚さ200μmである。従って、上述した特開
平5ー309983号公報に示された半導体装置の場合
(図35)は、実装時に基板とリードとの段差(最小3
00μm)が半田ペーストの厚さ(200μm)よりも
大きいため、リードと半田の接合が不可能になる、つま
り、単体での表面実装は不可能になるという問題点があ
った。
Further, when mounting the surface-mounting type semiconductor device on a substrate, solder paste is usually printed by a screen printing method, and after the soldering paste is adhered to the leads of the surface-mounting type semiconductor device to be mounted. The solder in the solder paste is melted and connected by reflow. In this case, the maximum thickness of the solder paste is almost equal to the thickness of the screen mask, and the currently used screen mask has a thickness of 200 μm. is there. Therefore, in the case of the semiconductor device disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 5-309983 (FIG. 35), a step (minimum 3) between the substrate and the lead during mounting.
Since the thickness (00 μm) is larger than the thickness (200 μm) of the solder paste, there is a problem in that the leads cannot be joined to the solder, that is, surface mounting alone is impossible.

【0014】この対策として、スクリーンマスクの厚さ
を300μm以上とすることが考えられるが、この場
合、半田の厚さが厚くなり、また、半田印刷幅も広くな
るため、つまり、スクリーンマスクの開口幅は最小でも
スクリーンマスクの厚さは必要であるため、リードピッ
チの小さい多ピンQFP(Quad・Flat・Package)と呼ば
れるケースの四辺の方向からリードの出ているパッケー
ジ等で用いられている0.5mmリードピッチの半導体装
置および狭ピッチTSOP(Thin・Small・Outline・Packa
ge)と呼ばれるケースの二辺の方向からリードの出てい
るパッケージおよびQFPのような0.65mmリードピッ
チの半導体装置には半田量が多すぎてリード間の半田ブ
リッジが発生し、短絡不良となるため、汎用性がなくな
る等の問題点があった。
As a countermeasure against this, it is conceivable to make the thickness of the screen mask 300 μm or more. In this case, however, the thickness of the solder becomes thicker and the solder printing width becomes wider, that is, the opening of the screen mask. Since the width of the screen mask is required even if the width is the minimum, it is used in packages such as multi-pin QFP (Quad / Flat / Package), which has a small lead pitch and has leads extending from the four sides of the case. mm lead pitch semiconductor device and narrow pitch TSOP (Thin / Small / Outline / Packa)
ge), which has leads extending from the two sides of the case and a semiconductor device with a 0.65 mm lead pitch such as QFP, has too much solder and leads to a solder bridge between leads, resulting in a short circuit failure. Therefore, there is a problem that versatility is lost.

【0015】この発明はこのような問題点を解決するた
めになされたもので、耐湿性等信頼性が高くかつ高密度
の実装が可能な汎用性の優れた半導体装置およびその製
造方法並びに実装方法を得ることを目的とする。
The present invention has been made to solve the above problems, and has a versatile semiconductor device having high reliability such as moisture resistance and capable of high-density mounting, and a manufacturing method and mounting method thereof. Aim to get.

【0016】[0016]

【課題を解決するための手段】請求項1の発明に係る半
導体装置は、半導体チップ上に設けられ、導体層を有す
る接着部材と、半導体チップ上に設けられた電極と導体
層とを電気的に接続する接続部材と、半導体チップ、導
体層、接着部材および接続部材を樹脂封止する封止部材
と、この封止部材に設けられた開口部を介して導体層に
接続された外部電極とを備えたものである。
According to another aspect of the present invention, there is provided a semiconductor device in which an adhesive member provided on a semiconductor chip and having a conductor layer, an electrode provided on the semiconductor chip, and a conductor layer are electrically connected. To the semiconductor chip, the conductor layer, the adhesive member and the connecting member with a sealing member, and an external electrode connected to the conductor layer through an opening provided in the sealing member. It is equipped with.

【0017】請求項2の発明に係る半導体装置は、半導
体チップ上に設けられ、導体層を有する接着部材と、半
導体チップ上に設けられた電極と導体層とを電気的に接
続する接続部材と、導体層上に設けられた金属突起と、
半導体チップ、導体層、接着部材、接続部材および金属
突起を樹脂封止しかつ金属突起を一部外部に露出させる
封止部材と、外部に露出した金属突起と接続された外部
電極とを備えたものである。
According to a second aspect of the present invention, there is provided a semiconductor device comprising: an adhesive member provided on a semiconductor chip and having a conductor layer; and a connecting member electrically connecting the electrode provided on the semiconductor chip and the conductor layer. A metal protrusion provided on the conductor layer,
A semiconductor chip, a conductor layer, an adhesive member, a connecting member, and a sealing member that seals the metal protrusion with resin and exposes the metal protrusion to the outside, and an external electrode connected to the metal protrusion exposed to the outside. It is a thing.

【0018】請求項3の発明に係る半導体装置は、請求
項1または2の発明において、接着部材は、半導体チッ
プ上に設けられた電極と接続される櫛形導体層を有する
ものである。
A semiconductor device according to a third aspect of the present invention is the semiconductor device according to the first or second aspect, wherein the adhesive member has a comb-shaped conductor layer connected to an electrode provided on the semiconductor chip.

【0019】請求項4の発明に係る半導体装置は、請求
項2の発明において、金属突起が露出している封止部材
の部分の周囲に凹部を設け、該凹部に上記外部電極の一
部を食い込ませたものである。
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the second aspect, wherein a recess is provided around a portion of the sealing member where the metal protrusion is exposed, and the recess has a portion of the external electrode. It is a bite.

【0020】請求項5の発明に係る半導体装置は、請求
項3の発明において、櫛形導体層は、電源供給または接
地電位用配線として使用されるものである。
A semiconductor device according to a fifth aspect of the present invention is the semiconductor device according to the third aspect, wherein the comb-shaped conductor layer is used as a power supply or ground potential wiring.

【0021】請求項6の発明に係る半導体装置は、半導
体チップの一側に設けられ、導体層を有する接着部材
と、半導体チップの他側に設けられた電極と導体層とを
電気的に接続する接続部材と、半導体チップ、導体層、
接着部材および接続部材を樹脂封止しかつ導体層の一側
を外部に露出させる封止部材とを備えたものである。
A semiconductor device according to a sixth aspect of the present invention electrically connects an adhesive member provided on one side of a semiconductor chip and having a conductor layer to an electrode and a conductor layer provided on the other side of the semiconductor chip. Connecting member, semiconductor chip, conductor layer,
And a sealing member that seals the adhesive member and the connecting member with resin and exposes one side of the conductor layer to the outside.

【0022】請求項7の発明に係る半導体装置は、請求
項6の発明において、封止部材上に半導体チップの能動
面と垂直な方向に突出して設けられた支持部材を備えた
ものである。
A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to the sixth aspect, further comprising a supporting member provided on the sealing member so as to project in a direction perpendicular to the active surface of the semiconductor chip.

【0023】請求項8の発明に係る半導体装置は、半導
体チップと離隔して設けられた導電性の基本部材と、こ
の基本部材上に設けられ、導体層を有する接着部材と、
半導体チップに設けられた第1および第2の電極と導体
層および基本部材とをそれぞれ電気的に接続する接続部
材と、半導体チップ、基本部材、導体層、接着部材およ
び接続部材を樹脂封止しかつ少なくとも基本部材と導体
層の一側を外部に露出させる封止部材とを備えたもので
ある。
According to another aspect of the present invention, there is provided a semiconductor device, wherein a conductive basic member is provided separately from the semiconductor chip, and an adhesive member is provided on the basic member and has a conductor layer.
The semiconductor chip, the basic member, the conductor layer, the adhesive member and the connecting member are resin-sealed with the connecting member electrically connecting the first and second electrodes provided on the semiconductor chip to the conductor layer and the basic member, respectively. In addition, at least the basic member and the sealing member that exposes one side of the conductor layer to the outside are provided.

【0024】請求項9の発明に係る半導体装置は、半導
体チップと離隔して設けられた導電性の基本部材と、半
導体チップと離隔しかつ基本部材の周囲に設けられた導
電性の環状部材と、基本部材上に設けられ、導体層を有
する接着部材と、半導体チップに設けられた第1、第2
および第3の電極と導体層、基本部材および環状部材と
をそれぞれ電気的に接続する接続部材と、半導体チッ
プ、基本部材、環状部材、導体層、接着部材および接続
部材を樹脂封止しかつ少なくとも基本部材、環状部材お
よび導体層の一側を外部に露出させる封止部材とを備え
たものである。
According to a ninth aspect of the present invention, there is provided a semiconductor device, wherein a conductive basic member is provided separately from the semiconductor chip, and a conductive annular member is provided apart from the semiconductor chip and provided around the basic member. , An adhesive member provided on the basic member and having a conductor layer, and first and second adhesive members provided on the semiconductor chip.
And a connection member for electrically connecting the third electrode to the conductor layer, the basic member and the annular member, respectively, and a semiconductor chip, the basic member, the annular member, the conductor layer, the adhesive member and the connection member are resin-sealed and at least And a sealing member that exposes one side of the conductor layer to the outside.

【0025】請求項10の発明に係る半導体装置は、請
求項8または9の発明において、封止部材より露出した
基本部材は支持用として使用されるものである。
According to a tenth aspect of the invention, in the semiconductor device according to the eighth or ninth aspect, the basic member exposed from the sealing member is used for supporting.

【0026】請求項11の発明に係る半導体装置は、請
求項8〜10の発明において、導体層は上記封止部材よ
り0.2〜1.0mm程度露出されるものである。
A semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to the eighth aspect, wherein the conductor layer is exposed by about 0.2 to 1.0 mm from the sealing member.

【0027】請求項12の発明に係る半導体装置は、請
求項8〜11の発明において、封止部材より露出した導
体層は実装時基板上の配線と接続する際のヒンジとして
使用されるものである。
A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the eighth aspect, wherein the conductor layer exposed from the sealing member is used as a hinge when connecting to the wiring on the board during mounting. is there.

【0028】請求項13の発明に係る半導体装置は、請
求項8〜12の発明において、基本部材は接地電位用と
して使用されるものである。
A semiconductor device according to a thirteenth aspect of the present invention is the semiconductor device according to the eighth aspect, wherein the basic member is used for ground potential.

【0029】請求項14の発明に係る半導体装置は、請
求項8〜13の発明において、基本部材は上記電極側の
表面を露出され、該露出部がワイヤボンディング可能と
されているものである。
A semiconductor device according to a fourteenth aspect of the present invention is the semiconductor device according to the eighth aspect, wherein the surface of the basic member on the electrode side is exposed and the exposed portion is wire-bondable.

【0030】請求項15の発明に係る半導体装置は、請
求項8〜14の発明において、封止部材の上記基本部材
が露出している部分に溝部を設けたものである。
A semiconductor device according to a fifteenth aspect of the present invention is the semiconductor device according to the eighth aspect, wherein a groove is provided in a portion of the sealing member where the basic member is exposed.

【0031】請求項16の発明に係る半導体装置は、請
求項8〜15の発明において、基本部材と環状部材は電
極を挟んで相互に対向した位置に配置されるものであ
る。
A semiconductor device according to a sixteenth aspect of the present invention is the semiconductor device according to any of the eighth to fifteenth aspects, wherein the basic member and the annular member are arranged at positions facing each other with the electrode interposed therebetween.

【0032】請求項17の発明に係る半導体装置は、請
求項8〜16の発明において、基本部材と環状部材は、
電源供給または接地電位用配線として使用されるもので
ある。
A semiconductor device according to a seventeenth aspect of the present invention is the semiconductor device according to the eighth aspect, wherein the basic member and the annular member are
It is used as a wiring for power supply or ground potential.

【0033】請求項18の発明に係る半導体装置は、請
求項8〜17の発明において、基本部材の一側は、接着
部材および導体層に対向する部分以外は削除されて櫛形
をなすものである。
A semiconductor device according to an eighteenth aspect of the present invention is the semiconductor device according to the eighteenth to seventeenth aspects, wherein one side of the basic member has a comb shape in which portions other than the portions facing the adhesive member and the conductor layer are removed. .

【0034】請求項19の発明に係る半導体装置は、半
導体チップ上に設けられた接着部材と、この接着部材よ
り延在して半導体チップ上に設けられた電極と電気的に
接続される配線部材と、半導体チップ、接着部材および
配線部材を樹脂封止する封止部材と、この封止部材に設
けられた開口部を介して配線部材に接続された外部電極
とを備えたものである。
According to a nineteenth aspect of the present invention, in a semiconductor device, an adhesive member provided on a semiconductor chip and a wiring member extending from the adhesive member and electrically connected to an electrode provided on the semiconductor chip. And a sealing member for sealing the semiconductor chip, the adhesive member and the wiring member with a resin, and an external electrode connected to the wiring member through an opening provided in the sealing member.

【0035】請求項20の発明に係る半導体装置は、半
導体チップ上に設けられた接着部材と、この接着部材よ
り延在して半導体チップ上に設けられた電極と電気的に
接続される配線部材と、半導体チップ、接着部材および
配線部材を樹脂封止しかつ配線部材の一側を所定の段差
を持って外部に露出させる封止部材とを備えたものであ
る。
A semiconductor device according to a twentieth aspect of the present invention is an adhesive member provided on a semiconductor chip, and a wiring member extending from the adhesive member and electrically connected to an electrode provided on the semiconductor chip. And a sealing member that seals the semiconductor chip, the adhesive member, and the wiring member with resin and exposes one side of the wiring member to the outside with a predetermined step.

【0036】請求項21の発明に係る半導体装置は、請
求項19または20の発明において、接着部材がTAB
テープであるものである。
The semiconductor device according to the invention of claim 21 is the semiconductor device according to claim 19 or 20, wherein the adhesive member is TAB.
It is a tape.

【0037】請求項22の発明に係る半導体装置は、請
求項19または20の発明において、接着部材がTAB
テープであり、該TABテープ上の配線部材を外部電極
として用いるものである。
A semiconductor device according to a twenty-second aspect of the present invention is the semiconductor device according to the nineteenth or twentieth aspect, wherein the adhesive member is TAB.
This is a tape, and the wiring member on the TAB tape is used as an external electrode.

【0038】請求項23の発明に係る半導体装置は、請
求項20〜22の発明において、封止部材は実装時基板
と対接する部分に該基板の配線と嵌合する位置決め凹部
を有するものである。
A semiconductor device according to a twenty-third aspect of the present invention is the semiconductor device according to the twenty-third aspect of the present invention, wherein the sealing member has a positioning recess for fitting with the wiring of the substrate at a portion which is in contact with the substrate during mounting. .

【0039】請求項24の発明に係る半導体装置は、請
求項20〜23の発明において、封止部材は実装時基板
と対接する部分に基板上のスルーホール等との干渉を防
ぐための逃げ凹部を有するものである。
A semiconductor device according to a twenty-fourth aspect of the present invention is the semiconductor device according to the twenty-third aspect of the present invention, wherein the sealing member is a relief recess for preventing interference with a through hole or the like on the substrate at a portion facing the substrate during mounting. Is to have.

【0040】請求項25の発明に係る半導体装置の製造
方法は、半導体チップ上に導体層を有する接着部材を貼
着す工程と、半導体チップ上に電極を形成する工程と、
電極と上記導体層とを電気的に接続する工程と、半導体
チップ、導体層、接着部材を樹脂封止する工程と、この
封止樹脂に上記導体層に達する開口部を形成する工程
と、開口部に半田を充填して外部電極を形成する工程と
を含むものである。
According to a twenty-fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a step of adhering an adhesive member having a conductor layer on a semiconductor chip, a step of forming electrodes on the semiconductor chip.
A step of electrically connecting the electrode and the conductor layer, a step of resin-sealing the semiconductor chip, the conductor layer, and an adhesive member, a step of forming an opening reaching the conductor layer in the sealing resin, and an opening And filling the portion with solder to form an external electrode.

【0041】請求項26の発明に係る半導体装置の製造
方法は、請求項25の発明において、開口部を樹脂封止
する際の金型に設けられた突起により形成するものであ
る。
According to a twenty-sixth aspect of the present invention, in the semiconductor device manufacturing method according to the twenty-fifth aspect of the present invention, the openings are formed by projections provided on a mold for resin sealing.

【0042】請求項27の発明に係る半導体装置の製造
方法は、請求項25または26の発明において、開口部
を樹脂封止する際の金型に設けられた突起を導体層に所
定の深さだけ押し込むように半導体チップと接着部材を
金型内に設置し、樹脂封止するものである。
According to a twenty-seventh aspect of the present invention, in the method of manufacturing a semiconductor device according to the twenty-fifth aspect or the twenty-sixth aspect of the present invention, the protrusion provided on the mold for resin-sealing the opening has a predetermined depth in the conductor layer. The semiconductor chip and the adhesive member are placed in a mold so that they are only pushed in, and are resin-sealed.

【0043】請求項28の発明に係る半導体装置の製造
方法は、請求項25〜27の発明において、半導体チッ
プと接着部材を金型内に設置する位置を保持するのに、
接着部材の架橋部を金型で挟むようにしたものである。
According to a twenty-eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device according to the twenty-fifth to twenty-seventh aspects of the present invention, in which the semiconductor chip and the adhesive member are held in positions to be set in a mold.
The cross-linking portion of the adhesive member is sandwiched between molds.

【0044】請求項29の発明に係る半導体装置の製造
方法は、請求項25〜28の発明において、開口部に半
田ボールを乗せ、リフローにより外部電極を形成するも
のである。
According to a twenty-ninth aspect of the present invention, in the method of manufacturing a semiconductor device according to the twenty-fifth to twenty-eighth aspects, solder balls are placed in the openings and the external electrodes are formed by reflow.

【0045】請求項30の発明に係る半導体装置の製造
方法は、半導体チップ上に導体層を有する接着部材を貼
着する工程と、半導体チップ上に電極を形成する工程
と、電極と導体層とを電気的に接続する工程と、導体層
上にワイヤボンディング法により金属突起を形成する工
程と、半導体チップ、導体層、接着部材および金属突起
を樹脂封止しかつ金属突起を一部外部に露出させる工程
と、外部に露出した金属突起と接続される外部電極を形
成する工程とを含むものである。
According to a thirtieth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of attaching an adhesive member having a conductor layer on a semiconductor chip, a step of forming an electrode on the semiconductor chip, an electrode and a conductor layer. Electrically connecting the semiconductor chip, the step of forming metal projections on the conductor layer by a wire bonding method, the semiconductor chip, the conductor layer, the adhesive member and the metal projections are resin-sealed and the metal projections are partially exposed to the outside. And a step of forming an external electrode connected to the metal protrusion exposed to the outside.

【0046】請求項31の発明に係る半導体装置の製造
方法は、請求項30の発明において、金属突起を一部外
部に露出させる工程において、金属突起の高さを、該金
属突起の切り残し量を調整し、該調整された金属突起を
樹脂封止の際に樹脂封止金型に押し付けるように樹脂封
止して金属突起の一部を露出させるものである。
According to a thirty-first aspect of the present invention, in the method of manufacturing a semiconductor device according to the thirtieth aspect, in the step of exposing a part of the metal projection to the outside, the height of the metal projection is determined by the uncut amount of the metal projection. Is adjusted, and the adjusted metal protrusion is resin-sealed so as to be pressed against a resin-sealing mold at the time of resin-sealing to expose a part of the metal protrusion.

【0047】請求項32の発明に係る半導体装置の製造
方法は、半導体チップの一側に導体層を有する接着部材
を貼着する工程と、半導体チップの他側に電極を形成す
る工程と、電極と導体層とを電気的に接続する工程と、
半導体チップ、導体層および接着部材を樹脂封止しかつ
導体層の一側を外部に露出させる工程とを含むものであ
る。
According to a thirty-second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a step of attaching an adhesive member having a conductor layer on one side of a semiconductor chip, a step of forming an electrode on the other side of the semiconductor chip, and an electrode. And a step of electrically connecting the conductor layer,
And the step of sealing the semiconductor chip, the conductor layer and the adhesive member with resin and exposing one side of the conductor layer to the outside.

【0048】請求項33の発明に係る半導体装置の製造
方法は、半導体チップと離隔して導電性の基本部材を配
置する工程と、基本部材上に導体層を有する接着部材を
貼着する工程と、半導体チップに第1および第2の電極
を形成する工程と、第1および第2の電極とと導体層お
よび基本部材とをそれぞれ電気的に接続する工程と、半
導体チップ、基本部材、導体層および接着部材を樹脂封
止しかつ少なくとも上記基本部材と上記導体層の一側を
外部に露出させる工程とを含むものである。
According to a thirty-third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a step of disposing a conductive basic member apart from a semiconductor chip, and a step of adhering an adhesive member having a conductor layer on the basic member. A step of forming first and second electrodes on a semiconductor chip, a step of electrically connecting the first and second electrodes to a conductor layer and a basic member, respectively, a semiconductor chip, a basic member, and a conductor layer And a step of sealing the adhesive member with resin and exposing at least the basic member and one side of the conductor layer to the outside.

【0049】請求項34の発明に係る半導体装置の製造
方法は、半導体チップと離隔して導電性の基本部材を配
置する工程と、半導体チップと離隔しかつ基本部材の周
囲に導電性の環状部材を配置する工程と、基本部材上に
導体層を有する接着部材を貼着する工程と、半導体チッ
プに第1、第2および第3の電極を形成する工程と、第
1、第2および第3の電極と導体層、基本部材および環
状部材とをそれぞれ電気的に接続する工程と、半導体チ
ップ、基本部材、環状部材、導体層および接着部材を樹
脂封止しかつ少なくとも上記基本部材、環状部材および
上記導体層の一側を外部に露出させる工程とを含むもの
である。
According to a thirty-fourth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of disposing a conductive basic member apart from a semiconductor chip, and a conductive annular member spaced from the semiconductor chip and surrounding the basic member. Arranging, a step of adhering an adhesive member having a conductor layer on the basic member, a step of forming first, second and third electrodes on the semiconductor chip, and first, second and third Electrically connecting the electrode and the conductor layer, the basic member and the annular member, respectively, and sealing the semiconductor chip, the basic member, the annular member, the conductor layer and the adhesive member with a resin, and at least the basic member, the annular member and And a step of exposing one side of the conductor layer to the outside.

【0050】請求項35の発明に係る半導体装置の製造
方法は、半導体チップ上に接着部材を貼着する工程と、
半導体チップ上に電極を形成する工程と、電極と接着部
材より延在する配線部材を電気的に接続する工程と、半
導体チップ、接着部材および配線部材を樹脂封止する工
程と、この封止樹脂に導体層に達する開口部を形成する
工程と、開口部に半田を充填して外部電極を形成する工
程とを含むものである。
A method of manufacturing a semiconductor device according to a thirty-fifth aspect of the present invention comprises a step of attaching an adhesive member on a semiconductor chip,
A step of forming an electrode on the semiconductor chip, a step of electrically connecting the electrode and a wiring member extending from the adhesive member, a step of resin-sealing the semiconductor chip, the adhesive member and the wiring member, and a sealing resin And a step of forming an external electrode by filling the opening with solder and forming an external electrode.

【0051】請求項36の発明に係る半導体装置の製造
方法は、半導体チップ上に接着部材を貼着する工程と、
半導体チップ上に電極を形成する工程と、電極と接着部
材より延在する配線部材を電気的に接続する工程と、こ
の接着部材より延在して半導体チップ上に設けられた電
極と電気的に接続される配線部材と、半導体チップ、接
着部材および配線部材を樹脂封止しかつ配線部材の一側
を所定の段差を持って外部に露出させる工程とを含むも
のである。
According to a thirty-sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising a step of attaching an adhesive member on a semiconductor chip,
A step of forming an electrode on the semiconductor chip, a step of electrically connecting the electrode and a wiring member extending from the adhesive member, and an electrode electrically extending from the adhesive member and provided on the semiconductor chip. The method includes a wiring member to be connected, a step of resin-sealing the semiconductor chip, the adhesive member and the wiring member and exposing one side of the wiring member to the outside with a predetermined step.

【0052】請求項37の発明に係る半導体装置の実装
方法は、半導体装置を基板に対して垂直に配置し、半導
体装置内の半導体チップの一側に貼着された接着部材上
の導体層を基板の配線と電気的に接続するようにしたも
のである。
According to a thirty-seventh aspect of the present invention, in a method for mounting a semiconductor device, the semiconductor device is arranged perpendicular to a substrate, and a conductor layer on an adhesive member attached to one side of a semiconductor chip in the semiconductor device is provided. It is designed to be electrically connected to the wiring of the substrate.

【0053】請求項38の発明に係る半導体装置の実装
方法は、半導体装置の樹脂封止部分に設けられた溝部の
内、基本部材を曲げるために用いられていない溝部に隣
接する他の半導体装置の支持部材を潜り込ませて実装す
るようにしたものである。
In the semiconductor device mounting method according to a thirty-eighth aspect of the present invention, another semiconductor device adjacent to a groove portion which is not used for bending the basic member among the groove portions provided in the resin-sealed portion of the semiconductor device is provided. The support member of (1) is embedded in the mounting member.

【0054】請求項39の発明に係る半導体装置の実装
方法は、半導体装置の半導体チップ表面側の樹脂表面に
配線部材の貼着された接着部材を露出させるように樹脂
封止し、接着部材上の配線部材と半導体装置の樹脂表面
との段差を所定値に抑え、接着部材上の配線部材を基板
に対向するように実装し、接着部材上の配線部材を基板
の配線と電気的に接続するようにしたものである。
According to a 39th aspect of the present invention, in a method for mounting a semiconductor device, resin is sealed so that an adhesive member to which a wiring member is attached is exposed on a resin surface on a semiconductor chip surface side of the semiconductor device. The wiring member on the adhesive member is mounted so as to face the substrate, and the wiring member on the adhesive member is electrically connected to the wiring on the substrate. It was done like this.

【0055】[0055]

【作用】請求項1の発明においては、半導体チップおよ
びその上の接着部材の周囲が封止されて耐湿性がよくな
り、また、外部電極と半導体チップ上の電極の長くして
封止樹脂と内蔵される接着部材、その上の導体層、接続
部材等との界面を伝わって侵入する水分の進行が抑えら
れ、さらに、耐湿性が向上される。また、実装密度の向
上と小型化が可能となる。
According to the first aspect of the present invention, the periphery of the semiconductor chip and the adhesive member on the semiconductor chip is sealed to improve moisture resistance, and the external electrodes and the electrodes on the semiconductor chip are lengthened to form a sealing resin. The progress of moisture that penetrates through the interface with the built-in adhesive member, the conductor layer thereon, the connecting member, etc. is suppressed, and the moisture resistance is further improved. Further, the packaging density can be improved and the size can be reduced.

【0056】請求項2の発明においては、半導体チップ
およびその上の接着部材の周囲が封止されて耐湿性がよ
くなり、また、外部電極と半導体チップ上の電極の長く
して封止樹脂と内蔵される接着部材、その上の導体層、
接続部材等との界面を伝わって侵入する水分の進行が抑
えられ、さらに、耐湿性が向上される。また、実装密度
の向上と小型化が可能となる。
According to the second aspect of the present invention, the periphery of the semiconductor chip and the adhesive member on the semiconductor chip is sealed to improve the moisture resistance, and the external electrodes and the electrodes on the semiconductor chip are lengthened to form a sealing resin. Adhesive member built in, conductor layer on it,
The progress of moisture that has entered the interface with the connecting member and the like is suppressed, and the moisture resistance is further improved. Further, the packaging density can be improved and the size can be reduced.

【0057】請求項3の発明においては、接着部材が櫛
形導体層を有するので、外部電極よりの信号を半導体チ
ップ上の種々の電極へ伝達することが可能となる。
In the third aspect of the invention, since the adhesive member has the comb-shaped conductor layer, it is possible to transmit the signal from the external electrode to various electrodes on the semiconductor chip.

【0058】請求項4の発明においては、金属突起が露
出している封止部材の部分に凹部を設けたので、外部電
極形成時に半田が凹部に流れ込み、封止樹脂と半田が機
械的にかみあい、半田と封止樹脂さらには外部電極と金
属突起との結合を強固にできる。
In the invention of claim 4, since the recess is provided in the portion of the sealing member where the metal projection is exposed, the solder flows into the recess when the external electrode is formed, and the sealing resin and the solder mechanically mesh with each other. The connection between the solder, the sealing resin, and the external electrode and the metal protrusion can be strengthened.

【0059】請求項5の発明においては、櫛形導体層を
電源供給用と接地用として使用できるので、半導体チッ
プ内での配線の引き回しが不要になり、配線によりイン
ダクタンスの増加が抑制されて半導体装置の動作の高速
化が可能となる。
In the invention of claim 5, since the comb-shaped conductor layer can be used for supplying power and for grounding, it is not necessary to lay out the wiring in the semiconductor chip, and the wiring suppresses an increase in inductance and the semiconductor device. It is possible to speed up the operation of.

【0060】請求項6の発明においては、垂直実装によ
る実装密度の向上を図ることができる。
According to the sixth aspect of the invention, the mounting density can be improved by vertical mounting.

【0061】請求項7の発明においては、支持部材によ
り半導体装置を基板に対して垂直に立てることができる
ので、実装が容易となり、実装性、自立性の向上を図る
ことができる。
According to the seventh aspect of the invention, since the semiconductor device can be erected vertically with respect to the substrate by the supporting member, the mounting becomes easy, and the mountability and the self-supporting property can be improved.

【0062】請求項8の発明においては、半導体チップ
の周囲は比較的接着力が強く、吸水率の低い封止樹脂で
覆われているため、実装時の熱により実装までに吸湿し
た水の爆発による界面剥離やそれに伴う接続部材の破断
が起こりにくくなり、製品の信頼性が向上する。
In the eighth aspect of the invention, since the periphery of the semiconductor chip is covered with the sealing resin having a relatively strong adhesive force and a low water absorption rate, the water absorbed by the heat during mounting explodes. The interface peeling and the resulting breakage of the connecting member are less likely to occur, and the reliability of the product is improved.

【0063】請求項9の発明においては、半導体チップ
内での配線の引き回しが不要になり、配線によりインダ
クタンスの増加が抑制されて半導体装置の動作の高速化
が可能となり、電気特性が向上する。
According to the invention of claim 9, it is not necessary to lay out the wiring in the semiconductor chip, the wiring suppresses the increase of the inductance, and the operation speed of the semiconductor device can be increased, thereby improving the electric characteristics.

【0064】請求項10の発明においては、基本部材を
支持用として使用するため、半導体装置の自立性を向上
することができる。
In the tenth aspect of the invention, since the basic member is used for supporting, the self-supporting property of the semiconductor device can be improved.

【0065】請求項11の発明においては、導体層が封
止部材より露出しているので、導体層と基板の配線を容
易に接続することができ、半田付けによるオープン不良
が防止される。
In the eleventh aspect of the invention, since the conductor layer is exposed from the sealing member, the conductor layer and the wiring of the substrate can be easily connected, and the open defect due to soldering can be prevented.

【0066】請求項12の発明においては、導体層をヒ
ンジとして使用できるので、実装性、信頼性の向上を図
ることができる。
According to the twelfth aspect of the invention, since the conductor layer can be used as a hinge, the mountability and reliability can be improved.

【0067】請求項13の発明においては、基本部材を
接地電位用として使用できるので、半導体チップ内での
配線の引き回しが不要になり、配線によりインダクタン
スの増加が抑制されて半導体装置の動作の高速化が可能
となる。
According to the thirteenth aspect of the present invention, since the basic member can be used for ground potential, it is not necessary to route the wiring within the semiconductor chip, and the wiring suppresses an increase in the inductance, and the semiconductor device operates at high speed. Can be realized.

【0068】請求項14の発明においては、基本部材の
露出部をワイヤボンディングできるので、半導体チップ
内での配線の引き回しが不要になり、配線によりインダ
クタンスの増加が抑制されて半導体装置の動作の高速化
が可能となり、また、電気特性の向上、製法の簡易化を
図ることができる。
According to the fourteenth aspect of the present invention, since the exposed portion of the basic member can be wire-bonded, it is not necessary to route the wiring within the semiconductor chip, and the wiring suppresses an increase in inductance, and the semiconductor device operates at high speed. It is also possible to improve the electrical characteristics and simplify the manufacturing method.

【0069】請求項15の発明においては、封止部材の
基本部材の露出している所に溝部を設けたので、半導体
装置の実装ピッチが小さくなり、高密度実装が可能とな
り、また、実装性を向上できる。
According to the fifteenth aspect of the present invention, since the groove portion is provided in the exposed portion of the basic member of the sealing member, the mounting pitch of the semiconductor device can be reduced, high density mounting can be performed, and the mountability can be improved. Can be improved.

【0070】請求項16の発明においては、電極を挟ん
で基本部材と環状部材を配置したので、半導体チップ内
での配線が短くなって、半導体チップ内での信号の遅延
が減少し、また、配線によりインダクタンス量が減少し
て半導体装置の動作の高速化が可能となり、電気特性の
向上を図ることができる。
According to the sixteenth aspect of the present invention, since the basic member and the annular member are arranged with the electrodes sandwiched therebetween, the wiring within the semiconductor chip is shortened and the signal delay within the semiconductor chip is reduced. The wiring reduces the amount of inductance, speeding up the operation of the semiconductor device, and improving electrical characteristics.

【0071】請求項17の発明においては、基本部材と
環状部材を電源供給用と接地用に使用できるので、半導
体チップ内での配線が短くなって、半導体チップ内での
信号の遅延が減少し、また、配線によりインダクタンス
量が減少して半導体装置の動作の高速化が可能となり、
電気特性の向上を図ることができる。
In the seventeenth aspect of the invention, since the basic member and the annular member can be used for power supply and grounding, the wiring within the semiconductor chip is shortened and the signal delay within the semiconductor chip is reduced. In addition, the wiring reduces the amount of inductance, enabling faster operation of the semiconductor device.
The electrical characteristics can be improved.

【0072】請求項18の発明においては、基本部材の
一側を櫛形としたので、封止樹脂と基本部材の密着性が
向上し、水分の侵入を抑制し、耐湿性の劣化を防ぐこと
ができる。
According to the eighteenth aspect of the present invention, since one side of the basic member is formed in a comb shape, the adhesion between the sealing resin and the basic member is improved, the ingress of water is suppressed, and the deterioration of moisture resistance is prevented. it can.

【0073】請求項19の発明においては、半導体装置
の小型化、実装密度の向上、信頼性の向上を図ることが
できる。
According to the nineteenth aspect of the invention, it is possible to reduce the size of the semiconductor device, improve the packaging density, and improve the reliability.

【0074】請求項20の発明においては、半導体装置
の小型化、実装密度の向上、信頼性の向上を図ることが
できる。
According to the twentieth aspect of the invention, the semiconductor device can be downsized, the packaging density can be improved, and the reliability can be improved.

【0075】請求項21の発明においては、接着部材と
してTABテープを用いるので、半導体装置の小型化に
寄与できる。
According to the twenty-first aspect of the invention, since the TAB tape is used as the adhesive member, it is possible to contribute to miniaturization of the semiconductor device.

【0076】請求項22の発明においては、接着部材と
してTABテープを用い、このTABテープ上の配線部
材を外部電極としても利用できるので、封止樹脂の厚さ
を薄くすることができる。
According to the twenty-second aspect of the present invention, since the TAB tape is used as the adhesive member and the wiring member on the TAB tape can be used as the external electrode, the thickness of the sealing resin can be reduced.

【0077】請求項23の発明においては、封止部材に
位置決め凹部を設けたので、配線処理が容易となり実装
性が向上する。
In the twenty-third aspect of the invention, since the positioning recess is provided in the sealing member, the wiring process is facilitated and the mountability is improved.

【0078】請求項24の発明においては、封止部材に
逃げ凹部を設けたので、位置決め凹部で概略位置合わせ
された場所から適正な実装位置へ動く、セルフアライメ
ントが可能になる。
According to the twenty-fourth aspect of the invention, since the escape recess is provided in the sealing member, it is possible to perform self-alignment in which the sealing member moves from a position roughly aligned with the positioning recess to an appropriate mounting position.

【0079】請求項25の発明においては、製造工程の
簡略化を図ることができる。
In the twenty-fifth aspect of the invention, the manufacturing process can be simplified.

【0080】請求項26の発明においては、開口部を樹
脂封止金型の突起を利用して形成するので、製造が容易
となる。
In the twenty-sixth aspect of the invention, the opening is formed by utilizing the protrusion of the resin-sealing die, so that the manufacturing becomes easy.

【0081】請求項27の発明においては、導体層上の
封止樹脂ばりが発生して導体層と外部電極との導電性を
損なうことが防止される。
According to the twenty-seventh aspect of the present invention, it is possible to prevent the occurrence of the sealing resin burr on the conductor layer and impair the conductivity between the conductor layer and the external electrode.

【0082】請求項28の発明においては、半導体チッ
プと接着部材の位置決めの際に、接着部材の架橋部を金
型で挟むので、製造が容易となる。
According to the twenty-eighth aspect of the present invention, since the bridge portion of the adhesive member is sandwiched between the molds when the semiconductor chip and the adhesive member are positioned, manufacturing is facilitated.

【0083】請求項29の発明においては、外部電極の
形成を、開口部に半田ボールを乗せて行うので、製造工
程の簡略化を図ることができる。
According to the twenty-ninth aspect of the invention, since the external electrodes are formed by placing the solder balls in the openings, the manufacturing process can be simplified.

【0084】請求項30の発明においては、簡単な製造
工程で半導体装置の小型化を図ることができる。
According to the thirtieth aspect of the invention, the size of the semiconductor device can be reduced by a simple manufacturing process.

【0085】請求項31の発明においては、金属突起の
高さを調整して一部露出できるので、製造工程が簡略化
される。
In the thirty-first aspect of the invention, since the height of the metal protrusion can be adjusted and a part thereof can be exposed, the manufacturing process is simplified.

【0086】請求項32の発明においては、簡単な製造
工程で半導体装置の小型化、実装密度の向上を図ること
ができる。
According to the thirty-second aspect of the invention, the size of the semiconductor device can be reduced and the packaging density can be improved by a simple manufacturing process.

【0087】請求項33の発明においては、簡単な製造
工程で信頼性の高い半導体装置を得ることができる。
According to the invention of claim 33, a highly reliable semiconductor device can be obtained by a simple manufacturing process.

【0088】請求項34の発明においては、簡単な製造
工程で電気特性の優れた半導体装置を得ることができ
る。
According to the thirty-fourth aspect of the present invention, a semiconductor device having excellent electric characteristics can be obtained by a simple manufacturing process.

【0089】請求項35の発明においては、簡単な製造
工程で半導体装置の小型化、実装密度の向上を図ること
ができる。
According to the thirty-fifth aspect of the invention, the size of the semiconductor device can be reduced and the packaging density can be improved by a simple manufacturing process.

【0090】請求項36の発明においては、簡単な製造
工程で半導体装置の小型化、実装密度の向上を図ること
ができる。
According to the thirty-sixth aspect of the invention, the semiconductor device can be downsized and the packaging density can be improved by a simple manufacturing process.

【0091】請求項37の発明においては、実装密度の
向上を図ることができる。
In the thirty-seventh aspect of the invention, the packaging density can be improved.

【0092】請求項38の発明においては、高密度実装
が可能になる。
According to the thirty-eighth aspect of the present invention, high-density mounting is possible.

【0093】請求項39の発明においては、高密度実装
が可能になる。
According to the thirty-ninth aspect of the present invention, high-density mounting is possible.

【0094】[0094]

【実施例】以下、この発明の一実施例を図を参照して説
明する。 実施例1.図1〜図4はこの発明の第1実施例を示すも
ので、図1はこの発明に係る半導体装置の一部断面を示
す外観図、図2は図1の線a−a′の部分で切断して示
す断面図、図3はこの発明に係る半導体装置の製造段階
における半田バンプ作成前の断面図、図4はこの発明に
係る半導体装置の製造方法を説明するための一部断面を
示す外観図であり、各図において、図28〜図29と対
応する部分には同一符号を付し、その詳細説明は省略す
る。図において、1Aは本実施例による半導体装置、9
は半導体チップ2に接着された接着部材としてのテー
プ、10はテープ9の上に形成された導体層、11はワ
イヤボンディングするための接続部材としての金属細
線、12は樹脂封止時に樹脂封止金型(図示せず)で形
成されたテープ9上の導体層10へ達する封止部材とし
ての封止樹脂6の開口部、13はテープ9の一部をなす
架橋部である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Example 1. 1 to 4 show a first embodiment of the present invention, FIG. 1 is an external view showing a partial cross section of a semiconductor device according to the present invention, and FIG. 2 is a portion taken along line aa 'in FIG. FIG. 3 is a cross-sectional view taken by cutting, FIG. 3 is a cross-sectional view before forming solder bumps in a manufacturing step of a semiconductor device according to the present invention, and FIG. It is an external view, and in each drawing, portions corresponding to those in FIGS. 28 to 29 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure, 1A is a semiconductor device according to the present embodiment, and 9
Is a tape as an adhesive member adhered to the semiconductor chip 2, 10 is a conductor layer formed on the tape 9, 11 is a fine metal wire as a connecting member for wire bonding, and 12 is a resin sealing at the time of resin sealing. An opening portion of the sealing resin 6 as a sealing member, which reaches the conductor layer 10 on the tape 9 formed by a mold (not shown), and 13 is a bridging portion forming a part of the tape 9.

【0095】図1および図2に示すように、半導体装置
1Aは半導体チップ2に接着されたテープ9を有し、こ
のテープ9上に形成された導体層10と半導体チップ2
上の電極としてのボンディングパッド3を金属細線11
でワイヤボンディングし、導体層10の一表面の一部を
露出するために封止樹脂6に図3に示すように開口部1
2を設ける。この開口部12は半導体装置1Aの製造工
程の途中の工程である樹脂封止工程で用いる樹脂封止金
型の樹脂封止部分の該当部分に設けた突起をテープ9上
の導体層10に押し当てて形成する。そして、この開口
部12に外部電極としての半田バンプ5を形成する。
As shown in FIGS. 1 and 2, the semiconductor device 1A has a tape 9 adhered to the semiconductor chip 2, and the conductor layer 10 formed on the tape 9 and the semiconductor chip 2 are provided.
The bonding pad 3 serving as an upper electrode is provided with a thin metal wire 11.
Wire bonding to expose a part of one surface of the conductor layer 10 in the sealing resin 6 as shown in FIG.
2 is provided. The opening 12 pushes the protrusion provided on the corresponding portion of the resin-sealed portion of the resin-sealed mold used in the resin-sealed step, which is a step in the manufacturing process of the semiconductor device 1A, onto the conductor layer 10 on the tape 9. Form by applying. Then, the solder bumps 5 as external electrodes are formed in the openings 12.

【0096】樹脂封止金型の突起は、樹脂封止金型内で
テープ9上の導体層10を例えば5〜100μm程度好
ましくは数10μm押し込むように設計されることによ
り、導電層10上に封止樹脂6のばりが発生し、導電層
10と半田バンプ5との導電性を損なうことのないよう
に工夫されている。従って、樹脂封止金型の突起が導電
層10を押し込むことによるストレスは、テープ9の弾
性により吸収されるため、半導体チップ2ヘの損傷はな
い。
The protrusions of the resin-sealing die are designed so that the conductor layer 10 on the tape 9 is pushed into the resin-sealing die by, for example, about 5 to 100 μm, preferably several tens of μm. It is devised so that burrs of the sealing resin 6 do not occur and the conductivity between the conductive layer 10 and the solder bumps 5 is not impaired. Therefore, the stress due to the protrusion of the resin-sealing mold pushing the conductive layer 10 is absorbed by the elasticity of the tape 9, and the semiconductor chip 2 is not damaged.

【0097】また、図3の半導体装置1Aの実質的に中
間製造物に半田バンプ5を形成するときには、半田ボー
ル(図示せず)を開口部12に配置しリフローすること
により、同じ樹脂封止金型で形成する外形との位置精度
を数μmの精度で半田バンプ5が精度よく形成できる。
また、図4に示すように、テープ9の一部を半導体装置
1Aの予定外形部分より突出させて架橋部13を設け、
半導体装置1Aを樹脂封止する際に樹脂封止金型で挟
み、半導体チップ2およびテープ9の樹脂封止金型内で
の位置を固定するようにし、樹脂封止金型に設けたテー
プ9上の導体層10と接触させ、半田バンプ5とのコン
タクトを得るために設けられた樹脂封止部6の開口部1
2を形成する。これにより、樹脂封止金型に設けた突起
と、テープ9上の導体層10との接触を確実なものと
し、テープ9上の導体層10と樹脂封止金型に設けた突
起の間の樹脂のにじみ出しによる封止樹脂ばりの発生が
抑えられる。
Further, when the solder bumps 5 are formed on substantially the intermediate product of the semiconductor device 1A of FIG. 3, solder balls (not shown) are arranged in the openings 12 and reflowed, so that the same resin sealing is performed. The solder bump 5 can be accurately formed with a positional accuracy of several μm with respect to the outer shape formed by the mold.
Further, as shown in FIG. 4, a part of the tape 9 is made to protrude from the planned outer shape portion of the semiconductor device 1A to provide a bridge portion 13,
When the semiconductor device 1A is resin-sealed, it is sandwiched between resin-sealing dies to fix the positions of the semiconductor chip 2 and the tape 9 in the resin-sealing die, and the tape 9 provided on the resin-sealing die. The opening 1 of the resin encapsulation portion 6 provided in order to make contact with the upper conductor layer 10 and obtain contact with the solder bumps 5.
Form 2 This ensures contact between the protrusions provided on the resin-sealing die and the conductor layer 10 on the tape 9, so that the conductor layer 10 on the tape 9 and the protrusions provided on the resin-sealing die are secured. Occurrence of sealing resin flash due to resin bleeding is suppressed.

【0098】実施例2.図5〜図8はこの発明の第2実
施例を示すもので、図5はこの発明に係る半導体装置の
一部断面を示す外観図、図6は図5の線kーk′の部分
で切断して示す断面図、図7はこの発明に係る半導体装
置の製造段階における樹脂封止前の状態を示す断面図、
図8はこの発明に係る半導体装置の製造方法を説明する
ための一部断面図であり、各図において、図1〜図4と
対応する部分には同一符号を付し、その詳細説明は省略
する。図において、1Bは本実施例による半導体装置、
14はワイヤボンディング技術を用いて半導体チップ1
0上に形成された金属突起、15はテープ9上に形成さ
れた櫛形導体層であって、この櫛形導体層15はテープ
9上の導体層の一部をなすもので、櫛形状をしており、
テープ9上の複数の導体層の部分よりワイヤボンディン
グを行うものである。16は半田バンプ5と金属突起1
4との接合性を向上するため、封止樹脂部6に設けられ
た凹部と嵌合する半田バンプ5の凸部である。
Example 2. 5 to 8 show a second embodiment of the present invention. FIG. 5 is an external view showing a partial cross section of a semiconductor device according to the present invention, and FIG. 6 is a portion taken along line kk 'in FIG. FIG. 7 is a cross-sectional view taken by cutting, FIG. 7 is a cross-sectional view showing a state before resin sealing in a manufacturing stage of a semiconductor device according to the present invention,
FIG. 8 is a partial cross-sectional view for explaining the method of manufacturing a semiconductor device according to the present invention. In each of the drawings, parts corresponding to those in FIGS. To do. In the figure, 1B is a semiconductor device according to the present embodiment,
14 is a semiconductor chip 1 using wire bonding technology
0 is a metal protrusion, and 15 is a comb-shaped conductor layer formed on the tape 9. The comb-shaped conductor layer 15 is a part of the conductor layer on the tape 9 and has a comb shape. Cage,
Wire bonding is performed from a plurality of conductor layer portions on the tape 9. 16 is a solder bump 5 and a metal protrusion 1
4 is a convex portion of the solder bump 5 that fits into a concave portion provided in the sealing resin portion 6 in order to improve the bondability with the solder bump 4.

【0099】従来よりワイヤボンディング技術による金
属突起の形成は、半導体チップ2上のボンディングパッ
ド3にバンプを形成し、TAB(Tape・Automated・Bondi
ng)テープと接合する場合に用いられるが、本実施例で
は、テープ9上の導体層10に上述のワイヤボンデイン
グ技術により金属突起14を形成する。これにより、上
述した特開平1−179334号公報に示されているよ
うな複雑な工程の方法を取る必要がなくなり、また、後
述の基板18(図11)のようなベース基板に半導体素
子をフェイスダウンボンディング(後述の図27のよう
に能動素子等の半導体素子を下方に向けテボンディング
する方法)する際の位置決めの困難さがなくなる。
Conventionally, the formation of the metal protrusions by the wire bonding technique involves forming bumps on the bonding pads 3 on the semiconductor chip 2 and forming TAB (Tape / Automated / Bondi).
In this embodiment, the metal protrusion 14 is formed on the conductor layer 10 on the tape 9 by the wire bonding technique described above. As a result, it is not necessary to use the method of complicated steps as disclosed in the above-mentioned Japanese Patent Laid-Open No. 1-179334, and the semiconductor element is placed on the base substrate such as the substrate 18 (FIG. 11) described later. There is no difficulty in positioning when down-bonding (a method of performing semiconductor bonding such as an active element downward as shown in FIG. 27 described later).

【0100】なお、上述したワイヤボンデイング技術を
用いた金属突起の形成時の材料として半田ワイヤを用い
るとリフロー時に半田バンプ5と融着し、高い強度が得
られる。また、導電層10を有するテープ9上に櫛形導
電層15を備えているので、テープ9上の複数の部分よ
り半導体チップ2との接続が可能となる。これにより、
例えば、半導体装置1Bの1つの半田バンプ5からの信
号を半導体チップ2内の種々のボンディングパッド3へ
伝達することが可能となる。さらに、櫛形導電層15を
電源供給用配線または接地配線とし、半導体チップ2内
の複数の位置への電源供給、接地を行うようにしてもよ
い。これにより、半導体チップ2内でのアルミ配線によ
る引き回しが不要となり、配線によるインダクタンスの
増加を抑え、半導体装置の高速化が可能となる。
If a solder wire is used as a material for forming the metal protrusion using the above-mentioned wire bonding technique, it is fused with the solder bump 5 at the time of reflow, and high strength can be obtained. Further, since the comb-shaped conductive layer 15 is provided on the tape 9 having the conductive layer 10, the semiconductor chip 2 can be connected from a plurality of parts on the tape 9. This allows
For example, a signal from one solder bump 5 of the semiconductor device 1B can be transmitted to various bonding pads 3 in the semiconductor chip 2. Further, the comb-shaped conductive layer 15 may be used as a power supply wiring or a ground wiring to supply power and ground to a plurality of positions in the semiconductor chip 2. This eliminates the need for aluminum wiring within the semiconductor chip 2, suppresses an increase in inductance due to the wiring, and speeds up the semiconductor device.

【0101】図7において、点線部分は樹脂封止される
部分の予想線である。図7に示すように、ワイヤボンデ
イング技術により形成された金属突起14は、樹脂封止
される予想線より突出しており、樹脂封止金型内で金属
突起14が金型内部に押し当てられ、樹脂封止後には金
属突起14が封止樹脂面より露出するようになされてい
る。つまり、ワイヤボンデイング技術により形成される
金属突起14の高さは、金属突起14自体の切り残し量
を制御することにより調整し、樹脂封止工程の段階で金
属突起14を樹脂封止金型に押し付けるように樹脂封止
し、金属突起14の一部を露出させる。これにより、製
造が容易となる。
In FIG. 7, the dotted line portion is an expected line of the portion sealed with resin. As shown in FIG. 7, the metal protrusion 14 formed by the wire bonding technique is projected from the expected line to be resin-sealed, and the metal protrusion 14 is pressed into the mold in the resin-sealed mold, After the resin sealing, the metal protrusion 14 is exposed from the sealing resin surface. That is, the height of the metal protrusion 14 formed by the wire bonding technique is adjusted by controlling the uncut amount of the metal protrusion 14 itself, and the metal protrusion 14 is formed into a resin-sealing mold in the resin sealing step. The resin is sealed so as to be pressed, and a part of the metal protrusion 14 is exposed. This facilitates manufacturing.

【0102】図8において、半田バンプ5を形成する部
分に嵌合するように封止樹脂6に凹部を設ける。する
と、半田バンプ5の形成時にこの凹部に半田が流れ込
み、封止樹脂6と半田が機械的にかみ合い、半田バンプ
5と封止樹脂6、さらには、半田バンプ5と金属突起1
4との接合が強固になる。なお、櫛形導体層15は実施
例1の半導体装置にも適用してもよい。
In FIG. 8, a recess is provided in the sealing resin 6 so as to fit in the portion where the solder bump 5 is formed. Then, when the solder bumps 5 are formed, the solder flows into the recesses, the sealing resin 6 and the solder mechanically mesh with each other, and the solder bumps 5 and the sealing resin 6, as well as the solder bumps 5 and the metal protrusions 1
The connection with 4 becomes strong. The comb-shaped conductor layer 15 may be applied to the semiconductor device of the first embodiment.

【0103】実施例3.図9〜図12はこの発明の第3
実施例を示すもので、図9はこの発明に係る半導体装置
の一部を示す外観図、図10はこの発明に係る半導体装
置の一部断面を示す外観図、図11はこの発明に係る半
導体装置の実装時の一部を示す外観図、図12は図11
の線bーb′の部分で切断して示す断面図であり、各図
において、図1〜図4と対応する部分には同一符号を付
し、その詳細説明は省略する。図において、1Cは本実
施例による半導体装置、17は半導体装置1Cを後述の
基板に対して立てるためのスタンドロック、18は半導
体装置1Cを実装するための基板、19は基板18に設
けられた配線、20は配線19と導電層10とを接続す
るための半田である。
Example 3. 9 to 12 show a third embodiment of the present invention.
9 shows an embodiment, FIG. 9 is an external view showing a part of a semiconductor device according to the present invention, FIG. 10 is an external view showing a partial cross section of a semiconductor device according to the present invention, and FIG. 11 is a semiconductor according to the present invention. FIG. 12 is an external view showing a part of the apparatus when mounted.
5 is a cross-sectional view taken along the line bb 'in FIG. 4A. In each drawing, the portions corresponding to those in FIGS. 1 to 4 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the figure, 1C is a semiconductor device according to this embodiment, 17 is a stand lock for standing the semiconductor device 1C on a substrate described later, 18 is a substrate for mounting the semiconductor device 1C, and 19 is provided on the substrate 18. The wiring 20 is a solder for connecting the wiring 19 and the conductive layer 10.

【0104】図9において、半導体装置1Cは導電層1
0を有するテープ9を半導体チップ2の一辺に貼り付
け、テープ9およびテープ9上の導電層10を含む平面
の一部を帯状に封止樹脂6より露出させる。そして、図
10に示すように、テープ9上に形成された導体層10
と半導体チップ2上のボンディングパッド3を金属細線
11でワイヤボンディングする。また、図11におい
て、基板18に半導体装置1Cを、その内部の半導体チ
ップ2が基板18に対して垂直となるように実装すると
共に、基板18上に配線19と半導体装置1Cの露出さ
れたテープ9上の導体層10とを垂直に交差するように
半田付けして実装する。
In FIG. 9, the semiconductor device 1C has a conductive layer 1
A tape 9 having 0 is attached to one side of the semiconductor chip 2, and a part of a plane including the tape 9 and the conductive layer 10 on the tape 9 is exposed in a strip shape from the sealing resin 6. Then, as shown in FIG. 10, the conductor layer 10 formed on the tape 9 is formed.
Then, the bonding pad 3 on the semiconductor chip 2 is wire-bonded with the fine metal wire 11. Further, in FIG. 11, the semiconductor device 1C is mounted on the substrate 18 so that the semiconductor chip 2 therein is perpendicular to the substrate 18, and the wiring 19 and the exposed tape of the semiconductor device 1C are provided on the substrate 18. 9 is mounted by soldering so as to vertically intersect the conductor layer 10 on the substrate 9.

【0105】また、半導体装置1Cには、半導体チップ
2の素子面と垂直な方向に延在するスタンドブロック1
7を樹脂封止工程で形成し、半導体装置1Cの一側面お
よびスタンドブロック17の一面で上記一側面と同一面
を水平にするようになされる。これにより、半導体装置
1Cを基板18に対して図11および図12に示すよう
に垂直に実装することができる。なお、ここでは、半導
体チップ2はテープ9により保持された状態で樹脂封止
されるが、慣用の半導体装置のように、半導体チップ2
をダイパッドと呼ばれるリードフレームの一部に接着
し、保持するようにしてもよい。
Further, in the semiconductor device 1C, the stand block 1 extending in the direction perpendicular to the element surface of the semiconductor chip 2 is provided.
7 is formed in a resin encapsulation process, and one side surface of the semiconductor device 1C and one surface of the stand block 17 are flush with the one side surface. As a result, the semiconductor device 1C can be mounted vertically on the substrate 18 as shown in FIGS. Here, the semiconductor chip 2 is resin-sealed while being held by the tape 9, but like the conventional semiconductor device, the semiconductor chip 2 is sealed.
May be adhered to a part of a lead frame called a die pad and held.

【0106】実施例4.図13〜図19はこの発明の第
4実施例を示すもので、図13はこの発明に係る半導体
装置の一部を示す外観図、図14はこの発明に係る半導
体装置の一部断面を示す外観図、図15はこの発明に係
る半導体装置の実装時の一部を示す外観図、図16は図
15の線cーc′の部分で切断して示す断面図、図17
はこの発明に係る半導体装置の実装時の状態を示す平面
図、図18はこの発明に係る半導体装置を複数個実装時
の状態を示す平面図、同じく図19はこの発明に係る半
導体装置を複数個実装時の状態を示す平面図であり、各
図において、図1〜図4および図11,図12と対応す
る部分には同一符号を付し、その詳細説明は省略する。
図において、1Dは本実施例による半導体装置、21は
半導体チップ2を接着し、保持するためのリードフレー
ムの一部であるダイパッド、22は導体層10を有する
テープ9を接着して保持し、半導体チップ2より浮かせ
るリードフレームの一部である基本部材としてのベース
リードであって、このベースリード22によりスタンド
リード8が形成される。23はスタンドリード8の屈曲
部を収納する封止樹脂6の溝部である。
Example 4. 13 to 19 show a fourth embodiment of the present invention, FIG. 13 is an external view showing a part of a semiconductor device according to the present invention, and FIG. 14 is a partial sectional view of the semiconductor device according to the present invention. 15 is an external view showing a part of the semiconductor device according to the present invention when mounted, FIG. 16 is a cross-sectional view taken along the line cc 'in FIG.
Is a plan view showing a mounted state of the semiconductor device according to the present invention, FIG. 18 is a plan view showing a mounted state of a plurality of semiconductor devices according to the present invention, and FIG. 19 is a plan view showing a plurality of semiconductor devices according to the present invention. It is a top view which shows the state at the time of individual mounting. In each figure, the same code | symbol is attached | subjected to FIG. 1-FIG.4 and FIG.11, FIG.12, and the detailed description is abbreviate | omitted.
In the figure, 1D is a semiconductor device according to the present embodiment, 21 is a die pad which is a part of a lead frame for adhering and holding the semiconductor chip 2, and 22 is a tape 9 having a conductor layer 10 for adhering and holding, The base lead 22 is a base lead that is a part of a lead frame that can be floated above the semiconductor chip 2. The base lead 22 forms the stand lead 8. Reference numeral 23 is a groove portion of the sealing resin 6 that accommodates the bent portion of the stand lead 8.

【0107】本実施例では、導体層10を有するテープ
9は、半導体チップ2上の一辺上にこれと離れて配置さ
れたベースリード22上に接着される。なお、図14で
は、ベースリード22はリードフレーム枠部(図示せ
ず)から切り取り、曲げる前の状態を示している。一
方、半導体チップ2はリードフレームの一部であるダイ
パッド21上に接着され固定される。これにより、テー
プ9を直接半導体チップ2上に貼り付けた上述の実施例
1の半導体装置1Aの場合と異なり、半導体チップ2の
周囲は比較的接着力が強く、吸水率の低い封止樹脂6で
覆われているため、半導体チップ2とテープ9の界面の
接着層に比べて実装時の熱により実装までに吸湿した水
の爆発による界面剥離およびそれに伴う金属細線11の
破断が起こりにくくなり、製品の信頼性が向上する。
In this embodiment, the tape 9 having the conductor layer 10 is adhered onto the base lead 22 which is arranged on one side of the semiconductor chip 2 and is separated therefrom. Note that, in FIG. 14, the base lead 22 is shown in a state before being cut and bent from a lead frame frame (not shown). On the other hand, the semiconductor chip 2 is adhered and fixed on the die pad 21 which is a part of the lead frame. Thus, unlike the case of the semiconductor device 1A of the above-described first embodiment in which the tape 9 is directly attached to the semiconductor chip 2, the periphery of the semiconductor chip 2 has a relatively strong adhesive force and the sealing resin 6 having a low water absorption rate. Since it is covered with, the interface peeling due to the explosion of water absorbed by the heat during mounting due to the heat at the time of mounting and the accompanying breakage of the metal fine wire 11 are less likely to occur than the adhesive layer at the interface between the semiconductor chip 2 and the tape 9. Product reliability is improved.

【0108】また、本実施例では、図13からも分かる
ように、テープ9上の導体層10を封止樹脂6の部分よ
り所定の長さ例えば0.2〜1mm程度突出させ、この導
体層10を図16に示すようにヒンジ(同図において導
体層10がL字状に曲がっている部分)のように基板1
8上の配線19と位置合わせして半田20により半田付
けを行う。これにより、上述の実施例3の半導体装置1
Cの場合よりテープ9上の導体層10と基板18上の配
線19との半田付けによる接続不良(オープン不良)が
低減される。
Further, in this embodiment, as can be seen from FIG. 13, the conductor layer 10 on the tape 9 is projected from the portion of the sealing resin 6 by a predetermined length, for example, 0.2 to 1 mm, and the conductor layer 10 is formed. As shown in FIG. 16, the substrate 1 is formed like a hinge (the portion in which the conductor layer 10 is bent in an L shape in the figure).
The soldering is performed by aligning with the wiring 19 on the wiring 8. As a result, the semiconductor device 1 of the above-described third embodiment
Compared to the case of C, connection failure (open failure) due to soldering of the conductor layer 10 on the tape 9 and the wiring 19 on the substrate 18 is reduced.

【0109】また、本実施例では、ベースリード22を
接地電位とし、このベースリード22がテープ9上の導
体層10より低インピーダンスとなるように設計する。
これにより、半導体装置1Dの高速動作が可能になる。
さらに、図14に示すように、テープ9をベースリード
22の一部に接着し、ベースリード22の半導体チップ
2の内側(ボンディングパッド3が配置されている所)
に近い部分を帯状に露出させる。これにより、接地電位
にあるベースリード22の任意の部分から半導体チップ
2上の任意の接地電位を必要とするボンディングパッド
3と接続することが可能となり、半導体チップ2内のア
ルミ配線の引き回しが短くなり、それだけ信号の遅延量
も少なくなって半導体装置1Dの高速動作が可能にな
る。ちなみに、図14では、8本の金属細線11の内、
図面に向かって左より第1番目,第5番目および第7番
目の金属細線11が接地電位用として半導体チップ2上
のボンディングパッド3とそれぞれ接続されている。
Further, in this embodiment, the base lead 22 is set to the ground potential, and the base lead 22 is designed to have a lower impedance than the conductor layer 10 on the tape 9.
This enables high-speed operation of the semiconductor device 1D.
Further, as shown in FIG. 14, the tape 9 is adhered to a part of the base lead 22 and the inside of the semiconductor chip 2 of the base lead 22 (where the bonding pad 3 is arranged).
The part near to is exposed in a strip. As a result, it is possible to connect any portion of the base lead 22 at ground potential to the bonding pad 3 on the semiconductor chip 2 that requires any ground potential, and the routing of aluminum wiring in the semiconductor chip 2 is short. As a result, the amount of signal delay is reduced and the semiconductor device 1D can operate at high speed. By the way, in FIG. 14, among the eight thin metal wires 11,
The first, fifth and seventh thin metal wires 11 from the left in the drawing are respectively connected to the bonding pads 3 on the semiconductor chip 2 for ground potential.

【0110】図17は半導体装置1Dのベースリード2
2に連なる外部リードとしてのスタンドリード8の曲げ
方向を示しており、この図17のように、2本の外部リ
ードを互いに異なる方向に曲げることにより、図32に
示したSVPのように4本の外部リードを用いることな
く同様の自立性を得ることができる。ことにより、同一
の外形のパッケージの場合、SVPに比べて2本の外部
リードを余分にテープ9上の導体層10を設けることが
できる。
FIG. 17 shows the base lead 2 of the semiconductor device 1D.
The bending direction of the stand lead 8 as an external lead connected to 2 is shown. By bending the two external leads in different directions as shown in FIG. 17, the four leads as in the SVP shown in FIG. Similar independence can be obtained without the use of external leads. As a result, in the case of packages having the same outer shape, the conductor layer 10 on the tape 9 can be provided with two extra external leads as compared with the SVP.

【0111】図18は半導体装置1Dを並列に実装した
場合を示しており、半導体装置1DがメモリICの場合
に予想される実装方法のうち、スタンドリード8の屈曲
部を収納する封止樹脂6の溝部23内に隣接する半導体
装置1Dのスタンドリード8を入れずに実装した場合で
ある。また、図19は図18と同様に半導体装置1Dを
並列に実装した場合であるが、図19ではスタンドリー
ド8の屈曲部を収納する封止樹脂6の溝部23内に隣接
する半導体装置1Dのスタンドリード8を潜り込ませて
実装した場合である。このように、スタンドリード8の
屈曲部を収納する封止樹脂6の溝部23内に隣接する半
導体装置1Dのスタンドリード8を潜り込ませることに
より、半導体装置1Dの実装ピッチが小さくなり、高密
度実装が可能となる。なお、テープ9上の導体層10を
封止樹脂6の部分より所定の長さ例えば0.2〜1mm程
度突出させ、この導体層10をヒンジのように基板18
上の配線19と位置合わせして半田20により半田付け
を行うことは、他のSVPの半導体装置にも適用しても
よい。
FIG. 18 shows a case where the semiconductor devices 1D are mounted in parallel. Among the mounting methods expected when the semiconductor device 1D is a memory IC, the sealing resin 6 for accommodating the bent portion of the stand lead 8 is used. This is a case where the adjacent semiconductor device 1D is mounted without inserting the stand lead 8 in the groove 23. Further, FIG. 19 shows a case where the semiconductor devices 1D are mounted in parallel as in FIG. 18, but in FIG. 19, the semiconductor device 1D adjacent to the groove 23 of the sealing resin 6 that accommodates the bent portion of the stand lead 8 is shown. This is a case where the stand lead 8 is mounted by being embedded. In this way, by making the stand lead 8 of the semiconductor device 1D adjacent to the groove 23 of the sealing resin 6 that accommodates the bent portion of the stand lead 8 submerged, the mounting pitch of the semiconductor device 1D is reduced, and high density mounting is performed. Is possible. In addition, the conductor layer 10 on the tape 9 is projected from the sealing resin 6 portion by a predetermined length, for example, about 0.2 to 1 mm, and the conductor layer 10 is formed into a substrate 18 like a hinge.
Aligning with the upper wiring 19 and soldering with the solder 20 may be applied to other SVP semiconductor devices.

【0112】実施例5.図20〜図23はこの発明の第
5実施例を示すもので、図20はこの発明に係る半導体
装置の製造段階におけるリード加工工程前の一部断面を
示す外観図、図21はこの発明に係る半導体装置の実装
時の一部を示す外観図、図22は図21の矢印dの方向
から見た側面図、図23はこの発明に係る半導体装置の
ベースリード、テープ、リングリード等の構成要素の一
部を示す外観図であり、各図において、図1〜図4およ
び図11,図12,図15と対応する部分には同一符号
を付し、その詳細説明は省略する。図において、1Eは
本実施例による半導体装置、24はベースリード22の
外側にベースリード22を囲むように配置された環状部
材としてのリングリード、25はベースリード22の一
部をなし、ベースリード22とテープ9および封止樹脂
6の接着性を向上させるために設けられたベースリード
の櫛歯部である。
Example 5. 20 to 23 show a fifth embodiment of the present invention. FIG. 20 is an external view showing a partial cross section before a lead processing step in a semiconductor device manufacturing stage according to the present invention, and FIG. 22 is an external view showing a part of the semiconductor device at the time of mounting, FIG. 22 is a side view seen from the direction of arrow d in FIG. 21, and FIG. 23 is a configuration of a base lead, tape, ring lead, etc. of the semiconductor device according to the present invention. It is an external view which shows a part of element, In each figure, the same code | symbol is attached | subjected to FIGS. 1-4 and FIG. 11, FIG. 12, FIG. 15, and the detailed description is abbreviate | omitted. In the figure, 1E is a semiconductor device according to the present embodiment, 24 is a ring lead as an annular member arranged outside the base lead 22 so as to surround the base lead 22, 25 is a part of the base lead 22, and the base lead is shown. 22 is a comb tooth portion of the base lead provided to improve the adhesiveness of the tape 22, the tape 9 and the sealing resin 6.

【0113】図20において、半導体チップ2上の一列
に並んだボンディングパッド3を挟んでベースリード2
2と反対側を通るようにかつベースリード22の周囲に
リングリード23を設け、ベースリード22とリングリ
ード23を各々電源供給電位または接地電位とする。こ
れにより、半導体チップ2内の任意のボンディングパッ
ド3に電源供給を行い、または、接地を行うことがで
き、半導体チップ2内のアルミ配線を短くし、半導体チ
ップ2内の信号の遅延を減少させると共に、電源供給お
よび接地に関与するリードのインダクタンス量を減少さ
せるため、上述した実施例4の半導体装置1Dの場合よ
りさらに動作を高速化することができる。
In FIG. 20, the base leads 2 are sandwiched by the bonding pads 3 arranged in a line on the semiconductor chip 2.
A ring lead 23 is provided around the base lead 22 so as to pass through the side opposite to 2, and the base lead 22 and the ring lead 23 are set to a power supply potential or a ground potential, respectively. As a result, power can be supplied to or grounded to any bonding pad 3 in the semiconductor chip 2, aluminum wiring in the semiconductor chip 2 can be shortened, and signal delay in the semiconductor chip 2 can be reduced. At the same time, since the amount of inductance of the leads involved in power supply and grounding is reduced, the operation speed can be further increased as compared with the case of the semiconductor device 1D of the fourth embodiment described above.

【0114】図21において、ベースリード22、リン
グリード24の一部封止樹脂6より出た部分をスタンド
リード8として用いる。ここでは、両端の2本ずつ合計
4本のスタンドリード8は、各々片端の2本が上述した
SVPのように異なる方向に曲げられる。図22におい
て、一部スタンドリード8と、このスタンドリード8の
屈曲部を収納する封止樹脂6の溝部23を点線で表して
いる。図23において、ベースリード22の一部、テー
プ9の下部、テープ9上の導体層10の下部以外のとこ
ろを削除し、櫛歯状にした場合のベースリード22、導
体層10を有するテープ9、およびリングリード23を
示しており、テープ9をベースリード22から離した状
態である。
In FIG. 21, portions of the base lead 22 and the ring lead 24 which are partially exposed from the sealing resin 6 are used as the stand leads 8. Here, the total of four stand leads 8 each having two ends are bent in two different directions at each end, as in the SVP described above. In FIG. 22, a part of the stand lead 8 and the groove portion 23 of the sealing resin 6 that accommodates the bent portion of the stand lead 8 are shown by a dotted line. In FIG. 23, a part of the base lead 22, the lower part of the tape 9, and the part other than the lower part of the conductor layer 10 on the tape 9 are removed to form a comb-shaped tape 9 having the base lead 22 and the conductor layer 10. , And the ring lead 23 are shown, with the tape 9 separated from the base lead 22.

【0115】図23に示すように、ベースリード22の
一部、テープ9上の導体層10の下部以外の所を削除し
たことにより、半導体装置1Eの製造工程で、半導体チ
ップ2上のボンディングパッド3とテープ9上の導体層
10とを金属細線11で接合する場合に、テープ9上の
導体層10への金属細線11のワイヤボンディング性を
損なうことがない。これは、ワイヤボンディンするテー
プ9上の導体層10の下部にはベースリード22が存在
するため、ワイヤボンディング時の荷重を有効に使い得
るからで、下地が軟らかいとボンディング荷重が減少す
るためボンディング剥がれが生じる。また、封止後封止
樹脂6とベースリード22の密着性を向上するために、
封止樹脂6とベースリード22の界面を通して水分の侵
入を抑え、耐湿性の劣化を抑制できる。ベースリード2
2とテープ9および封止樹脂6の接着性を向上させるた
めに設けられたベースリードの櫛歯部25は、他の実施
例におけるベースリード22にも同様に適用してもよ
い。
As shown in FIG. 23, by removing a part of the base lead 22 and a portion other than the lower part of the conductor layer 10 on the tape 9, the bonding pad on the semiconductor chip 2 is manufactured in the manufacturing process of the semiconductor device 1E. When 3 and the conductor layer 10 on the tape 9 are joined by the metal fine wire 11, the wire bonding property of the metal fine wire 11 to the conductor layer 10 on the tape 9 is not impaired. This is because the base lead 22 is present below the conductor layer 10 on the tape 9 for wire bonding, so that the load at the time of wire bonding can be effectively used. Peeling occurs. Further, in order to improve the adhesion between the sealing resin 6 and the base lead 22 after sealing,
Water can be prevented from entering through the interface between the sealing resin 6 and the base lead 22, and the deterioration of moisture resistance can be suppressed. Base lead 2
The comb-teeth portion 25 of the base lead provided to improve the adhesiveness between the tape 2, the tape 9 and the sealing resin 6 may be similarly applied to the base lead 22 in other embodiments.

【0116】実施例6.図24および図25はこの発明
の第6実施例を示すもので、図24はこの発明に係る半
導体装置の一部断面を示す外観図、図25は図24の線
eーe′の部分で切断して示す断面図であり、各図にお
いて、図1〜図4と対応する部分には同一符号を付し、
その詳細説明は省略する。図において、1Fは本実施例
による半導体装置、26は半導体チップ2上に設けられ
た接着部材としてのTABテープ、27はTABテープ
26上の外部電極としての配線、28はTABテープ2
6の内部リード、29はTABテープ26上の櫛形配
線、30はTABテープ26の架橋部、31はボンディ
ングパッド3上に設けられたバンプである。
Example 6. 24 and 25 show a sixth embodiment of the present invention, FIG. 24 is an external view showing a partial cross section of a semiconductor device according to the present invention, and FIG. 25 is a portion taken along the line ee 'in FIG. It is sectional drawing cut and shown, In each figure, the same code | symbol is attached | subjected to the part corresponding to FIGS.
Detailed description thereof will be omitted. In the figure, 1F is a semiconductor device according to the present embodiment, 26 is a TAB tape as an adhesive member provided on the semiconductor chip 2, 27 is a wiring as an external electrode on the TAB tape 26, and 28 is a TAB tape 2.
Reference numeral 6 is an internal lead, 29 is a comb-shaped wiring on the TAB tape 26, 30 is a bridge portion of the TAB tape 26, and 31 is a bump provided on the bonding pad 3.

【0117】図24において、TAB技術を用い、TA
Bテープ26の内部リード28の先端部と半導体チップ
2のボンディングパッド3とをバンプ31と呼ばれる金
属突起電極を介して接続する。TABテープ26の樹脂
封止部分より外側の破線で示すTABテープの架橋部3
0は実施例1における架橋部13(図4)と同様、封止
金型内での半導体チップ2の位置固定、半田バンプ5を
形成するために、封止樹脂6に設けた凹部を形成するた
めの封止金型の突起をTABテープ26上に圧接させる
ことを可能にする。その後このTABテープの架橋部3
0はその役目が終わると切断される。
In FIG. 24, TA is used and TA
The tip end of the internal lead 28 of the B tape 26 and the bonding pad 3 of the semiconductor chip 2 are connected via a metal projection electrode called a bump 31. The bridge portion 3 of the TAB tape indicated by a broken line outside the resin-sealed portion of the TAB tape 26
Similarly to the bridging portion 13 (FIG. 4) in Example 1, 0 forms a concave portion provided in the sealing resin 6 for fixing the position of the semiconductor chip 2 in the sealing mold and forming the solder bump 5. It is possible to press the protrusion of the sealing die on the TAB tape 26. After that, the bridge part 3 of this TAB tape
0 is cut off when its role ends.

【0118】また、TAB技術を用いる場合は、実施例
1の半導体装置1Aの場合と異なり、TABテープ26
の内部リード28がTABテープ26の位置より上に存
在せずとも半導体チップ2との接続が可能となる。つま
り、TABテープ26上の封止樹脂6の厚さを抑え、半
導体装置1Fを小型化することができる。なお、バンプ
31はボンディングパッド3の上に設けてもよいし、あ
るいは、TABテープ26の内部リード28側に設けて
もよい。また、本実施例では、TABテープ26と半導
体チップ2とが接着した状態で示されているが、半導体
チップ2はTABテープ9より出ている内部リード28
で吊り下げることも可能であり、必ずしも接着の必要性
はない。
When the TAB technique is used, unlike the case of the semiconductor device 1A of the first embodiment, the TAB tape 26 is used.
It is possible to connect to the semiconductor chip 2 even if the internal lead 28 is not above the position of the TAB tape 26. That is, the thickness of the sealing resin 6 on the TAB tape 26 can be suppressed, and the semiconductor device 1F can be downsized. The bumps 31 may be provided on the bonding pads 3 or may be provided on the inner lead 28 side of the TAB tape 26. Further, in the present embodiment, the TAB tape 26 and the semiconductor chip 2 are shown in a state of being bonded, but the semiconductor chip 2 has the internal lead 28 protruding from the TAB tape 9.
It is also possible to hang it with, and it is not always necessary to bond it.

【0119】実施例7.図26および図27はこの発明
の第7実施例を示すもので、図26はこの発明に係る半
導体装置の一部断面を示す外観図、図27は図26の線
fーf′の部分で切断して示す断面図であり、各図にお
いて、図1〜図4および図11,図12,図15,図2
4と対応する部分には同一符号を付し、その詳細説明は
省略する。図において、1Gは本実施例による半導体装
置、32は半導体装置1Gの表面に金型を用いて形成さ
れ、基板18の配線27と嵌合する位置決め凹部、33
は基板18に形成されたスルーホール、34は基板18
のスルーホール33等との干渉を防ぐために半導体装置
1Gの表面に金型を用いて形成された逃げ凹部である。
Example 7. 26 and 27 show a seventh embodiment of the present invention. FIG. 26 is an external view showing a partial cross section of a semiconductor device according to the present invention, and FIG. 27 is a portion taken along line f-f 'in FIG. It is sectional drawing cut and shown, and in each figure, FIGS. 1-4, FIG. 11, FIG. 12, FIG. 15, FIG.
Portions corresponding to 4 are assigned the same reference numerals and detailed description thereof will be omitted. In the figure, 1G is a semiconductor device according to the present embodiment, 32 is a positioning recess formed on the surface of the semiconductor device 1G by using a mold and fitted with the wiring 27 of the substrate 18, 33
Is a through hole formed in the substrate 18, 34 is the substrate 18
This is a relief recess formed by using a mold on the surface of the semiconductor device 1G in order to prevent interference with the through holes 33 and the like.

【0120】本実施例では、半導体チップ2上に配線2
7を有するTABテープ26を設け、配線27と半導体
チップ2とを電気的に接続すると共に、TABテープ2
6上の配線27が帯状に露出するように樹脂封止し、樹
脂封止面とTABテープ26上の配線27の段差を20
0μm以下に抑え、半導体装置1GのTABテープ26
上の配線27を下にして、かつ配線27と基板18上の
配線19とを位置決めした後半田付けが可能なパッケー
ジとする。このように、封止樹脂面と配線27との段差
を200μm以下に抑えたので、例えばスクリーン印刷
による半田塗布時の半田とTABテープ26上の配線2
7が接触してリフロー後のオープン不良が発生すること
がなくなる。また、半導体装置1Gは封止樹脂より側面
に突出するリードフレームが存在しないので、実装時に
必要な面積が小さくなり、高密度実装が可能となる。
In this embodiment, the wiring 2 is formed on the semiconductor chip 2.
7 is provided, the wiring 27 and the semiconductor chip 2 are electrically connected, and the TAB tape 2 is provided.
The wiring 27 on 6 is resin-sealed so as to be exposed in a strip shape, and the step between the resin sealing surface and the wiring 27 on the TAB tape 26 is set to 20.
The TAB tape 26 of the semiconductor device 1G is suppressed to 0 μm or less.
The upper wiring 27 is set downward, and the wiring 27 and the wiring 19 on the substrate 18 are positioned and then soldered. In this way, since the step between the sealing resin surface and the wiring 27 is suppressed to 200 μm or less, the solder and the wiring 2 on the TAB tape 26 at the time of applying solder by screen printing, for example.
It is possible to prevent the contact of 7 and the occurrence of an open defect after reflow. Further, since the semiconductor device 1G does not have a lead frame protruding to the side surface from the encapsulating resin, the area required for mounting is small, and high-density mounting is possible.

【0121】また、本実施例では、基板18上の配線1
9と嵌合する位置決め凹部32を半導体装置1Gと基板
18上の配線19との位置決めを概略行うようにしてい
る。これにより、実装が容易となり、実装性が向上す
る。また、本実施例では、半導体装置1Gの表面に金型
を用いて逃げ凹部34を形成する。これにより、基板1
8上の配線19以外の例えばスルーホール33等の部分
と半導体装置1Gとの干渉を防ぎ、位置決め凹部32の
効果を充分なものとすると共に、半導体装置1Gと基板
18との接触面積を少なくして、半田リフロー時の半導
体装置1Gが微少に動き、位置決め凹部32によって概
略位置合わせされた場所から適正な実装位置へ動くいわ
ゆるセルフアライメントが可能になる。
Further, in this embodiment, the wiring 1 on the substrate 18
The positioning recess 32 that fits with the wiring 9 is roughly positioned between the semiconductor device 1G and the wiring 19 on the substrate 18. This facilitates mounting and improves mountability. Further, in this embodiment, the escape recess 34 is formed on the surface of the semiconductor device 1G using a mold. As a result, the substrate 1
8, the interference between the semiconductor device 1G and a portion other than the wiring 19 such as the through hole 33 is prevented, the effect of the positioning recess 32 is made sufficient, and the contact area between the semiconductor device 1G and the substrate 18 is reduced. As a result, so-called self-alignment is possible in which the semiconductor device 1G moves slightly during solder reflow and moves from a position roughly aligned by the positioning recess 32 to an appropriate mounting position.

【0122】また、図26に示すように、半導体装置1
Gの表面、半導体チップ2の表面と同じ側に半導体装置
1Gの表面より最大200μmへこんだ部分にある電極
面と基板18上の配線19とを半田ペーストを介して接
着した後リフローする。図中、符号mは半導体装置1G
の表面と電極面すなわち配線27との段差を表し、最大
200μmであり、符号nは半田ペーストの厚さで、通
常最大200μmである。なお、ここでは、TABテー
プ26上の配線27と半導体チップ2との電気的な接続
にTAB法を用いているため、図中、mの樹脂厚さは内
部リード28が封止樹脂6の通して見え、不良となる限
界概ね50μmまで薄くすることができる。
Further, as shown in FIG. 26, the semiconductor device 1
The surface of G and the surface of the semiconductor chip 2 are bonded to the wiring surface 19 on the substrate 18 and the electrode surface, which is recessed by a maximum of 200 μm from the surface of the semiconductor device 1G, through solder paste and then reflowed. In the figure, the symbol m indicates the semiconductor device 1G.
Represents a step between the surface of the electrode and the electrode surface, that is, the wiring 27, and has a maximum of 200 μm, and the symbol n is the thickness of the solder paste, which is usually a maximum of 200 μm. Here, since the TAB method is used for electrical connection between the wiring 27 on the TAB tape 26 and the semiconductor chip 2, the resin thickness m in the figure indicates that the inner lead 28 is through the sealing resin 6. It is possible to reduce the thickness to about 50 .mu.m, which is the limit at which it looks and becomes defective.

【0123】[0123]

【発明の効果】以上のように請求項1の発明によれば、
半導体チップ上に設けられ、導体層を有する接着部材
と、半導体チップ上に設けられた電極と導体層とを電気
的に接続する接続部材と、半導体チップ、導体層、接着
部材および接続部材を樹脂封止する封止部材と、この封
止部材に設けられた開口部を介して導体層に接続された
外部電極とを備えたので、耐湿性がよくなって信頼性を
向上でき、また、電気特性、実装密度および汎用性の向
上を図ることができると共に、小型化が可能となるとい
う効果がある。
As described above, according to the invention of claim 1,
An adhesive member provided on the semiconductor chip and having a conductor layer, a connecting member for electrically connecting the electrode and the conductor layer provided on the semiconductor chip, a semiconductor chip, a conductor layer, an adhesive member, and a resin connecting member. Since the sealing member for sealing and the external electrode connected to the conductor layer through the opening provided in the sealing member are provided, moisture resistance is improved and reliability can be improved. The characteristics, the mounting density, and the versatility can be improved, and the size can be reduced.

【0124】請求項2の発明によれば、半導体チップ上
に設けられ、導体層を有する接着部材と、半導体チップ
上に設けられた電極と導体層とを電気的に接続する接続
部材と、導体層上に設けられた金属突起と、半導体チッ
プ、導体層、接着部材、接続部材および金属突起を樹脂
封止しかつ金属突起を一部外部に露出させる封止部材
と、外部に露出した金属突起と接続された外部電極とを
備えたので、耐湿性がよくなって信頼性を向上でき、ま
た、電気特性、実装密度および汎用性の向上を図ること
ができつと共に、小型化が可能となるという効果があ
る。
According to the invention of claim 2, an adhesive member provided on the semiconductor chip and having a conductor layer, a connecting member for electrically connecting the electrode and the conductor layer provided on the semiconductor chip, and a conductor. A metal protrusion provided on the layer, a semiconductor chip, a conductor layer, an adhesive member, a connecting member, and a sealing member that seals the metal protrusion with resin and exposes the metal protrusion to the outside, and a metal protrusion exposed to the outside. Since it has an external electrode connected with, the moisture resistance is improved and the reliability can be improved. In addition, the electrical characteristics, the mounting density and the versatility can be improved, and the size can be reduced. There is an effect.

【0125】請求項3の発明によれば、請求項1または
2の発明において、接着部材は、半導体チップ上に設け
られた電極と接続される櫛形導体層を有するので、請求
項1または2の発明の効果に加えて、外部電極よりの信
号を半導体チップ上の種々の電極へ伝達することが可能
となるという効果がある。
According to the invention of claim 3, in the invention of claim 1 or 2, the adhesive member has a comb-shaped conductor layer connected to the electrode provided on the semiconductor chip. In addition to the effect of the invention, there is an effect that a signal from an external electrode can be transmitted to various electrodes on a semiconductor chip.

【0126】請求項4の発明によれば、請求項2の発明
において、金属突起が露出している封止部材の部分の周
囲に凹部を設け、該凹部に上記外部電極の一部を食い込
ませたので、請求項2の発明の効果に加えて、外部電極
形成時に半田が凹部に流れ込み、封止樹脂と半田が機械
的にかみあい、半田と封止樹脂さらには外部電極と金属
突起との結合を強固にできるという効果がある。
According to the invention of claim 4, in the invention of claim 2, a recess is provided around the portion of the sealing member where the metal projection is exposed, and a part of the external electrode is made to bite into the recess. Therefore, in addition to the effect of the invention of claim 2, when the external electrode is formed, the solder flows into the concave portion, the sealing resin and the solder are mechanically meshed, and the solder and the sealing resin, and further the external electrode and the metal protrusion are coupled to each other. There is an effect that can be solid.

【0127】請求項5の発明によれば、請求項3の発明
において、櫛形導体層は、電源供給または接地電位用配
線として使用されるので、請求項3の発明の効果に加え
て、半導体チップ内での配線の引き回しが不要になり、
配線によりインダクタンスの増加が抑制されて半導体装
置の動作の高速化が可能となるという効果がある。
According to the invention of claim 5, in the invention of claim 3, the comb-shaped conductor layer is used as a wiring for power supply or a ground potential. Therefore, in addition to the effect of the invention of claim 3, a semiconductor chip is provided. There is no need for wiring inside,
The wiring has an effect that an increase in inductance is suppressed and the operation speed of the semiconductor device can be increased.

【0128】請求項6の発明によれば、半導体チップの
一側に設けられ、導体層を有する接着部材と、半導体チ
ップの他側に設けられた電極と導体層とを電気的に接続
する接続部材と、半導体チップ、導体層、接着部材およ
び接続部材を樹脂封止しかつ導体層の一側を外部に露出
させる封止部材とを備えたので、垂直実装による実装密
度の向上と信頼性および汎用性の向上を図ることができ
るという効果がある。
According to the invention of claim 6, an adhesive member provided on one side of the semiconductor chip and having a conductor layer is electrically connected to an electrode provided on the other side of the semiconductor chip and the conductor layer. Since the semiconductor device includes the member and the sealing member that seals the semiconductor chip, the conductor layer, the adhesive member, and the connecting member with resin and exposes one side of the conductor layer to the outside, improvement in mounting density and reliability due to vertical mounting and There is an effect that versatility can be improved.

【0129】請求項7の発明によれば、請求項6の発明
において、封止部材上に半導体チップの能動面と垂直な
方向に突出して設けられた支持部材を備えたので、請求
項6の発明の効果に加えて、実装が容易となり、実装
性、自立性の向上を図ることができるという効果があ
る。
According to the invention of claim 7, in the invention of claim 6, the supporting member is provided on the sealing member so as to project in a direction perpendicular to the active surface of the semiconductor chip. In addition to the effects of the invention, there is an effect that mounting is facilitated, and mountability and independence can be improved.

【0130】請求項8の発明によれば、半導体チップと
離隔して設けられた導電性の基本部材と、この基本部材
上に設けられ、導体層を有する接着部材と、半導体チッ
プに設けられた第1および第2の電極と導体層および基
本部材とをそれぞれ電気的に接続する接続部材と、半導
体チップ、基本部材、導体層、接着部材および接続部材
を樹脂封止しかつ少なくとも基本部材と導体層の一側を
外部に露出させる封止部材とを備えたので、実装時の熱
により実装までに吸湿した水の爆発による界面剥離やそ
れに伴う接続部材の破断が起こりにくくなり、製品の信
頼性を向上でき、また、実装密度、電気特性および汎用
性の向上を図ることができるという効果がある。
According to the eighth aspect of the present invention, a conductive basic member provided separately from the semiconductor chip, an adhesive member provided on the basic member and having a conductor layer, and the semiconductor chip are provided. A connecting member electrically connecting the first and second electrodes to the conductor layer and the basic member, respectively, and a semiconductor chip, the basic member, the conductor layer, the adhesive member and the connecting member are resin-sealed, and at least the basic member and the conductor. Since a sealing member that exposes one side of the layer to the outside is provided, interface peeling due to the explosion of water that has absorbed moisture by the heat of mounting and the accompanying breakage of the connecting member are less likely to occur, and product reliability is improved. There is an effect that it is possible to improve the mounting density, electrical characteristics and versatility.

【0131】請求項9の発明によれば、半導体チップと
離隔して設けられた導電性の基本部材と、半導体チップ
と離隔しかつ基本部材の周囲に設けられた導電性の環状
部材と、基本部材上に設けられ、導体層を有する接着部
材と、半導体チップに設けられた第1、第2および第3
の電極と導体層、基本部材および環状部材とをそれぞれ
電気的に接続する接続部材と、半導体チップ、基本部
材、環状部材、導体層、接着部材および接続部材を樹脂
封止しかつ少なくとも基本部材、環状部材および導体層
の一側を外部に露出させる封止部材とを備えたので、半
導体チップ内での配線の引き回しが不要になり、配線に
よりインダクタンスの増加が抑制されて半導体装置の動
作の高速化が可能となり、電気特性を向上でき、また、
実装密度、信頼性および汎用性の向上を図ることができ
るという効果がある。
According to the ninth aspect of the present invention, there is provided a conductive basic member which is provided separately from the semiconductor chip, and a conductive annular member which is provided apart from the semiconductor chip and provided around the basic member. An adhesive member provided on the member and having a conductor layer, and first, second and third adhesive members provided on the semiconductor chip.
A connecting member for electrically connecting the electrode and the conductor layer, the basic member and the annular member, respectively, and a semiconductor chip, a basic member, an annular member, a conductor layer, an adhesive member and at least the basic member resin-sealed, Since the annular member and the sealing member that exposes one side of the conductor layer to the outside are provided, it is not necessary to route the wiring within the semiconductor chip, and the wiring suppresses an increase in the inductance, thereby increasing the operation speed of the semiconductor device. Can be made possible, electrical characteristics can be improved, and
There is an effect that the packaging density, reliability and versatility can be improved.

【0132】請求項10の発明によれば、請求項8また
は9の発明において、封止部材より露出した基本部材は
支持用として使用されるので、請求項8または9の発明
の効果に加えて、半導体装置の自立性を向上することが
できるという効果がある。
According to the invention of claim 10, in the invention of claim 8 or 9, since the basic member exposed from the sealing member is used for supporting, in addition to the effect of the invention of claim 8 or 9, The advantage is that the independence of the semiconductor device can be improved.

【0133】請求項11の発明によれば、請求項8〜1
0の発明において、導体層は上記封止部材より0.2〜1.0
mm程度露出されるので、請求項8〜10の発明の効果に
加えて、導体層と基板の配線を容易に接続することがで
き、半田付けによるオープン不良が防止されるという効
果がある。
According to the invention of claim 11, claims 8 to 1
In the invention of No. 0, the conductor layer is 0.2 to 1.0 from the sealing member.
Since it is exposed by about mm, in addition to the effects of the inventions of claims 8 to 10, there is an effect that the conductor layer and the wiring of the substrate can be easily connected and an open defect due to soldering is prevented.

【0134】請求項12の発明によれば、請求項8〜1
1の発明において、封止部材より露出した導体層は実装
時基板上の配線と接続する際のヒンジとして使用される
ので、導体層をヒンジとして使用できるので、請求項8
〜11の発明の効果に加えて、実装性、信頼性の向上を
図ることができるという効果がある。
According to the invention of claim 12, claims 8 to 1
In the invention of claim 1, since the conductor layer exposed from the sealing member is used as a hinge when connecting to the wiring on the board during mounting, the conductor layer can be used as a hinge.
In addition to the effects of the inventions of 11 to 11, there is an effect that mountability and reliability can be improved.

【0135】請求項13の発明によれば、請求項8〜1
2の発明において、基本部材は接地電位用として使用さ
れるので、請求項8〜12の発明の効果に加えて、半導
体チップ内での配線の引き回しが不要になり、配線によ
りインダクタンスの増加が抑制されて半導体装置の動作
の高速化が可能となるという効果がある。
According to the invention of claim 13, claims 8 to 1
In the second aspect of the invention, since the basic member is used for ground potential, in addition to the effects of the invention of the eighth to the twelfth aspect, it is not necessary to route the wiring within the semiconductor chip, and the wiring suppresses an increase in inductance. Therefore, there is an effect that the operation speed of the semiconductor device can be increased.

【0136】請求項14の発明によれば、請求項8〜1
3の発明において、基本部材は上記電極側の表面を露出
され、該露出部がワイヤボンディング可能とされている
ので、請求項8〜13の発明の効果に加えて、半導体チ
ップ内での配線の引き回しが不要になり、配線によりイ
ンダクタンスの増加が抑制されて半導体装置の動作の高
速化が可能となり、また、電気特性の向上、製法の簡易
化を図ることができるという効果がある。
According to the invention of claim 14, claims 8 to 1
In the invention of claim 3, since the surface of the basic member on the electrode side is exposed and the exposed portion can be wire-bonded, in addition to the effects of the invention of claims 8 to 13, There is an effect that routing is unnecessary, an increase in inductance is suppressed by the wiring, the operation speed of the semiconductor device can be increased, and the electrical characteristics can be improved and the manufacturing method can be simplified.

【0137】請求項15の発明によれば、請求項8〜1
4の発明において、封止部材の上記基本部材が露出して
いる部分に溝部を設けたので、請求項8〜14の発明の
効果に加えて、半導体装置の実装ピッチが小さくなり、
高密度実装が可能となり、また、実装性を向上できると
いう効果がある。
According to the invention of claim 15, claims 8 to 1
In the invention of claim 4, since the groove is provided in the portion of the sealing member where the basic member is exposed, in addition to the effects of the invention of claims 8 to 14, the mounting pitch of the semiconductor device is reduced,
This has the effect of enabling high-density mounting and improving mountability.

【0138】請求項16の発明によれば、請求項8〜1
5の発明において、基本部材と環状部材は電極を挟んで
相互に対向した位置に配置されるので、請求項8〜15
の発明の効果に加えて、半導体チップ内での配線が短く
なって、半導体チップ内での信号の遅延が減少し、ま
た、配線によりインダクタンス量が減少して半導体装置
の動作の高速化が可能となり、電気特性の向上を図るこ
とができるという効果がある。
According to the invention of claim 16, claims 8 to 1
In the invention of claim 5, the basic member and the annular member are arranged at positions facing each other with the electrode interposed therebetween.
In addition to the effects of the invention described above, the wiring within the semiconductor chip is shortened, the signal delay within the semiconductor chip is reduced, and the inductance amount is reduced by the wiring, which enables faster operation of the semiconductor device. Therefore, there is an effect that the electrical characteristics can be improved.

【0139】請求項17の発明によれば、請求項8〜1
6の発明において、基本部材と環状部材は、電源供給ま
たは接地電位用配線として使用されるので、請求項8〜
16の発明の効果に加えて、半導体チップ内での配線が
短くなって、半導体チップ内での信号の遅延が減少し、
また、配線によりインダクタンス量が減少して半導体装
置の動作の高速化が可能となり、電気特性の向上を図る
ことができるという効果がある。
According to the invention of claim 17, claims 8 to 1
In the invention of claim 6, the basic member and the annular member are used as a power supply or a ground potential wiring.
In addition to the effects of the sixteenth invention, the wiring within the semiconductor chip is shortened, and the signal delay within the semiconductor chip is reduced.
Further, there is an effect that the amount of inductance is reduced by the wiring, the operation speed of the semiconductor device can be increased, and the electrical characteristics can be improved.

【0140】請求項18の発明によれば、請求項8〜1
7の発明において、基本部材の一側は、接着部材および
導体層に対向する部分以外は削除されて櫛形をなすの
で、請求項8〜17の発明の効果に加えて、封止樹脂と
基本部材の密着性が向上し、水分の侵入を抑制し、耐湿
性の劣化を防ぐことができるという効果がある。
According to the invention of claim 18, claims 8 to 1
In the invention of claim 7, one side of the basic member is deleted except for a portion facing the adhesive member and the conductor layer to form a comb shape. Therefore, in addition to the effects of the invention of claims 8 to 17, the sealing resin and the basic member are provided. The adhesiveness is improved, the invasion of moisture can be suppressed, and the deterioration of moisture resistance can be prevented.

【0141】請求項19の発明によれば、半導体チップ
上に設けられた接着部材と、この接着部材より延在して
半導体チップ上に設けられた電極と電気的に接続される
配線部材と、半導体チップ、接着部材および配線部材を
樹脂封止する封止部材と、この封止部材に設けられた開
口部を介して配線部材に接続された外部電極とを備えた
ので、半導体装置の小型化、実装密度、汎用性、信頼性
および電気特性の向上を図ることができるという効果が
ある。
According to the nineteenth aspect of the invention, an adhesive member provided on the semiconductor chip, and a wiring member extending from the adhesive member and electrically connected to an electrode provided on the semiconductor chip, Since the semiconductor chip, the adhesive member, and the sealing member that seals the wiring member with the resin are provided, and the external electrodes connected to the wiring member through the openings provided in the sealing member are provided, the semiconductor device can be downsized. Further, there is an effect that the mounting density, versatility, reliability and electric characteristics can be improved.

【0142】請求項20の発明によれば、半導体チップ
上に設けられた接着部材と、この接着部材より延在して
半導体チップ上に設けられた電極と電気的に接続される
配線部材と、半導体チップ、接着部材および配線部材を
樹脂封止しかつ配線部材の一側を所定の段差を持って外
部に露出させる封止部材とを備えたので、半導体装置の
小型化、実装密度、汎用性、信頼性および電気特性の向
上を図ることができるという効果がある。
According to the twentieth aspect of the present invention, an adhesive member provided on the semiconductor chip, and a wiring member extending from the adhesive member and electrically connected to an electrode provided on the semiconductor chip, Since the semiconductor chip, the adhesive member, and the sealing member that seals the wiring member with the resin and exposes one side of the wiring member to the outside with a predetermined step, downsizing of the semiconductor device, mounting density, versatility In addition, there is an effect that reliability and electrical characteristics can be improved.

【0143】請求項21の発明によれば、請求項19ま
たは20の発明において、接着部材がTABテープであ
るので、請求項19または20の発明の効果に加えて、
半導体装置の小型化に寄与できるという効果がある。
According to the invention of claim 21, in the invention of claim 19 or 20, since the adhesive member is a TAB tape, in addition to the effect of the invention of claim 19 or 20,
There is an effect that it can contribute to miniaturization of a semiconductor device.

【0144】請求項22の発明によれば、請求項19ま
たは20の発明において、接着部材がTABテープであ
り、該TABテープ上の配線部材を外部電極として用い
るので、請求項19または20の発明の効果に加えて、
封止樹脂の厚さを薄くすることができるという効果があ
る。
According to the invention of claim 22, in the invention of claim 19 or 20, the adhesive member is a TAB tape, and the wiring member on the TAB tape is used as an external electrode. Therefore, the invention of claim 19 or 20 In addition to the effect of
There is an effect that the thickness of the sealing resin can be reduced.

【0145】請求項23の発明によれば、請求項20〜
22の発明において、封止部材は実装時基板と対接する
部分に該基板の配線と嵌合する位置決め凹部を有するの
で、請求項20〜22の発明の効果に加えて、配線処理
が容易となり実装性が向上するという効果がある。
According to the invention of Claim 23, Claims 20 to
In the invention of claim 22, since the sealing member has a positioning recess for fitting with the wiring of the board at a portion facing the board at the time of mounting, in addition to the effects of the invention of claims 20 to 22, wiring processing is facilitated and mounting is performed. There is an effect that the property is improved.

【0146】請求項24の発明に係る半導体装置は、請
求項20〜23の発明において、封止部材は実装時基板
と対接する部分に基板上のスルーホール等との干渉を防
ぐための逃げ凹部を有するので、請求項20〜23の発
明の効果に加えて、位置決め凹部で概略位置合わせされ
た場所から適正な実装位置へ動く、セルフアライメント
が可能になるという効果がある。
A semiconductor device according to a twenty-fourth aspect of the present invention is the semiconductor device according to any one of the twenty-third to twenty-third aspects, wherein the sealing member is a relief recess for preventing interference with a through hole or the like on the substrate at a portion facing the substrate during mounting. Therefore, in addition to the effects of the inventions of claims 20 to 23, there is an effect that self-alignment that moves from a position roughly aligned by the positioning recess to an appropriate mounting position becomes possible.

【0147】請求項25の発明によれば、半導体チップ
上に導体層を有する接着部材を貼着す工程と、半導体チ
ップ上に電極を形成する工程と、電極と上記導体層とを
電気的に接続する工程と、半導体チップ、導体層、接着
部材を樹脂封止する工程と、この封止樹脂に上記導体層
に達する開口部を形成する工程と、開口部に半田を充填
して外部電極を形成する工程とを含むので、簡単な製造
工程で半導体装置の小型化、実装密度の向上を図ること
ができるという効果がある。
According to the twenty-fifth aspect of the invention, the step of attaching the adhesive member having the conductor layer on the semiconductor chip, the step of forming the electrode on the semiconductor chip, and the step of electrically connecting the electrode and the conductor layer to each other are performed. The step of connecting, the step of resin-sealing the semiconductor chip, the conductor layer, and the adhesive member, the step of forming an opening reaching the conductor layer in this sealing resin, and the opening is filled with solder to form an external electrode. Since the step of forming is included, there is an effect that the semiconductor device can be downsized and the packaging density can be improved by a simple manufacturing process.

【0148】請求項26の発明によれば、請求項25の
発明において、開口部を樹脂封止する際の金型に設けら
れた突起により形成するので、請求項24の発明の効果
に加えて、製造が容易となり、生産効率を向上できると
いう効果がある。
According to the invention of claim 26, in addition to the effect of the invention of claim 24, in the invention of claim 25, since the opening is formed by the protrusion provided on the mold at the time of resin sealing. Therefore, there is an effect that the manufacturing becomes easy and the production efficiency can be improved.

【0149】請求項27の発明によれば、請求項25ま
たは26の発明において、開口部を樹脂封止する際の金
型に設けられた突起を導体層に所定の深さだけ押し込む
ように半導体チップと接着部材を金型内に設置し、樹脂
封止するので、請求項25または26の発明の効果に加
えて、導体層上の封止樹脂ばりが発生して導体層と外部
電極との導電性を損なうことが防止されるという効果が
ある。
According to the twenty-seventh aspect of the invention, in the twenty-fifth or twenty-sixth aspect of the invention, the semiconductor provided so that the protrusion provided on the mold for resin-sealing the opening is pushed into the conductor layer by a predetermined depth. Since the chip and the adhesive member are placed in a mold and resin-sealed, in addition to the effect of the invention of claim 25 or 26, a sealing resin burr on the conductor layer is generated and the conductor layer and the external electrode are There is an effect that loss of conductivity is prevented.

【0150】請求項28の発明によれば、請求項25〜
27の発明において、半導体チップと接着部材を金型内
に設置する位置を保持するのに、接着部材の架橋部を金
型で挟むようにしたので、製造が容易となり、生産効率
を向上できるという効果がある。
According to the invention of Claim 28, Claims 25 to
In the invention of No. 27, since the bridge portion of the adhesive member is sandwiched between the molds in order to hold the position where the semiconductor chip and the adhesive member are installed in the mold, the manufacturing is facilitated and the production efficiency can be improved. effective.

【0151】請求項29の発明によれば、請求項25〜
28の発明において、開口部に半田ボールを乗せ、リフ
ローにより外部電極を形成するので、請求項25〜28
の発明の効果に加えて、製造工程の簡略化を図ることが
できるという効果がある。
According to the invention of claim 29, claims 25
In the twenty-eighth aspect of the invention, the solder balls are placed in the openings, and the external electrodes are formed by reflowing.
In addition to the effect of the invention described above, there is an effect that the manufacturing process can be simplified.

【0152】請求項30の発明によれば、半導体チップ
上に導体層を有する接着部材を貼着する工程と、半導体
チップ上に電極を形成する工程と、電極と導体層とを電
気的に接続する工程と、導体層上にワイヤボンディング
法により金属突起を形成する工程と、半導体チップ、導
体層、接着部材および金属突起を樹脂封止しかつ金属突
起を一部外部に露出させる工程と、外部に露出した金属
突起と接続される外部電極を形成する工程とを含むの
で、簡単な製造工程で半導体装置の小型化を図ることが
できるという効果がある。
According to the thirtieth aspect of the present invention, the step of attaching an adhesive member having a conductor layer on the semiconductor chip, the step of forming an electrode on the semiconductor chip, and the electrode and the conductor layer are electrically connected. A step of forming a metal protrusion on the conductor layer by a wire bonding method, a step of resin-sealing the semiconductor chip, the conductor layer, the adhesive member and the metal protrusion and exposing a part of the metal protrusion to the outside, Since the method further includes the step of forming the external electrode connected to the metal protrusion exposed to the outside, there is an effect that the semiconductor device can be downsized by a simple manufacturing process.

【0153】請求項31の発明によれば、請求項30の
発明において、金属突起を一部外部に露出させる工程に
おいて、金属突起の高さを、該金属突起の切り残し量を
調整し、該調整された金属突起を樹脂封止の際に樹脂封
止金型に押し付けるように樹脂封止して金属突起の一部
を露出させるので、請求項30の発明の効果に加えて、
さらに、製造工程が簡略化されるという効果がある。
According to the invention of claim 31, in the invention of claim 30, in the step of exposing a part of the metal projection to the outside, the height of the metal projection is adjusted, and the uncut amount of the metal projection is adjusted. In addition to the effect of the invention of claim 30, in addition to the effect of the invention of claim 30, since the adjusted metal protrusion is resin-sealed so as to be exposed to the resin-sealing die during resin sealing to expose a part of the metal protrusion.
Further, there is an effect that the manufacturing process is simplified.

【0154】請求項32の発明によれば、半導体チップ
の一側に導体層を有する接着部材を貼着する工程と、半
導体チップの他側に電極を形成する工程と、電極と導体
層とを電気的に接続する工程と、半導体チップ、導体層
および接着部材を樹脂封止しかつ導体層の一側を外部に
露出させる工程とを含むので、簡単な製造工程で半導体
装置の小型化、実装密度の向上を図ることができるとい
う効果がある。
According to the thirty-second aspect of the invention, the step of attaching the adhesive member having the conductor layer on one side of the semiconductor chip, the step of forming the electrode on the other side of the semiconductor chip, and the electrode and the conductor layer are performed. Since it includes a step of electrically connecting and a step of resin-sealing the semiconductor chip, the conductor layer and the adhesive member and exposing one side of the conductor layer to the outside, miniaturization and mounting of the semiconductor device by a simple manufacturing process. There is an effect that the density can be improved.

【0155】請求項33の発明によれば、半導体チップ
と離隔して導電性の基本部材を配置する工程と、基本部
材上に導体層を有する接着部材を貼着する工程と、半導
体チップに第1および第2の電極を形成する工程と、第
1および第2の電極とと導体層および基本部材とをそれ
ぞれ電気的に接続する工程と、半導体チップ、基本部
材、導体層および接着部材を樹脂封止しかつ少なくとも
上記基本部材と上記導体層の一側を外部に露出させる工
程とを含むので、簡単な製造工程で信頼性の高い半導体
装置を得ることができるという効果がある。
According to the thirty-third aspect of the invention, the step of disposing the conductive basic member at a distance from the semiconductor chip, the step of adhering an adhesive member having a conductor layer on the basic member, A step of forming the first and second electrodes, a step of electrically connecting the first and second electrodes to the conductor layer and the basic member, respectively, and a step of resin-forming the semiconductor chip, the basic member, the conductor layer and the adhesive member. Since it includes the step of sealing and exposing at least the basic member and one side of the conductor layer to the outside, there is an effect that a highly reliable semiconductor device can be obtained by a simple manufacturing process.

【0156】請求項34の発明によれば、半導体チップ
と離隔して導電性の基本部材を配置する工程と、半導体
チップと離隔しかつ基本部材の周囲に導電性の環状部材
を配置する工程と、基本部材上に導体層を有する接着部
材を貼着する工程と、半導体チップに第1、第2および
第3の電極を形成する工程と、第1、第2および第3の
電極と導体層、基本部材および環状部材とをそれぞれ電
気的に接続する工程と、半導体チップ、基本部材、環状
部材、導体層および接着部材を樹脂封止しかつ少なくと
も上記基本部材、環状部材および上記導体層の一側を外
部に露出させる工程とを含むので、簡単な製造工程で電
気特性の優れた半導体装置を得ることができるという効
果がある。
According to the thirty-fourth aspect of the present invention, the step of disposing the conductive basic member at a distance from the semiconductor chip, and the step of disposing the conductive annular member at a distance from the semiconductor chip and around the basic member. A step of adhering an adhesive member having a conductor layer on the basic member, a step of forming first, second and third electrodes on a semiconductor chip, a first, second and third electrode and a conductor layer A step of electrically connecting the basic member and the annular member to each other, and at least one of the basic member, the annular member and the conductive layer, which is obtained by resin-sealing the semiconductor chip, the basic member, the annular member, the conductor layer and the adhesive member. Since the step of exposing the side to the outside is included, there is an effect that a semiconductor device having excellent electric characteristics can be obtained by a simple manufacturing process.

【0157】請求項35の発明によれば、半導体チップ
上に接着部材を貼着する工程と、半導体チップ上に電極
を形成する工程と、電極と接着部材より延在する配線部
材を電気的に接続する工程と、半導体チップ、接着部材
および配線部材を樹脂封止する工程と、この封止樹脂に
導体層に達する開口部を形成する工程と、開口部に半田
を充填して外部電極を形成する工程とを含むので、簡単
な製造工程で半導体装置の小型化、実装密度の向上を図
ることができるという効果がある。
According to the thirty-fifth aspect of the present invention, the step of attaching the adhesive member to the semiconductor chip, the step of forming the electrode on the semiconductor chip, and the wiring member extending from the electrode and the adhesive member are electrically connected. Step of connecting, step of resin-sealing semiconductor chip, adhesive member and wiring member, step of forming an opening reaching the conductor layer in this sealing resin, and filling the opening with solder to form an external electrode Since it includes the step of forming the semiconductor device, the semiconductor device can be downsized and the packaging density can be improved by a simple manufacturing process.

【0158】請求項36の発明によれば、半導体チップ
上に接着部材を貼着する工程と、半導体チップ上に電極
を形成する工程と、電極と接着部材より延在する配線部
材を電気的に接続する工程と、この接着部材より延在し
て半導体チップ上に設けられた電極と電気的に接続され
る配線部材と、半導体チップ、接着部材および配線部材
を樹脂封止しかつ配線部材の一側を所定の段差を持って
外部に露出させる工程とを含むので、簡単な製造工程で
半導体装置の小型化、実装密度の向上を図ることができ
るという効果がある。
According to the thirty-sixth aspect of the present invention, the step of attaching the adhesive member on the semiconductor chip, the step of forming the electrode on the semiconductor chip, and the wiring member extending from the electrode and the adhesive member are electrically connected. The step of connecting, the wiring member extending from the adhesive member and electrically connected to the electrode provided on the semiconductor chip, the semiconductor chip, the adhesive member and the wiring member are resin-sealed and one of the wiring members is formed. Since the step of exposing the side to the outside with a predetermined step is included, there is an effect that the semiconductor device can be downsized and the packaging density can be improved by a simple manufacturing process.

【0159】請求項37の発明によれば、半導体装置を
基板に対して垂直に配置し、半導体装置内の半導体チッ
プの一側に貼着された接着部材上の導体層を基板の配線
と電気的に接続するようにしたので、実装密度の向上を
図ることができるという効果がある。
According to the thirty-seventh aspect of the present invention, the semiconductor device is arranged vertically to the substrate, and the conductor layer on the adhesive member attached to one side of the semiconductor chip in the semiconductor device is electrically connected to the wiring of the substrate. Since they are electrically connected, there is an effect that the packaging density can be improved.

【0160】請求項38の発明によれば、半導体装置の
樹脂封止部分に設けられた溝部の内、基本部材を曲げる
ために用いられていない溝部に隣接する他の半導体装置
の支持部材を潜り込ませて実装するようにしたので、高
密度実装が可能になるという効果がある。
According to the thirty-eighth aspect of the present invention, among the groove portions provided in the resin-sealed portion of the semiconductor device, the supporting member of another semiconductor device adjacent to the groove portion not used for bending the basic member is embedded. Since it is mounted in such a manner, there is an effect that high-density mounting becomes possible.

【0161】請求項39の発明によれば、半導体装置の
半導体チップ表面側の樹脂表面に配線部材の貼着された
接着部材を露出させるように樹脂封止し、接着部材上の
配線部材と半導体装置の樹脂表面との段差を所定値に抑
え、接着部材上の配線部材を基板に対向するように実装
し、接着部材上の配線部材を基板の配線と電気的に接続
するようにしたので、高密度実装が可能になるという効
果がある。
According to the thirty-ninth aspect of the present invention, resin sealing is performed so as to expose the adhesive member to which the wiring member is adhered on the resin surface on the semiconductor chip surface side of the semiconductor device, and the wiring member and the semiconductor on the adhesive member. Since the step difference with the resin surface of the device is suppressed to a predetermined value, the wiring member on the adhesive member is mounted so as to face the substrate, and the wiring member on the adhesive member is electrically connected to the wiring of the substrate. This has the effect of enabling high-density mounting.

【図面の簡単な説明】[Brief description of drawings]

【図1】 この発明に係る半導体装置の第1実施例の一
部断面を示す外観図である。
FIG. 1 is an external view showing a partial cross section of a first embodiment of a semiconductor device according to the present invention.

【図2】 図1の線a−a′の部分で切断して示す断面
図である。
2 is a cross-sectional view taken along the line aa 'in FIG.

【図3】 この発明に係る半導体装置の第1実施例の製
造段階における半田バンプ作成前の断面図である。
FIG. 3 is a sectional view of a semiconductor device according to a first embodiment of the present invention before a solder bump is formed in a manufacturing stage.

【図4】 この発明に係る半導体装置の第1実施例の製
造工程を説明するための一部断面を示す外観図である。
FIG. 4 is an external view showing a partial cross section for explaining a manufacturing process of the first embodiment of the semiconductor device according to the present invention.

【図5】 この発明に係る半導体装置の第2実施例の一
部断面を示す外観図である。
FIG. 5 is an external view showing a partial cross section of a second embodiment of the semiconductor device according to the present invention.

【図6】 図5の線k−k′の部分で切断して示す断面
図である。
6 is a cross-sectional view taken along the line kk 'in FIG.

【図7】 この発明に係る半導体装置の第2実施例の製
造段階における樹脂封止前の状態を示す断面図である。
FIG. 7 is a cross-sectional view showing a state before resin sealing in a manufacturing stage of a second embodiment of a semiconductor device according to the present invention.

【図8】 この発明に係る半導体装置の第2実施例の製
造工程を説明するための一部断面図である。
FIG. 8 is a partial cross-sectional view for explaining the manufacturing process for the second embodiment of the semiconductor device according to the present invention.

【図9】 この発明に係る半導体装置の第3実施例の一
部を示す外観図である。
FIG. 9 is an external view showing a part of a third embodiment of the semiconductor device according to the present invention.

【図10】 この発明に係る半導体装置の第3実施例の
一部断面を示す外観図である。
FIG. 10 is an external view showing a partial cross section of a third embodiment of the semiconductor device according to the present invention.

【図11】 この発明に係る半導体装置の第3実施例の
実装時の一部を示す外観図である。
FIG. 11 is an external view showing a part of a semiconductor device according to a third embodiment of the present invention when it is mounted.

【図12】 図11の線b−b′の部分で切断して示す
断面図である。
12 is a cross-sectional view taken along the line bb 'in FIG.

【図13】 この発明に係る半導体装置の第4実施例の
一部を示す外観図である。
FIG. 13 is an external view showing a part of a fourth embodiment of the semiconductor device according to the present invention.

【図14】 この発明に係る半導体装置の第4実施例の
一部断面を示す外観図である。
FIG. 14 is an external view showing a partial cross section of a fourth embodiment of the semiconductor device according to the present invention.

【図15】 この発明に係る半導体装置の第4実施例の
実装時の一部を示す外観図である。
FIG. 15 is an external view showing a part of a semiconductor device according to a fourth embodiment of the present invention at the time of mounting.

【図16】 図15の線c−c′の部分で切断して示す
断面図である。
16 is a cross-sectional view taken along the line cc 'of FIG.

【図17】 この発明に係る半導体装置の第4実施例の
実装時の状態を示す平面図である。
FIG. 17 is a plan view showing a mounted state of the semiconductor device according to the fourth embodiment of the invention.

【図18】 この発明の第4実施例の半導体装置を複数
個実装した状態を示す平面図である。
FIG. 18 is a plan view showing a state in which a plurality of semiconductor devices according to the fourth embodiment of the present invention are mounted.

【図19】 この発明の第4実施例の半導体装置を複数
個実装した状態を示す平面図である。
FIG. 19 is a plan view showing a state in which a plurality of semiconductor devices according to the fourth embodiment of the present invention are mounted.

【図20】 この発明に係る半導体装置の第5実施例の
製造段階におけるリード加工工程前の一部断面を示す外
観図である。
FIG. 20 is an external view showing a partial cross section of the semiconductor device according to the fifth embodiment of the present invention before the lead processing step in the manufacturing stage.

【図21】 この発明に係る半導体装置の第5実施例の
実装時の一部を示す外観図である。
FIG. 21 is an external view showing a part of the semiconductor device according to the fifth embodiment of the present invention during mounting.

【図22】 図21の矢印dの方向から見た側面図であ
る。
22 is a side view seen from the direction of arrow d in FIG.

【図23】 この発明に係る半導体装置の第5実施例の
ベースリード、テープ、リングリード等の構成要素の一
部を示す外観図である。
FIG. 23 is an external view showing a part of components such as a base lead, a tape and a ring lead of a fifth embodiment of the semiconductor device according to the present invention.

【図24】 この発明に係る半導体装置の第6実施例の
一部断面を示す外観図である。
FIG. 24 is an external view showing a partial cross section of a sixth embodiment of the semiconductor device according to the present invention.

【図25】 図24の線e−e′の部分で切断して示す
断面図である。
FIG. 25 is a cross-sectional view taken along the line ee ′ of FIG. 24.

【図26】この発明に係る半導体装置の第7実施例の一
部断面を示す外観図である。
FIG. 26 is an external view showing a partial cross section of a seventh embodiment of the semiconductor device according to the present invention.

【図27】 図26の線f−f′の部分で切断して示す
断面図である。
27 is a cross-sectional view taken along the line ff ′ of FIG. 26.

【図28】 従来の半導体装置の一部断面を示す外観図
である。
FIG. 28 is an external view showing a partial cross section of a conventional semiconductor device.

【図29】 図28の線g−g′の部分で切断して示す
断面図である。
FIG. 29 is a cross-sectional view taken along the line gg ′ of FIG. 28.

【図30】 従来の半導体装置のZIPを示す外観図で
ある。
FIG. 30 is an external view showing a ZIP of a conventional semiconductor device.

【図31】 従来の半導体装置のZIPを示す側面図で
ある。
FIG. 31 is a side view showing a ZIP of a conventional semiconductor device.

【図32】 従来の半導体装置のSVPを示す外観図で
ある。
FIG. 32 is an external view showing an SVP of a conventional semiconductor device.

【図33】 従来の半導体装置のSVPをh方向から見
た側面図である。
FIG. 33 is a side view of the SVP of the conventional semiconductor device as seen from the h direction.

【図34】 図32の線j−j′の部分で切断して示す
断面図である。
FIG. 34 is a cross-sectional view taken along the line j-j ′ in FIG. 32.

【図35】 従来の半導体装置を示す断面図である。FIG. 35 is a cross-sectional view showing a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1A〜1G 半導体装置、2 半導体チップ、3 ボン
ディングパッド、5半田バンプ、6 封止樹脂、9 テ
ープ、10 導体層、11 金属細線、12開口部、1
3,30 架橋部、14 金属突起、15 櫛形導体
層、16 凸部、17 スタンドロック、18 基板、
19,27 配線、20 半田、22ベースリード、2
3 溝部、24 リングリード、25 櫛形部、26
TABテープ、28 内部リード、29 櫛形配線、3
2 位置決め凹部、33 スルーホール、34 逃げ凹
部。
1A to 1G Semiconductor device, 2 Semiconductor chip, 3 Bonding pad, 5 Solder bump, 6 Sealing resin, 9 Tape, 10 Conductor layer, 11 Metal fine wire, 12 Opening part, 1
3,30 bridge part, 14 metal projection, 15 comb-shaped conductor layer, 16 convex part, 17 stand lock, 18 substrate,
19,27 wiring, 20 solder, 22 base lead, 2
3 groove part, 24 ring lead, 25 comb part, 26
TAB tape, 28 internal leads, 29 comb-shaped wiring, 3
2 positioning recess, 33 through hole, 34 escape recess.

フロントページの続き (51)Int.Cl.6 識別記号 庁内整理番号 FI 技術表示箇所 H01L 21/321 23/02 B 23/28 Z 6921−4E 23/50 R Y Continuation of the front page (51) Int.Cl. 6 Identification code Office reference number FI Technical display location H01L 21/321 23/02 B 23/28 Z 6921-4E 23/50 RY

Claims (39)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップ上に設けられ、導体層を有
する接着部材と、 上記半導体チップ上に設けられた電極と上記導体層とを
電気的に接続する接続部材と、 上記半導体チップ、上記導体層、上記接着部材および上
記接続部材を樹脂封止する封止部材と、 この封止部材に設けられた開口部を介して上記導体層に
接続された外部電極とを備えたことを特徴とする半導体
装置。
1. An adhesive member provided on a semiconductor chip and having a conductor layer, a connecting member for electrically connecting an electrode provided on the semiconductor chip and the conductor layer, the semiconductor chip, and the conductor. A sealing member that seals the layer, the adhesive member, and the connecting member with resin, and an external electrode connected to the conductor layer through an opening provided in the sealing member. Semiconductor device.
【請求項2】 半導体チップ上に設けられ、導体層を有
する接着部材と、 上記半導体チップ上に設けられた電極と上記導体層とを
電気的に接続する接続部材と、 上記導体層上に設けられた金属突起と、 上記半導体チップ、上記導体層、上記接着部材、上記接
続部材および上記金属突起を樹脂封止しかつ上記金属突
起を一部外部に露出させる封止部材と、 上記外部に露出した金属突起と接続された外部電極とを
備えたことを特徴とする半導体装置。
2. An adhesive member provided on a semiconductor chip and having a conductor layer, a connecting member for electrically connecting an electrode provided on the semiconductor chip and the conductor layer, and provided on the conductor layer. And a sealing member that seals the semiconductor chip, the conductor layer, the adhesive member, the connecting member, and the metal protrusion with a resin and partially exposes the metal protrusion to the outside, and the exposed metal protrusion. A semiconductor device comprising: the metal protrusion and an external electrode connected to the metal protrusion.
【請求項3】 上記接着部材は、上記半導体チップ上に
設けられた電極と接続される櫛形導体層を有する請求項
1または2記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the adhesive member has a comb-shaped conductor layer connected to an electrode provided on the semiconductor chip.
【請求項4】 上記金属突起が露出している封止部材の
部分の周囲に凹部を設け、該凹部に上記外部電極の一部
を食い込ませた請求項2記載の半導体装置。
4. The semiconductor device according to claim 2, wherein a recess is provided around the portion of the sealing member where the metal protrusion is exposed, and a part of the external electrode is bitten into the recess.
【請求項5】 上記櫛形導体層は、電源供給または接地
電位用配線として使用される請求項3記載の半導体装
置。
5. The semiconductor device according to claim 3, wherein the comb-shaped conductor layer is used as a wiring for power supply or ground potential.
【請求項6】 半導体チップの一側に設けられ、導体層
を有する接着部材と、 上記半導体チップの他側に設け
られた電極と上記導体層とを電気的に接続する接続部材
と、 上記半導体チップ、上記導体層、上記接着部材および上
記接続部材を樹脂封止しかつ上記導体層の一側を外部に
露出させる封止部材とを備えたことを特徴とする半導体
装置。
6. An adhesive member provided on one side of a semiconductor chip and having a conductor layer, a connection member electrically connecting an electrode provided on the other side of the semiconductor chip to the conductor layer, and the semiconductor described above. A semiconductor device comprising: a chip, the conductor layer, the adhesive member, and a sealing member that seals the connecting member with a resin and exposes one side of the conductor layer to the outside.
【請求項7】 上記封止部材上に上記半導体チップの能
動面と垂直な方向に突出して設けられた支持部材を備え
た請求項6記載の半導体装置。
7. The semiconductor device according to claim 6, further comprising a support member provided on the sealing member so as to project in a direction perpendicular to the active surface of the semiconductor chip.
【請求項8】 半導体チップと離隔して設けられた導電
性の基本部材と、 この基本部材上に設けられ、導体層を有する接着部材
と、 上記半導体チップに設けられた第1および第2の電極と
上記導体層および上記基本部材とをそれぞれ電気的に接
続する接続部材と、 上記半導体チップ、上記基本部材、上記導体層、上記接
着部材および上記接続部材を樹脂封止しかつ少なくとも
上記基本部材と上記導体層の一側を外部に露出させる封
止部材とを備えたことを特徴とする半導体装置。
8. A conductive basic member provided separately from the semiconductor chip, an adhesive member provided on the basic member and having a conductor layer, and first and second conductive members provided on the semiconductor chip. A connecting member electrically connecting the electrode to the conductor layer and the basic member, respectively, and the semiconductor chip, the basic member, the conductor layer, the adhesive member and the connecting member are resin-sealed and at least the basic member. A semiconductor device comprising: a sealing member that exposes one side of the conductor layer to the outside.
【請求項9】 半導体チップと離隔して設けられた導電
性の基本部材と、 上記半導体チップと離隔しかつ上記基本部材の周囲に設
けられた導電性の環状部材と、上記基本部材上に設けら
れ、導体層を有する接着部材と、 上記半導体チップに設けられた第1、第2および第3の
電極と上記導体層、上記基本部材および上記環状部材と
をそれぞれ電気的に接続する接続部材と、 上記半導体チップ、上記基本部材、上記環状部材、上記
導体層、上記接着部材および上記接続部材を樹脂封止し
かつ少なくとも上記基本部材、上記環状部材および上記
導体層の一側を外部に露出させる封止部材とを備えたこ
とを特徴とする半導体装置。
9. A conductive basic member provided separately from a semiconductor chip, a conductive annular member provided apart from the semiconductor chip and around the basic member, and provided on the basic member. And an adhesive member having a conductor layer, and a connecting member electrically connecting the first, second and third electrodes provided on the semiconductor chip to the conductor layer, the basic member and the annular member, respectively. , The semiconductor chip, the basic member, the annular member, the conductor layer, the adhesive member and the connection member are resin-sealed and at least one side of the basic member, the annular member and the conductor layer is exposed to the outside. A semiconductor device comprising a sealing member.
【請求項10】 上記封止部材より露出した上記基本部
材は支持用として使用される請求項8または9記載の半
導体装置。
10. The semiconductor device according to claim 8, wherein the basic member exposed from the sealing member is used for supporting.
【請求項11】 上記導体層は上記封止部材より0.2〜
1.0mm程度露出される請求項8〜10のいずれかに記載
の半導体装置。
11. The conductor layer is 0.2 to 0.2 mm thicker than the sealing member.
The semiconductor device according to claim 8, which is exposed by about 1.0 mm.
【請求項12】 上記封止部材より露出した上記導体層
は実装時基板上の配線と接続する際のヒンジとして使用
される請求項8〜11のいずれかに記載の半導体装置。
12. The semiconductor device according to claim 8, wherein the conductor layer exposed from the sealing member is used as a hinge when connecting to a wiring on a board during mounting.
【請求項13】 上記基本部材は接地電位用として使用
される請求項8〜12のいずれかに記載の半導体装置。
13. The semiconductor device according to claim 8, wherein the basic member is used for ground potential.
【請求項14】 上記基本部材は上記電極側の表面を露
出され、該露出部がワイヤボンディング可能とされてい
る請求項8〜13のいずれかに記載の半導体装置。
14. The semiconductor device according to claim 8, wherein the surface of the basic member on the electrode side is exposed, and the exposed portion is wire-bondable.
【請求項15】 上記封止部材の上記基本部材が露出し
ている部分に溝部を設けた請求項8〜14のいずれかに
記載の半導体装置。
15. The semiconductor device according to claim 8, wherein a groove is provided in a portion of the sealing member where the basic member is exposed.
【請求項16】 上記基本部材と上記環状部材は上記電
極を挟んで相互に対向した位置に配置される請求項8〜
15のいずれかに記載の半導体装置。
16. The basic member and the annular member are arranged at positions facing each other with the electrode interposed therebetween.
16. The semiconductor device according to any one of 15.
【請求項17】 上記基本部材と上記環状部材は、電源
供給または接地電位用配線として使用される請求項8〜
16のいずれかに記載の半導体装置。
17. The basic member and the annular member are used for power supply or ground potential wiring.
16. The semiconductor device according to any one of 16.
【請求項18】 上記基本部材の一側は、上記接着部材
および上記導体層に対向する部分以外は削除されて櫛形
をなす請求項8〜17のいずれかに記載の半導体装置。
18. The semiconductor device according to claim 8, wherein one side of the basic member has a comb shape except for a portion facing the adhesive member and the conductor layer.
【請求項19】 半導体チップ上に設けられた接着部材
と、 この接着部材より延在して上記半導体チップ上に設けら
れた電極と電気的に接続される配線部材と、 上記半導体チップ、上記接着部材および上記配線部材を
樹脂封止する封止部材と、 この封止部材に設けられた
開口部を介して上記配線部材に接続された外部電極とを
備えたことを特徴とする半導体装置。
19. An adhesive member provided on a semiconductor chip, a wiring member extending from the adhesive member and electrically connected to an electrode provided on the semiconductor chip, the semiconductor chip, and the adhesive. A semiconductor device comprising: a member and a sealing member for sealing the wiring member with a resin; and an external electrode connected to the wiring member through an opening provided in the sealing member.
【請求項20】 半導体チップ上に設けられた接着部材
と、 この接着部材より延在して上記半導体チップ上に設けら
れた電極と電気的に接続される配線部材と、 上記半導体チップ、上記接着部材および上記配線部材を
樹脂封止しかつ上記配線部材の一側を所定の段差を持っ
て外部に露出させる封止部材とを備えたことを特徴とす
る半導体装置。
20. An adhesive member provided on a semiconductor chip, a wiring member extending from the adhesive member and electrically connected to an electrode provided on the semiconductor chip, the semiconductor chip, the adhesive A semiconductor device, comprising: a member and a wiring member that seals the wiring member with a resin; and a sealing member that exposes one side of the wiring member to the outside with a predetermined step.
【請求項21】 上記接着部材がTABテープである請
求項19または20記載の半導体装置。
21. The semiconductor device according to claim 19, wherein the adhesive member is a TAB tape.
【請求項22】 上記接着部材がTABテープであり、
該TABテープ上の配線部材を外部電極として用いる請
求項19または20記載の半導体装置。
22. The adhesive member is a TAB tape,
21. The semiconductor device according to claim 19, wherein the wiring member on the TAB tape is used as an external electrode.
【請求項23】 上記封止部材は実装時基板と対接する
部分に該基板の配線と嵌合する位置決め凹部を有する請
求項20〜22記載の半導体装置。
23. The semiconductor device according to claim 20, wherein the sealing member has a positioning recess that is fitted to the wiring of the board at a portion facing the board when mounted.
【請求項24】 上記封止部材は実装時基板と対接する
部分に基板上のスルーホール等との干渉を防ぐための逃
げ凹部を有する請求項20〜23のいずれかに記載の半
導体装置。
24. The semiconductor device according to claim 20, wherein the sealing member has an escape recess for preventing interference with a through hole or the like on the substrate at a portion facing the substrate during mounting.
【請求項25】 半導体チップ上に導体層を有する接着
部材を貼着す工程と、 上記半導体チップ上に電極を形成する工程と、 上記電極と上記導体層とを電気的に接続する工程と、 上記半導体チップ、上記導体層、上記接着部材を樹脂封
止する工程と、 この封止樹脂に上記導体層に達する開口部を形成する工
程と、 上記開口部に半田を充填して外部電極を形成する工程と
を含むことを特徴とする半導体装置の製造方法。
25. A step of attaching an adhesive member having a conductor layer on a semiconductor chip, a step of forming an electrode on the semiconductor chip, and a step of electrically connecting the electrode and the conductor layer. A step of resin-sealing the semiconductor chip, the conductor layer, and the adhesive member, a step of forming an opening reaching the conductor layer in the sealing resin, and a solder is filled in the opening to form an external electrode. A method of manufacturing a semiconductor device, comprising:
【請求項26】 上記開口部を樹脂封止する際の金型に
設けられた突起により形成する請求項25記載の半導体
装置の製造方法。
26. The method of manufacturing a semiconductor device according to claim 25, wherein the opening is formed by a protrusion provided on a mold for resin sealing.
【請求項27】 上記開口部を樹脂封止する際の金型に
設けられた突起を上記導体層に所定の深さだけ押し込む
ように上記半導体チップと上記接着部材を上記金型内に
設置し、樹脂封止する請求項25または26記載の半導
体装置の製造方法。
27. The semiconductor chip and the adhesive member are set in the mold so that a protrusion provided on the mold when resin-sealing the opening is pressed into the conductor layer by a predetermined depth. 27. The method of manufacturing a semiconductor device according to claim 25, wherein the method is resin-sealing.
【請求項28】 上記半導体チップと上記接着部材を上
記金型内に設置する位置を保持するのに、上記接着部材
の架橋部を上記金型で挟むようにした請求項25〜27
のいずれかに記載の半導体装置の製造方法。
28. In order to hold a position where the semiconductor chip and the adhesive member are installed in the mold, a bridge portion of the adhesive member is sandwiched between the molds.
A method for manufacturing a semiconductor device according to any one of 1.
【請求項29】 上記開口部に半田ボールを乗せ、リフ
ローにより上記外部電極を形成する請求項25〜28の
いずれかに記載の半導体装置の製造方法。
29. The method of manufacturing a semiconductor device according to claim 25, wherein a solder ball is placed on the opening, and the external electrode is formed by reflow.
【請求項30】 半導体チップ上に導体層を有する接着
部材を貼着する工程と、 上記半導体チップ上に電極を形成する工程と、 上記電極と上記導体層とを電気的に接続する工程と、 上記導体層上にワイヤボンディング法により金属突起を
形成する工程と、 上記半導体チップ、上記導体層、上記接着部材および上
記金属突起を樹脂封止しかつ上記金属突起を一部外部に
露出させる工程と、 上記外部に露出した金属突起と接続される外部電極を形
成する工程とを含むことを特徴とする半導体装置の製造
方法。
30. A step of attaching an adhesive member having a conductor layer on a semiconductor chip, a step of forming an electrode on the semiconductor chip, and a step of electrically connecting the electrode and the conductor layer. A step of forming a metal protrusion on the conductor layer by a wire bonding method; a step of resin-sealing the semiconductor chip, the conductor layer, the adhesive member, and the metal protrusion and exposing the metal protrusion to a part of the outside. And a step of forming an external electrode connected to the metal protrusion exposed to the outside, the method of manufacturing a semiconductor device.
【請求項31】 上記金属突起を一部外部に露出させる
工程において、上記金属突起の高さを、該金属突起の切
り残し量を調整し、該調整された金属突起を樹脂封止の
際に樹脂封止金型に押し付けるように樹脂封止して上記
金属突起の一部を露出させる請求項30記載の半導体装
置の製造方法。
31. In the step of partially exposing the metal protrusion to the outside, the height of the metal protrusion is adjusted by adjusting the uncut amount of the metal protrusion, and the adjusted metal protrusion is sealed with a resin. 31. The method of manufacturing a semiconductor device according to claim 30, wherein a part of the metal protrusion is exposed by resin-sealing so as to press the resin-molding die.
【請求項32】 半導体チップの一側に導体層を有する
接着部材を貼着する工程と、 上記半導体チップの他側に電極を形成する工程と、 上記電極と上記導体層とを電気的に接続する工程と、 上記半導体チップ、上記導体層および上記接着部材を樹
脂封止しかつ上記導体層の一側を外部に露出させる工程
とを含むことを特徴とする半導体装置の製造方法。
32. A step of adhering an adhesive member having a conductor layer on one side of the semiconductor chip, a step of forming an electrode on the other side of the semiconductor chip, and an electrical connection between the electrode and the conductor layer. And a step of sealing the semiconductor chip, the conductor layer and the adhesive member with a resin and exposing one side of the conductor layer to the outside.
【請求項33】 半導体チップと離隔して導電性の基本
部材を配置する工程と、 上記基本部材上に導体層を有する接着部材を貼着する工
程と、 上記半導体チップに第1および第2の電極を形成する工
程と、上記第1および第2の電極とと上記導体層および
上記基本部材とをそれぞれ電気的に接続する工程と、 上記半導体チップ、上記基本部材、上記導体層および上
記接着部材を樹脂封止しかつ少なくとも上記基本部材と
上記導体層の一側を外部に露出させる工程とを含むこと
を特徴とする半導体装置の製造方法。
33. A step of disposing a conductive basic member at a distance from a semiconductor chip, a step of adhering an adhesive member having a conductor layer on the basic member, and a first and second step on the semiconductor chip. A step of forming electrodes, a step of electrically connecting the first and second electrodes to the conductor layer and the basic member, respectively, the semiconductor chip, the basic member, the conductor layer and the adhesive member And a step of exposing at least one side of the conductor layer to the outside, and a method of manufacturing a semiconductor device.
【請求項34】 半導体チップと離隔して導電性の基本
部材を配置する工程と、 上記半導体チップと離隔しかつ上記基本部材の周囲に導
電性の環状部材を配置する工程と、上記基本部材上に導
体層を有する接着部材を貼着する工程と、 上記半導体チップに第1、第2および第3の電極を形成
する工程と、 上記第1、第2および第3の電極と上記導体層、上記基
本部材および上記環状部材とをそれぞれ電気的に接続す
る工程と、 上記半導体チップ、上記基本部材、上記環状部材、上記
導体層および上記接着部材を樹脂封止しかつ少なくとも
上記基本部材、上記環状部材および上記導体層の一側を
外部に露出させる工程とを含むことを特徴とする半導体
装置の製造方法。
34. A step of disposing a conductive basic member at a distance from a semiconductor chip; a step of disposing a conductive annular member at a distance from the semiconductor chip and around the basic member; A step of attaching an adhesive member having a conductor layer to the semiconductor chip, a step of forming first, second and third electrodes on the semiconductor chip, the first, second and third electrodes and the conductor layer, Electrically connecting the basic member and the annular member, respectively, and sealing the semiconductor chip, the basic member, the annular member, the conductor layer and the adhesive member with resin and at least the basic member, the annular A step of exposing a member and one side of the conductor layer to the outside, and a method of manufacturing a semiconductor device.
【請求項35】 半導体チップ上に接着部材を貼着する
工程と、 上記半導体チップ上に電極を形成する工程と、 上記電極と上記接着部材より延在する配線部材を電気的
に接続する工程と、 上記半導体チップ、上記接着部材および上記配線部材を
樹脂封止する工程と、 この封止樹脂に上記導体層に達する開口部を形成する工
程と、 上記開口部に半田を充填して外部電極を形成する工程と
を含むことを特徴とする半導体装置の製造方法。
35. A step of adhering an adhesive member on a semiconductor chip, a step of forming an electrode on the semiconductor chip, and a step of electrically connecting the electrode and a wiring member extending from the adhesive member. A step of resin-sealing the semiconductor chip, the adhesive member, and the wiring member; a step of forming an opening reaching the conductor layer in the sealing resin; and filling the opening with solder to form an external electrode. And a step of forming the semiconductor device.
【請求項36】 半導体チップ上に接着部材を貼着する
工程と、 上記半導体チップ上に電極を形成する工程と、 上記電極と上記接着部材より延在する配線部材を電気的
に接続する工程と、この接着部材より延在して上記半導
体チップ上に設けられた電極と電気的に接続される配線
部材と、 上記半導体チップ、上記接着部材および上記配線部材を
樹脂封止しかつ上記配線部材の一側を所定の段差を持っ
て外部に露出させる工程とを含むことを特徴とする半導
体装置の製造方法。
36. A step of adhering an adhesive member on a semiconductor chip, a step of forming an electrode on the semiconductor chip, and a step of electrically connecting the electrode and a wiring member extending from the adhesive member. A wiring member which extends from the adhesive member and is electrically connected to an electrode provided on the semiconductor chip, and the semiconductor chip, the adhesive member and the wiring member are resin-sealed and And a step of exposing one side to the outside with a predetermined step, the method for manufacturing a semiconductor device.
【請求項37】 半導体装置を基板に対して垂直に配置
し、 上記半導体装置内の半導体チップの一側に貼着された接
着部材上の導体層を上記基板の配線と電気的に接続する
ようにしたことを特徴とする半導体装置の実装方法。
37. A semiconductor device is arranged vertically to a substrate, and a conductor layer on an adhesive member attached to one side of a semiconductor chip in the semiconductor device is electrically connected to wiring of the substrate. A method for mounting a semiconductor device, comprising:
【請求項38】 半導体装置の樹脂封止部分に設けられ
た溝部の内、基本部材を曲げるために用いられていない
溝部に隣接する他の半導体装置の支持部材を潜り込ませ
て実装するようにしたことを特徴とする半導体装置の実
装方法。
38. A supporting member for another semiconductor device, which is adjacent to a groove not used for bending a basic member among the grooves provided in the resin-sealed portion of the semiconductor device, is mounted by being embedded therein. A method for mounting a semiconductor device, comprising:
【請求項39】 半導体装置の半導体チップ表面側の樹
脂表面に配線部材の貼着された接着部材を露出させるよ
うに樹脂封止し、上記接着部材上の配線部材と半導体装
置の樹脂表面との段差を所定値に抑え、上記接着部材上
の配線部材を基板に対向するように実装し、上記接着部
材上の配線部材を上記基板の配線と電気的に接続するよ
うにしたことを特徴とする半導体装置の実装方法。
39. A resin is sealed so as to expose an adhesive member to which a wiring member is adhered, on a resin surface on the semiconductor chip surface side of the semiconductor device, and the wiring member on the adhesive member and the resin surface of the semiconductor device are separated from each other. The step is suppressed to a predetermined value, the wiring member on the adhesive member is mounted so as to face the substrate, and the wiring member on the adhesive member is electrically connected to the wiring of the substrate. Semiconductor device mounting method.
JP17102094A 1994-07-22 1994-07-22 Semiconductor device, its manufacturing method and mounting method Expired - Fee Related JP3150253B2 (en)

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DE19526511A DE19526511A1 (en) 1994-07-22 1995-07-20 PCB mounting applications of an encapsulated semiconductor package
KR1019950022303A KR100201168B1 (en) 1994-07-22 1995-07-22 Semiconductor device, manufacture thereof and its mounting method

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JP3150253B2 (en) 2001-03-26
KR100201168B1 (en) 1999-06-15
KR960005966A (en) 1996-02-23

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