JPH0837449A - Latch circuit - Google Patents

Abstract

PURPOSE:To obtain a self-adjustment function to avoid a meta-stable state by setting a capability ratio of P-channel and N-channel transistors(TRs) of a feedback loop inverter largely different from the capability of P-channel and N-channel TRs of an inverter. CONSTITUTION:A transfer gate 1 is closed by applying asynchronous data to an input terminal IN and an H level to a clock CLK, and then data are passed. The data are stored by an inverter 3 and a feedback loop inverter 4. In this case, a transfer gate 2 is open. When the level of the clock CLK changes from H into L, and when the asynchronous data are changed at the moment when the gate 1 is ON to OFF and the gate 2 changes from OFF to ON, a node 11 reaches an intermediate potential and malfunction may take place. However, an inverter outputs a level being an intermediate level MH or over and an intermediate level ML or below. Thus, the meta-stable state of the node 11 is avoided and passes through the inverter 3, then a potential of a node 12 is confirmed to an H or L level. Thus, the output of an output terminal OUT is confirmed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a latch circuit for preventing malfunction due to a metastable state.

[0002]

2. Description of the Related Art FIG. 1 shows a general latch circuit. Reference numerals 1 and 2 are transfer gates, 3 is an inverter, 4 is a feedback loop inverter, and 5 is an output inverter. Inverter 5
Is connected in series to the output path from the first transfer gate 1, and the feedback loop inverter 4 includes a node 12 which is a connection point between the inverter 3 and the output inverter 5 and a first transfer gate 2 through a second transfer gate 2. It is connected to a feedback path leading to a node 11 which is a connection point between the gate 1 and the inverter 3. The drive capacity of the inverter is inverter 3> feedback loop inverter 4.

In the conventional circuit as described above, the Pch transistor and Nch transistor capability ratios of the inverter 3, the feedback loop inverter 4, and the output inverter 5 are often the same.

Next, the operation will be described. In Fig. 1, asynchronous data is input to the input terminal IN, and the clock CLK is
When the H ″ level is applied, the transfer gate 1 is turned on, data passes therethrough and reaches the node 11. After that, the level of the node 12 is also determined through the inverter 3. This data is then fed back to the inverter 3 and the feedback. It is stored by the loop inverter 4. At this time, the transfer gate 2 is OFF.

[0005]

Here, the clock CLK is used.
Changes from “H” level to “L” level, and when the asynchronous data changes at the moment when the transfer gate 1 changes from ON to OFF and the transfer gate 2 changes from OFF to ON, the node 11 becomes an intermediate potential and passes through the inverter 3. The node 12 may be in a potential indefinite state (meta-stable state) for a certain period of time, causing a malfunction. Also, when the asynchronous data input is indefinite, such as when the power is turned on, the same metastable state may occur, and malfunction may occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a latch circuit which prevents a metastable state by the latch circuit itself without adding new hardware and does not cause a malfunction. .

[0007]

In order to solve the above problems, the latch circuit of the present invention is the circuit of FIG. 1 in which the Pch transistor / Nch transistor capability ratio of the feedback loop inverter 4 is set to the Pch transistor of the inverters 3 and 5. , Nch transistor capability ratio is largely removed from the setting.

[0008]

With the above configuration, the metastable state is avoided by the latch circuit itself, the level of the output terminal is fixed, and malfunction is prevented.

[0009]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a latch circuit according to an embodiment of the present invention, which is the same as a general latch circuit except for inverter performance. In FIG. 1, an inverter 3 and an output inverter 5 are Pch transistors, N
The ch transistor capability ratio is set to the same ratio, and the feedback loop inverter 4 has a switching level of H
The transistor capability ratio is set to Pch transistor> Nch transistor so that the intermediate level M _H is close to the level, or the Pch transistor <is set so that the switching level is an intermediate level M _L close to the L level.
It is configured by an Nch transistor.

The input / output waveforms of the inverter 3 and the output inverter 5 are shown in FIG. 2 (a), and the input / output waveforms of the feedback loop inverter 4 are shown in FIGS. 2 (b) and 2 (c). The drive capacity of the inverter is inverter 3> feedback loop inverter 4.

Next, the operation will be described. In Fig. 1, asynchronous data is input to the input terminal IN, and the clock CLK is
By applying "H", the transfer gate 1 is turned on, and the data passes through.
Inverter 3 and feedback loop inverter 4
Stored by. At this time, the transfer gate 2 is O
It is FF.

Here, the clock CLK changes from "H" level to "L" level, and the transfer gate 1 is turned on.
If the asynchronous data changes at the moment when the transfer gate 2 changes from OFF to the transfer gate 2 changes from OFF to ON, the node 11 becomes the intermediate potential and the node 12 enters the metastable state via the inverter 3, which may cause a malfunction.

However, since the input / output waveform of the feedback loop inverter 4 obtains the characteristic of FIG. 2B or 2C in the circuit of this embodiment, the output of the feedback loop inverter 4 is above M _H or below M _L. Output the level of. Therefore, the metastable state of the node 11 is avoided, and the potential of the node 12 is fixed at "H" level or "L" level by passing through the inverter 3.

As a result, the fixed level of the output terminal OUT is output, and malfunction can be prevented. Also, when asynchronous data input is undefined due to power-on, etc.,
The feedback loop inverter 4 works to avoid the metastable state, and the level of the output terminal OUT can be fixed to prevent malfunction.

[0015]

As described above, according to the present invention, the metastable avoidance function can be easily added to the inside of the latch circuit, and the effect of preventing the malfunction due to the metastable state can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an example of a latch circuit used in an embodiment of the present invention.

FIG. 2 is a characteristic diagram showing an input / output waveform of each inverter in the latch circuit according to the embodiment of the present invention.

[Explanation of symbols]

 1, 2 Transfer gate 3 Inverter 4 Feedback loop inverter 5 Output inverter 11 and 12 Latch circuit internal node

Claims (1)

[Claims] 1. A latch circuit comprising a feedback loop inverter having a Pch transistor / Nch transistor capability ratio different from that of a data output path inverter.