JPH083960B2 - Data processing device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a data processing device having a memory capable of writing and reading digital data.

<Prior Art> With the recent increase in memory capacity and miniaturization, a memory capable of storing one screen of a television signal (for example, a so-called frame memory) has come to be used in consumer equipment, For example, it has become possible to obtain good special playback images used in VTR still image playback and slow motion playback.

On the other hand, the present applicant has proposed a system for digitally recording a still image on a VTR separately from an analog video signal using the above memory. (See Japanese Patent Application No. 60-276125)
With this system, it has become possible to record and reproduce still images of extremely high quality even in consumer VTRs.

FIG. 3 shows the simplest configuration for writing and reading a video signal to and from the frame memory. In FIG. 3, reference numeral 1 is an analog video signal input terminal, and 2 is an analog-digital (A / D) converter for converting the input analog video signal into a digital signal 3. The digital signal output from the A / D converter 2 is written into and read from the memory 4 according to the address given by the address generator 8. The digital signal read from the memory 4 is converted into an analog signal by the digital-analog (D / A) converter 6 and output from the output terminal 7.

The writing and reading operations to and from the memory 4 will be described with reference to the timing chart of FIG. The write operation and the read operation to the memory 4 are performed in a time division manner. The read operation is performed in the first half and the write operation is performed in the latter half of the period in which the address generator 8 specifies the same address. This switching between reading and writing is performed by a write control signal (shown in FIG. 4 (d)) given to the memory 4 from the address generator 8.

In the timing chart of FIG. 4, (a) is an address given by the address generator 8, (b) is a digital signal output from the memory 4, (c) is a digital signal input to the memory 4, and (d) is This is a write control signal.
In this timing chart, the cycle time T of writing / reading of the memory 4 is the same as the sampling cycle of the A / D converter 2. When the operation of the memory 4 is slow and the cycle time can be set only longer than the sampling cycle (that is, when the shortest cycle time that can be set in the memory 4 is longer than the sampling cycle), the memories are provided in parallel. For example, when viewed as one of these memories, the cycle time can be equivalently matched with the sampling period.

In the figure, the digital signal output from the memory 4 is slightly behind the addressing timing, but this is based on the access time due to the structural characteristics of the memory, and is written after the output of the memory 4 is fixed once. If the operation is performed, the output of the memory 4 becomes indefinite. Therefore, a latch circuit is actually provided at the output end of the memory 4, and the latch circuit is used to hold the memory output before the D / A converter 6
To send a signal to.

As long as the memory 4 is operating as described above, the contents of the memory are constantly rewritten to new ones. However, if writing is prohibited by always setting the write control signal (d) to the low level, it is stored in the memory 4. It is also possible to retain the contents that have been set. For example, even when a moving image signal is input to the terminal 1, a still image can be output from the memory 4.

Next, FIG. 5 shows another conventional configuration example for writing and reading a video signal to and from the frame memory. In FIG. 5, the same components as those in FIG. 3 are designated by the same reference numerals, and the description thereof will be omitted. In the configuration shown in FIG. 5, the digital signal from the A / D converter 2 is written to the memory 4 according to the address from the write address generator 10, and the digital signal from the read address generator 11 to the D / A converter 6 according to the address. Provides a digital signal. Reference numeral 12 is a manual operation unit for designating a read address.

As a result, the write address and the read address can be made different, special effects such as image enlargement, reduction, and inversion can be obtained, and further, the transmission rate of the input digital signal and the output digital signal can be made different. Etc. can be done easily.

FIG. 6 is a timing chart for explaining the operation of the memory of FIG. 5, in which (a) shows write (W) and read (R) addresses, and (b), (c),
(D) is similar to FIG. In the figure, the read cycle t _RC and the write cycle t _WC of the memory usually have the same value due to the circuit configuration. Therefore, in this case, the sampling period of the A / D converter 2 is (t _RC + t _WC ), and the operation of the memory 4 in FIG. 5 must be performed at twice the speed of the operation of the memory 4 in FIG. High-speed memory is required.

<Problems to be Solved by the Invention> In the frame memory of FIG. 5, when a still image is to be output, writing is prohibited, but the write address given to the memory 4 is completely useless. The efficiency of memory usage in time was reduced by half.

The present invention has been made in view of the circumstances as described above, and it is possible to effectively use the memory and to increase the amount of information read from the memory per unit time without increasing the speed of the memory itself. The purpose is to provide a device.

<Means for Solving Problems> With the above object, the data processing device of the present invention is
A memory in which a write address and a read address can be set independently of each other when writing and reading digital data alternately, and a digital-analog converter that converts digital data read from the memory into analog data The memory independently sets the read and write addresses of the data read cycle from the memory and the operation cycle of the digital-analog converter when the memory sequentially changes the read address and only reads the data. The data is set to be half the size of the data written and read alternately.

<Operation> With the configuration as described above, data that can be read from the memory per single time without using a memory that can operate at high speed, that is, without using a memory that can rewrite write / read addresses at high speed. It has become possible to increase the amount of information and to effectively use the memory.

Example An example of the present invention will be described below.

FIG. 1 is a diagram showing a schematic configuration of a data processing apparatus as an embodiment of the present invention. In FIG. 1, the same components as those in FIG.

The operation for writing and reading a digital signal in the memory 4 is exactly the same as in the case of FIG. 5, and the read address generator 11 divides the clock generated by the clock generator 13 into 1/2 frequency dividers. It is supplied through the A terminal of the switch 14 and the switch 15, and the read address is updated at a predetermined timing. On the other hand, the clock generated from the clock generator 13 is supplied to the D / A converter 6 through the 1/2 divider 16 and the A terminal of the switch 17, and the memory 4
Is operating in the cycle that outputs data.

The address given to the memory 4 at this time is as shown in FIG. 2 (a), which is the same as in FIG. 6 (a).
The digital signal output from the memory 4 is also the same as in FIG. 6 (b) as shown in FIG. 2 (c).

Next, the operation when outputting a still image will be described. When a still image output is ordered from the manual operation unit 12, the switch 15,1
7 are both connected to the B terminal, the clock output from the clock generator 13 is directly supplied to the read address generator 11 via the B terminal of the switch 15, and the clock output from the clock generator 13 is directly switched to the switch 17 It is supplied to the D / A converter 6 via the B terminal of. Therefore, the address switching cycle of the read address generator 11 and the operation cycle of the D / A converter 6 are each halved. FIG. 2B shows a read address when outputting a still image, and FIG. 2D shows a digital signal output from the memory 4.

As described above, according to the configuration of FIG. 1, the amount of read information per unit time is doubled when only reading is performed as compared to when writing and reading are performed. An additional configuration when such data processing is performed will be briefly described below.

In recent years, as a method of doubling the number of scanning lines per field of a normal interlaced scanning type television signal, non-interlaced display is possible on an output monitor to display an image without interlace interference, and it is dedicated The device has also been developed. However, according to the above configuration, the amount of information read from the memory 4 is doubled, so that the number of scanning lines can be easily doubled. Therefore, according to the above configuration, it is possible to obtain an output image by a normal interlaced scanning method for a moving image and a non-interlaced output image having a double scanning line number for a still image.

At this time, since the synchronizing signal is different between the interlaced scanning video signal and the non-interlaced scanning video signal, it goes without saying that two types of synchronizing signal adding circuits must be provided after the output terminal 7.

<Effects of the Invention> As described above, according to the present invention, a simple circuit is added without increasing the operation speed of the memory, that is, without increasing the rewriting speed of the write / read address. Only with this, it is possible to increase the information amount of data that can be read from the memory per unit time.

[Brief description of drawings]

FIG. 1 is a diagram showing a main configuration of an embodiment of a data processing device of the present invention, FIG. 2 is a timing chart for explaining the operation of the memory of FIG. 1, and FIG. 3 is a conventional data processing device. FIG. 4 is a timing chart for explaining the operation of the memory shown in FIG. 3, FIG. 5 is a diagram showing another example of the conventional data processing device, and FIG. 6 is a diagram shown in FIG. 6 is a timing chart for explaining the operation of the memory. In the figure, 2 is an A / D converter, 4 is a memory, 6 is a D / A converter, 10
Is a write address generator, 11 is a read address generator, 12 is a manual operation unit, 13 is a clock generator, and 14 and 1
6 is a frequency divider, and 15 and 17 are switches.

Front page continued (72) Inventor Hirohisa Takahashi 770 Shimonoge, Takatsu-ku, Kawasaki-shi, Kanagawa Canon Inc., Tamagawa Plant In the office

Claims (1)

[Claims] 1. A memory in which a write address and a read address can be set independently of each other when writing and reading digital data are alternately performed, and a digital which converts digital data read from the memory into analog data. An analog converter, wherein the memory writes the data read cycle from the memory and the operation cycle of the digital-analog converter when the memory sequentially changes the read address and only reads data. The data processing device is characterized in that the read address and the read address are independently set to halve those when data is written and read alternately.