JPH084152B2 - Semiconductor light emitting device - Google Patents

Semiconductor light emitting device

Info

Publication number
JPH084152B2
JPH084152B2 JP9580386A JP9580386A JPH084152B2 JP H084152 B2 JPH084152 B2 JP H084152B2 JP 9580386 A JP9580386 A JP 9580386A JP 9580386 A JP9580386 A JP 9580386A JP H084152 B2 JPH084152 B2 JP H084152B2
Authority
JP
Japan
Prior art keywords
electrode
light emitting
semiconductor light
emitting device
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP9580386A
Other languages
Japanese (ja)
Other versions
JPS62252180A (en
Inventor
明 水由
浩彰 木下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Cable Industries Ltd
Original Assignee
Mitsubishi Cable Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Cable Industries Ltd filed Critical Mitsubishi Cable Industries Ltd
Priority to JP9580386A priority Critical patent/JPH084152B2/en
Publication of JPS62252180A publication Critical patent/JPS62252180A/en
Publication of JPH084152B2 publication Critical patent/JPH084152B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/022—Mountings; Housings
    • H01S5/0233—Mounting configuration of laser chips
    • H01S5/02345—Wire-bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
    • H01S5/042—Electrical excitation ; Circuits therefor
    • H01S5/0425—Electrodes, e.g. characterised by the structure
    • H01S5/04254—Electrodes, e.g. characterised by the structure characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
    • H01S5/18—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities
    • H01S5/183—Surface-emitting [SE] lasers, e.g. having both horizontal and vertical cavities having only vertical cavities, e.g. vertical cavity surface-emitting lasers [VCSEL]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires

Landscapes

  • Led Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Lasers (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体発光素子に関し、詳細には半導体発
光素子の表面電極の構造に関するものである。Description: TECHNICAL FIELD The present invention relates to a semiconductor light emitting device, and more particularly to a structure of a surface electrode of the semiconductor light emitting device.

〔従来の技術〕[Conventional technology]

発光ダイオードや半導体レーザ等の半導体素子等の表
面電極、たとえば発光ダイオードの表面電極は、第３図
に示すように、シングルヘテロまたはダブルヘテロ構造
を有する平板部Ｂの上面の中央に円板形状の電極E1が、
平板部Ｂの下面の全面に電極E2がそれぞれ形成されてい
る。このような発光ダイオードを実際に使用するには、
電極E2をたとえばステム電極10にダイボンディングによ
り取り付け、電極E1とリード端子11とを金等のワイヤ12
を用いてワイヤボンディングによって接続する。As shown in FIG. 3, a surface electrode of a semiconductor element such as a light emitting diode or a semiconductor laser, for example, a surface electrode of a light emitting diode has a disk-shaped central portion on the upper surface of a flat plate portion B having a single hetero structure or a double hetero structure. Electrode E1 is
Electrodes E2 are formed on the entire lower surface of the flat plate portion B, respectively. To actually use such a light emitting diode,
The electrode E2 is attached to the stem electrode 10 by die bonding, for example, and the electrode E1 and the lead terminal 11 are connected to the wire 12 such as gold.
Are connected by wire bonding.

〔発明が解決しようとする問題点〕[Problems to be solved by the invention]

しかしながら、平板部Ｂの上面の電極E1は一般に円板
状でかつ小さくしかも平板部Ｂの表面に突出する状態に
形成したものであるため、たとえば電極E1とリード端子
11とを接続する際に、ワイヤボンディングによって電極
E1にワイヤ12の一端を接着した後にワイヤ12を引っ張る
と、電極E1が平板部Ｂの上面から剥がれてしまうことが
ある。However, since the electrode E1 on the upper surface of the flat plate portion B is generally formed in a disk shape and is small and protrudes from the surface of the flat plate portion B, for example, the electrode E1 and the lead terminal.
When connecting with 11, the electrode by wire bonding
If the wire 12 is pulled after adhering one end of the wire 12 to E1, the electrode E1 may peel off from the upper surface of the flat plate portion B.

従って本発明の目的は、ワイヤボンディングを行う際
に半導体発光素子の表面電極が剥がれ難く構成した半導
体発光素子を提供することにある。Therefore, an object of the present invention is to provide a semiconductor light emitting device having a structure in which the surface electrode of the semiconductor light emitting device is not easily peeled off during wire bonding.

〔問題点を解決するための手段〕[Means for solving problems]

前記目的は、素子の電極形成面に形成された溝に、ワ
イヤボンディングによる接続用の電極を設けてなり、当
該溝の断面形状が、その開口部と底部との間に、該開口
部と同幅であるか、もしくは該開口部より幅広である部
分を有し、該電極の上面部が素子の電極形成面と同高と
なっていることを特徴とする半導体発光素子により達成
される。The object is to provide an electrode for connection by wire bonding in a groove formed on the electrode formation surface of the element, and the cross-sectional shape of the groove is the same as that of the opening between the opening and the bottom. This is achieved by a semiconductor light emitting device characterized in that it has a width or a part wider than the opening, and the upper surface of the electrode is flush with the electrode formation surface of the device.

〔実施例〕〔Example〕

以下、本発明の半導体発光素子を図面に基づいて説明
する。Hereinafter, a semiconductor light emitting device of the present invention will be described with reference to the drawings.

本発明の半導体発光素子の一実施例を、よく知られて
いるAlGaAs/GaAs系0.66μｍ発光波長の面発光ダイオー
ドを例にとって説明する。第１図（ｅ）はその発光ダイ
オードの斜視図で、平板部ＢはGaAs基板B1と、AlGaAs発
光層B2と、AlGaAsバリヤ層B3とを形成したシングルヘテ
ロ接合からなり、バリヤ層B3の表面の中央には円板状電
極E1が埋設され、基板B1の底面の全面には電極E2が設け
られている。One embodiment of the semiconductor light emitting device of the present invention will be described by taking a well-known AlGaAs / GaAs system surface emitting diode having an emission wavelength of 0.66 μm as an example. FIG. 1 (e) is a perspective view of the light emitting diode. The flat plate portion B is composed of a single heterojunction in which a GaAs substrate B1, an AlGaAs light emitting layer B2, and an AlGaAs barrier layer B3 are formed. A disk-shaped electrode E1 is embedded in the center, and an electrode E2 is provided on the entire bottom surface of the substrate B1.

次に、上記のような構造、特に埋設された電極を有す
る構造の発光ダイオードの製造方法の一例を概説する。Next, an example of a method of manufacturing a light emitting diode having the above structure, particularly a structure having a buried electrode will be outlined.

まず、GaAs基板B1上に、発光層となるAl0.35Ga0.65As
結晶層B2と電子の逆流を防止するAl0.5Ga0.5Asバリヤ層
B3とをエピタキシャル成長させたシングルヘテロウェハ
を製作する。このシングルヘテロウェハにつき、ホトリ
ソグラフィを用いてレジストＲの中央部が円形状に貫通
したレジストＲをバリヤ層B3上に形成する（第１図ａ参
照）。レジストＲのパターニング後、例えばCl2、Cl2＋
Ar、Cl2＋H2、CCl4、CCl4＋Ar、CCl4＋H2等のハロゲン
系ガスを用いて反応性イオンエッチング（RIE）、ある
いは反応性イオンビームエッチング（RIBE）によりレジ
ストＲの貫通部分の円形状をそのままバリヤ層B3の一定
の深さまで形成して、円形状溝Ｍを形成する（第１図ｂ
参照）。次に、バリヤ層B3に形成した溝Ｍ内にｐ側電極
E1を、また基板B1の下面の全面にｎ側電極E2を真空蒸着
等の手段によって設ける（第１図ｃ参照）。この時、必
要ならば電解メッキ法等も用いて電極を厚くする。その
後、不必要な電極材料及びレジストＲをリフトオフ法に
より除去することにより、電極E1が素子の表面に埋め込
まれた発光ダイオードが製造される（第１図ｄ及びｅ参
照）。この後、チップ化して個々の発光ダイオードにす
る。なお、本発明においては、溝内に設けられる電極の
接続はワイヤボンディングによって行うため、当該電極
面は、ワイヤとの接着が容易かつ確実になされるよう、
第１図に示すような平面状に形成されることが好まし
い。First, on the GaAs substrate B1, Al 0.35 Ga 0.65 As which will be the light emitting layer is formed.
Al 0.5 Ga 0.5 As barrier layer that prevents backflow of electrons from the crystalline layer B2
A single hetero wafer is produced by epitaxially growing B3 and. With respect to this single hetero wafer, a resist R in which the central portion of the resist R is circularly penetrated is formed on the barrier layer B3 by using photolithography (see FIG. 1a). After patterning the resist R, for example, Cl 2 , Cl 2 +
Reactive ion etching (RIE) or reactive ion beam etching (RIBE) is used to etch the penetrating portion of the resist R using a halogen-based gas such as Ar, Cl 2 + H 2 , CCl 4 , CCl 4 + Ar, and CCl 4 + H 2 . The circular shape is formed as it is to a certain depth of the barrier layer B3 to form the circular groove M (FIG. 1b).
reference). Next, in the groove M formed in the barrier layer B3, the p-side electrode
E1 and the n-side electrode E2 are provided on the entire lower surface of the substrate B1 by means such as vacuum deposition (see FIG. 1c). At this time, if necessary, the electrode is thickened by using an electrolytic plating method or the like. Thereafter, the unnecessary electrode material and the resist R are removed by the lift-off method to manufacture a light emitting diode in which the electrode E1 is embedded in the surface of the device (see FIGS. 1d and 1e). After that, it is made into chips to form individual light emitting diodes. In the present invention, since the electrodes provided in the groove are connected by wire bonding, the electrode surface should be easily and surely bonded to the wire.
It is preferably formed in a flat shape as shown in FIG.

このようにして得られた発光ダイオードの電極E1は、
バリヤ層B3の溝Ｍ内に保持された状態にあるので、ワイ
ヤボンディング時の剥がれを抑制することができる。ま
た溝Ｍ内に電極E1を設けたことにより、電極E1と素子の
接触面積が素子の容量増加による変調特性の悪化を生じ
ることなく増加してオーミック抵抗が減少するため、結
果として素子の発光輝度が増加すると共に、素子自体の
放熱特性が向上し、素子の寿命及び高出力化を計ること
ができる。The electrode E1 of the light emitting diode thus obtained is
Since it is held in the groove M of the barrier layer B3, peeling during wire bonding can be suppressed. Further, by providing the electrode E1 in the groove M, the contact area between the electrode E1 and the element is increased without causing the deterioration of the modulation characteristic due to the increase of the capacitance of the element, and the ohmic resistance is reduced. And the heat dissipation characteristics of the element itself are improved, and the life and output of the element can be increased.

本発明の埋設電極を有する半導体発光素子の別の利点
としては、電極を素子の表面に埋め込むものであり、該
電極の上面部が素子の電極形成面と同高となっているた
め、電極と素子の接触面積の増加に起因する素子の容量
増加によって変調特性を悪化させることなく電極の容積
を大きくできると共に、従来においてリフトオフを行う
ためにマスク（SiO2,SiN4）を非常に厚く堆積させてい
たが、薄くてもリフトオフを行うことができる。また、
このような構成によれば、例えば電極が素子の電極形成
面から突出するように形成される場合に比して、電極が
素子に安定して固定され得るものとなり、就中、ワイヤ
との接続後に該ワイヤによって受ける左右方向の応力に
対して特に電極の安定性が高くなる。さらにまた、電極
を素子の電極形成面から突出させることが不要であるた
め、電極を厚く形成する必要がなく、このため例えば真
空蒸着等の方法のみによっても電極形成を行い得、製造
工程の簡略化ならびに製造コストの低減が可能となる。
また、本発明の半導体発光素子の製造に当たって、溝を
形成する際に反応性イオンエッチングを用いれば、自然
酸化膜除去後の素子の表面が非常に清浄となり、この清
浄な素子の表面に電極を形成するので、素子と電極との
接触によるオーミック抵抗を低減できる。Another advantage of the semiconductor light emitting device having the embedded electrode of the present invention is that the electrode is embedded in the surface of the device, and since the upper surface portion of the electrode is flush with the electrode formation surface of the device, The volume of the electrode can be increased without deteriorating the modulation characteristics due to the increase of the element capacitance due to the increase of the contact area of the element, and the mask (SiO 2 , SiN 4 ) is deposited very thick to perform lift-off in the past. However, lift-off can be performed even if it is thin. Also,
According to such a configuration, the electrode can be more stably fixed to the element as compared with the case where the electrode is formed so as to project from the electrode formation surface of the element. The stability of the electrode becomes particularly high with respect to the lateral stress that is later applied by the wire. Furthermore, since it is not necessary to project the electrodes from the electrode formation surface of the element, it is not necessary to form the electrodes thickly. Therefore, for example, the electrodes can be formed only by a method such as vacuum deposition, which simplifies the manufacturing process. It is possible to reduce cost and manufacturing cost.
Further, in the production of the semiconductor light emitting device of the present invention, if reactive ion etching is used when forming the groove, the surface of the device after the natural oxide film is removed becomes very clean, and the electrode is attached to the surface of this clean device. Since it is formed, ohmic resistance due to contact between the element and the electrode can be reduced.

第２図（ａ）、（ｂ）、（ｃ）は、バリヤ層B3に形成
する溝Ｍの径方向の断面形状の変更例を示すものであ
る。（ａ）では溝Ｍの断面形状が、その開口部と底部と
の間に、該開口部より幅広である部分を有するため、ま
た（ｂ）の溝Ｍも同様の形状を呈しているため、（ａ）
及び（ｂ）に示した溝Ｍ内に電極E1を形成すれば、電極
E1はさらに剥がれ難くなる。（ｃ）に示したものは、電
極E1の剥がれを抑制することに加えて、電極E1と素子と
の接触面積を積極的に増大させようとするものであり、
これは反応性イオンエッチング時にマスクとの選択比を
利用することにより形成することができる。（ｄ）はさ
らに別の変更例で、溝Ｍの断面形状は（ａ）に示したも
のと同様であるが、平面形状は第１図（ｅ）の如く円形
ではなく、素子の表面を横断するものである。FIGS. 2 (a), (b) and (c) show examples of changing the radial cross-sectional shape of the groove M formed in the barrier layer B3. In (a), since the cross-sectional shape of the groove M has a portion wider than the opening between the opening and the bottom, the groove M in (b) also has the same shape. (A)
If the electrode E1 is formed in the groove M shown in FIGS.
E1 becomes more difficult to peel off. The one shown in (c) is intended to positively increase the contact area between the electrode E1 and the element in addition to suppressing peeling of the electrode E1.
This can be formed by utilizing the selection ratio with the mask at the time of reactive ion etching. (D) is a further modification, in which the cross-sectional shape of the groove M is similar to that shown in (a), but the planar shape is not circular as shown in FIG. To do.

この他、反応性イオンエッチングは、条件を最適化す
ることにより、GaAs等化合物半導体の結晶方位依存を有
しないエッチングが可能で、さらに高輝度である電極パ
ターン（たとえば素子の平面からみてＸ字形や星形等）
をエッチングすることもできるので、本発明の半導体発
光素子の製造に際し、特に電極形成時に反応性イオンエ
ッチングを用いることが好ましい。In addition, reactive ion etching enables etching that does not depend on the crystal orientation of a compound semiconductor such as GaAs by optimizing the conditions, and has an electrode pattern of higher brightness (for example, an X-shaped shape when viewed from the plane of the element, (Star shape, etc.)
Since it can also be etched, it is preferable to use reactive ion etching in the production of the semiconductor light emitting device of the present invention, particularly when forming electrodes.

なお、このような埋設電極において、素子と電極を構
成する金属との熱膨張率の相違により、素子に応力が加
わる場合には、電極形成後にアニーリング（たとえば、
約200℃）することによって応力の問題を回避すること
ができる。In such a buried electrode, when stress is applied to the element due to the difference in coefficient of thermal expansion between the element and the metal forming the electrode, annealing (for example,
By doing so, the problem of stress can be avoided.

また、上述の実施例は、シングルヘテロ構造の面発光
ダイオードであるが、本発明の半導体発光素子は、これ
に限定されることはなく、他の材料（たとえばGaAsP
等）からなる発光ダイオードであってもよく、また面発
光素子に限らず、ストライプ形の発光ダイオードやレー
ザダイオードであっても構わない。Further, although the above-described embodiment is a surface emitting diode having a single hetero structure, the semiconductor light emitting device of the present invention is not limited to this, and other materials (for example, GaAsP) may be used.
And the like), and not only the surface light emitting element but also a stripe type light emitting diode or a laser diode.

〔発明の効果〕〔The invention's effect〕

以上説明したように、本発明の半導体発光素子は、素
子の電極形成面に形成された溝に、ワイヤボンディング
により接続用の電極を設けるようにし、さらに、当該溝
の断面形状を、その開口部と底部との間に、該開口部と
同幅であるか、もしくは該開口部より幅広である部分を
有するものとし、さらに、当該電極の上面部が素子の電
極形成面と同高となるようにしたことにより、電極のワ
イヤボンディング時に電極が剥がれ難くなり、また素子
と電極との接触面積が容量増加による変調特性の悪化を
生じることなく増大するので、オーミック抵抗を低減す
ることができ、発光輝度も増大し、しかも素子自体の寿
命を延ばすことができ、非常に有用なものである。As described above, in the semiconductor light emitting device of the present invention, the electrode for connection is provided by wire bonding in the groove formed in the electrode formation surface of the device, and the cross-sectional shape of the groove has the opening And a bottom portion having the same width as the opening portion or wider than the opening portion, and further, the upper surface portion of the electrode is flush with the electrode formation surface of the element. This makes it difficult for the electrode to peel off during wire bonding of the electrode, and since the contact area between the element and the electrode increases without degrading the modulation characteristics due to the increased capacitance, the ohmic resistance can be reduced and the light emission can be improved. The brightness is increased and the life of the device itself can be extended, which is very useful.

【図面の簡単な説明】[Brief description of drawings]

第１図（ａ）〜（ｅ）は本発明の半導体発光素子及び電
極製造方法の一実施例を示す概略工程図、第２図（ａ）
〜（ｄ）は溝の形状の変更例を示す図、第３図（ａ）、
（ｂ）は従来の発光ダイオード及びその使用例を示す図
で、（ａ）は発光ダイオードの断面図、（ｂ）はその実
際の使用時の斜視図である。 B:平板部 B1:基板 B2:発光層 B3:バリヤ層 E1、E2:電極 M:溝 R:レジスト1 (a) to 1 (e) are schematic process diagrams showing one embodiment of a semiconductor light emitting device and an electrode manufacturing method of the present invention, and FIG. 2 (a).
~ (D) is a diagram showing an example of changing the shape of the groove, Fig. 3 (a),
(B) is a figure which shows the conventional light emitting diode and its usage example, (a) is sectional drawing of a light emitting diode, (b) is a perspective view at the time of actual use. B: Flat plate part B1: Substrate B2: Light emitting layer B3: Barrier layer E1, E2: Electrode M: Groove R: Resist

Claims (1)

【特許請求の範囲】[Claims] 【請求項１】素子の電極形成面に形成された溝に、ワイ
ヤボンディングによる接続用の電極を設けてなり、当該
溝の断面形状が、その開口部と底部との間に、該開口部
と同幅であるか、もしくは該開口部より幅広である部分
を有し、該電極の上面部が素子の電極形成面と同高とな
っていることを特徴とする半導体発光素子。1. A groove formed on an electrode forming surface of an element is provided with an electrode for connection by wire bonding, and a cross-sectional shape of the groove is such that an opening portion is formed between an opening portion and a bottom portion. A semiconductor light-emitting device having a portion having the same width or wider than the opening, and the upper surface of the electrode is flush with the electrode formation surface of the device.
JP9580386A 1986-04-24 1986-04-24 Semiconductor light emitting device Expired - Lifetime JPH084152B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9580386A JPH084152B2 (en) 1986-04-24 1986-04-24 Semiconductor light emitting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9580386A JPH084152B2 (en) 1986-04-24 1986-04-24 Semiconductor light emitting device

Publications (2)

Publication Number Publication Date
JPS62252180A JPS62252180A (en) 1987-11-02
JPH084152B2 true JPH084152B2 (en) 1996-01-17

Family

ID=14147589

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9580386A Expired - Lifetime JPH084152B2 (en) 1986-04-24 1986-04-24 Semiconductor light emitting device

Country Status (1)

Country Link
JP (1) JPH084152B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5019666B2 (en) * 2000-06-22 2012-09-05 ローム株式会社 Manufacturing method of semiconductor device
JP2008172040A (en) * 2007-01-12 2008-07-24 Sony Corp Semiconductor light emitting device, method for manufacturing semiconductor light emitting device, backlight, display, and electronic device

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5749392Y2 (en) * 1976-12-02 1982-10-29
JPS57103374A (en) * 1980-12-19 1982-06-26 Oki Electric Ind Co Ltd High-brightness light emitting diode
JPS59228718A (en) * 1983-06-11 1984-12-22 Toshiba Corp Semiconductor device

Also Published As

Publication number Publication date
JPS62252180A (en) 1987-11-02

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