JPH084225B2 - Demodulation circuit - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a demodulation circuit for demodulating a PE-modulated signal.

Conventional Technology As a conventional PE demodulation clock generation circuit, for example, the fourth
Some are shown in the figure. Reference numeral 1 is a differentiating circuit for generating a pulse having a minute width at the rising edge or the falling edge of the input signal a. Reference numeral 2 is a mono-multivibrator that is activated when the differential pulse of the differential circuit output b is input when the output c is at the low level and generates the output c that maintains the high level for the constant width T. If the bit cell time of the input signal (time corresponding to 1 bit of demodulated data) is T _O , T is
By setting it to be larger than 1 / 2T _{O and} smaller than T _O , the output c will generate one pulse for one bit of demodulated data. Usually, considering that there is jitter in the input signal, T is set to the center value 3 / 4T _O of 1 / 2T _O and T _O. Three
Is a delay circuit, and outputs c to fully satisfy the setup time of the circuit when the input signal is demodulated by the demodulation clock.
Is used as the demodulation clock.

The conventional PE demodulation clock generation circuit configured as described above receives an input signal a as shown in FIG.
The demodulation clock c having the period T _O is output via the differential circuit output b. In this system, a signal modulated by PE can be demodulated without using a PLL (phase locked loop). Therefore, there is an advantage that the demodulation clock can be created with almost no need for the phase synchronization signal section for pulling in the phase synchronization of the PLL circuit.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above-mentioned configuration, when a dropout occurs in the input signal a as shown in FIG. 6, a loss occurs in the differential circuit output b and a loss in the demodulation clock c occurs. However, the demodulated data causes a bit shift. The bit shift has a problem that even if it is 1 bit, the error may continue after the bit shift and become a multiple error, which may exceed the detection capability of the error detection code. .

In view of the above point, the present invention prevents the occurrence of bit shift of demodulated data even when a loss occurs in the PE-modulated input signal, and can utilize the capability of the error detection code or the error correction code. An object is to provide a demodulation circuit for a modulated signal.

Means for Solving the Problems The present invention provides a pulse generated from a rising edge or a falling edge of a PE-modulated input signal to generate a demodulation clock of a pulse longer than 1/2 bit cell time and shorter than 1 bit cell time. Creating means, detecting means for detecting a match between the data demodulated using the demodulation clock created by the pulse creating means and a predetermined bit string indicating the beginning of the demodulated data, and the demodulation before the loss of the input signal An additional pulse creating means for creating an additional pulse synchronized with a clock is provided, and after the predetermined leading bit string is detected by the detecting means, the additional pulse is demodulated for a missing input signal within N bits. It continues to demodulate by adding it as a clock, and when the input signal exceeding N bits is lost, the addition of the additional pulse is stopped to recover. Which is a demodulation circuit, characterized in that the stop.

Operation According to the present invention, when the PE-modulated input signal has a loss by the above configuration, if the number of bits is within a predetermined number of bits, the demodulated clock is provided with the same number of clock pulses as the number of missing bits. Thus, the bit shift of the data sampled by the demodulation clock is prevented, and the influence of the loss of the input signal makes full use of the capability of the error correction code or the error detection code. Further, when the following loss occurs, the addition of the clock pulse to the demodulation clock is stopped.

(1) When there is a missing input signal that exceeds the capability of the error correction code or the error detection code (2) Since the head bit string indicating the start of the demodulated data was erroneously detected, the demodulated data ends and the no-data portion or the next When the Gap Length until Data Is Sent is Reached FIG. 1 is a block diagram of a PE demodulation circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 10 is a differentiating circuit which generates a pulse f having a minute width at the falling edge and the rising edge of the input signal e. The pulse width of the pulse f is set to be equal to or greater than the synchronization of the system clock g in order to synchronize with the system clock g by the flip-flop 13 described later. The synchronization of the system clock g is set sufficiently smaller than the shortest inversion interval of the input signal. 11 is an AND gate, which is the output f of the differentiating circuit 10 and the inverting gate
Outputs the logical product of 12 outputs. A flip-flop 13 outputs a signal h obtained by synchronizing the output of the AND gate 11 with the system clock g. Output h is shift register
It is input to the reset terminals of 14 and the set terminals of the shift register 15 and the shift register 16. 14, 15 are L-stage shift registers, and 16 are M-stage shift registers. In the shift register 14, Q ₁ to Q _L are reset to “0” by the output h of the flip-flop 13, and the shift register 15
The output h sets Q _{L + 1} to Q _2L to “1”, and the shift register 16 outputs Q _{2L + 1} to Q _{2L + M} to “1”.
Is set to Q _L output of the shift register 14 to the input terminal of the shift register 15, Q _2L outputs of the shift register 15 is inputted to the input terminal and the AND gate 17 of the shift register 16. The outputs of the shift registers 14, 15, 16 are such that, when no pulse is generated at the output h, the output Q ₁ is at Q ₂ , the output Q ₂ is at Q ₃ , each time a pulse of the system clock g is input, ... …
… The output Q _2L-1 shifts to Q _2L and so on, and the data shifts one stage to the right. Although the data at the input terminal of the shift register 14 shifts to the output Q _L , T _O / 2 (T _O is the bit cell time of the input signal), and the data at the input terminal of the shift register 15 shifts to the output Q _2L. T _O / 2, shift register
The data on the 16 input terminals is T to shift to the output Q _{2L + M.}
The number of stages "L" and "M" of the shift register are set so that the number becomes _O / 4. Reference numeral 18 denotes a delay circuit which delays the output Q _{2L + M} of the shift register 16 to obtain the demodulation clock i in order to sufficiently satisfy the setup time of the circuit when the input signal is demodulated by the demodulation clock. A shift register 19 demodulates the input signal e with the demodulation clock i. Reference numeral 20 denotes a comparator, which compares the output of the shift register 19 with the head bit string for data demodulation, and when they match, sets the output of the flip-flop 21 to a high level via the set terminal.
A counter 22 outputs the number Q of missing bits by counting the output Q _{2L + M} of the shift register 16 when the input signal is missing. 23 is a comparator, counter 22
When the former becomes larger than the latter, the output of the flip-flop 21 is set to the low level via the OR gate 24. The flip-flop 21 is reset through the OR gate 24 even when the demodulation is completed.

The operation of the embodiment of the present invention will be described with reference to the time charts of FIGS. 2 and 3. The following description will be made assuming that the input signal has no jitter. FIG. 2 shows the operation when there is no loss in the input signal, and FIG. 3 shows the operation when there is a loss in the input signal. In both figures, it is assumed that the head bit string is detected and the output of the flip-flop 21 is at the high level. When there is no omission in the input signal, as shown in FIG. 2, the AND gate 11, the inverting gate 12, the flip-flop 13, the shift registers 14, 15 and 16 are all shifted with respect to the output f of the differentiating circuit 10. The output Q _{2L + M} of the register 16 becomes a mono-multi output with a time constant of 3 / 4T _O. On the other hand, when there is a missing input signal, as shown in Fig. 3, when there is no missing signal, when the shift registers 14 and 15 are to be reset or set originally, it is delayed by T _O / 4. Since the shift register Q _{2L + M} becomes high level and the shift registers 14 and 15 constitute the oscillator thereafter, and the output Q _2L becomes the oscillation output of the period T _O , the demodulation clock i is generated even if the input signal is lost. After that, when the loss of the input signal ends, the generation of the demodulation clock is started for the input signal. If the number of missing bits exceeds a predetermined value N, the comparator 23 resets the flip-flop 21 via the OR gate 24, the output of the flip-flop 21 becomes low level, and the AND gate 17 A low level is input to the input terminal of the shift register 14 via the shift register 14, the oscillation by the shift registers 14 and 15 is stopped, the addition of pulses to the demodulation clock is stopped, and the subsequent demodulation is disabled, and the detection of the first bit string is performed. Return to the state.

As described above, according to the present invention, it is possible to prevent the shift of the demodulated data by adding a pulse to the demodulation clock when the signal is missing within N bits. Further, with respect to signal loss exceeding N bits, the following three points are advantageous by stopping the addition of pulses to the demodulation clock and moving to the detection operation of the head bit string.

(1) By setting N to be equal to or less than the maximum number of correctable error bits of the error correction code of data, the subsequent data demodulation is stopped for a signal loss of a scale that cannot be error corrected, and erroneous correction is prevented.

(2) By setting N to be equal to or less than the maximum number of error bits that can be detected by the error detection code of the data, it is possible to prevent the error detection code from being detected as being correct although it is incorrect.

(3) By setting N to be equal to or less than the number of bits corresponding to the gap length between data blocks, a correct data head bit string is missed, and even if the head bit string is erroneously detected in the middle of data, the head bit string The detection operation state can be restored, and the demodulation operation is prevented from continuously overrun to the next data block.

EFFECTS OF THE INVENTION As described above, according to the present invention, when PE demodulation is performed, a pulse is added to the demodulation clock if the loss of the input signal is less than a certain level after the detection of the leading bit string of the data. Thus, bit shift of demodulated data can be prevented. By stopping adding the pulse to the demodulation clock when the loss of the input signal exceeds a certain level, (1) erroneous correction is prevented when a signal loss exceeding the capability of the error correction code occurs.

(2) Prevent erroneous detection when a signal loss that exceeds the capability of the error detection code occurs.

(3) When the data head bit string is erroneously detected in the data, the demodulation operation is prevented from being continuously performed up to the next data block.

So, its practical effect is great.

[Brief description of drawings]

FIG. 1 is a block diagram of a PE demodulation circuit of an embodiment of the present invention, FIGS. 2 and 3 are timing charts of the same embodiment, and FIG. 4 is a block diagram of a conventional PE demodulation clock generation circuit. 6 and 6 are timing charts of a conventional example. 10: Differentiation circuit, 13,21 ... Flip-flop, 14,15,1
6,19 …… Shift register, 18 …… Delay circuit, 20,23 ……
Comparator, 22 ... Counter.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Yuzuru Kuroki 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yuji Takagi, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.

Claims (4)

[Claims] 1. A pulse creating means for starting a rising edge or a falling edge of a PE-modulated input signal to create a demodulation clock of a pulse longer than 1/2 bit cell time and shorter than 1 bit cell time, and the pulse creation. Detecting means for detecting a match between the data demodulated using the demodulation clock created by the means and a predetermined bit string indicating the beginning of the demodulated data; and an additional pulse synchronized with the demodulation clock before the loss of the input signal. It has an additional pulse creating means for creating, and after the predetermined head bit string is detected by the detecting means, for the missing of the input signal within N bits, the additional pulse is added as a demodulation clock for demodulation. Continuing, when the input signal exceeding N bits is lost, the addition of the additional pulse is stopped to stop the demodulation. That demodulation circuit. 2. An upper limit N of the number of input signal missing bits for adding a pulse to a demodulation clock after detecting a predetermined head bit string.
Is set to a value equal to or less than the maximum number of error bits that can be error-corrected, The demodulation circuit according to claim 1, wherein 3. An upper limit N of the number of missing bits of an input signal for adding a pulse to a demodulation clock after detecting a predetermined head bit string.
Is set to be equal to or less than the maximum number of error bits capable of error detection, The demodulation circuit according to claim 1, wherein 4. An upper limit N of the number of input signal missing bits for adding a pulse to a demodulation clock after detecting a predetermined head bit string.
Is set to a value equal to or less than the number of bits corresponding to the gap length between the data blocks, and the demodulation circuit according to claim 1.