JPH084232B2 - Difference information data conversion method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention is directed to n bits (n
Is a positive integer) m pieces of difference information data (m is a positive integer)
The present invention relates to a difference information data conversion method for collectively converting new information data of m × n bits.

[Conventional technology]

Conventionally, when converting an analog information signal into digital information data for transmission or recording, the well-known DPCM (Differen
tial Pulse Code Modulation). In this system, a difference between a signal inputted first and a signal inputted next is taken, and the difference is quantized and coded into digital information data. According to this method, only the difference information from the previous input signal is quantized and encoded,
Information can be compressed.

In addition, a method is also considered in which some digital difference information data obtained by these DPCM methods are collected and converted into other information data.

[Problems to be Solved by the Invention] However, when converting some digital difference information data obtained by using the DPCM method into other information data, for example, the difference information data is n bits (n bits).
Is a positive integer) and is converted into m × n bits of new information data for every m (m is a positive integer), there are 2 ⁿ types of generation patterns of the n bits of difference information data. , If these are grouped into m pieces and made into m × n bits,
Since it is considered that 2 ^{m × n} kinds of patterns will occur in the m × n bit data before conversion, it is necessary to prepare 2 ^{m × n} kinds of information data of m × n bits after conversion. When the subsequent m × n bit information data is stored in a memory or the like and the input m × n bit data is converted as a read address, a method such as a memory backup is used, the memory is as described above. 2 ^{m × n} kinds of m × n
The bit information data had to be stored, and a large capacity memory was required.

Also, the data input during the above conversion is "1", "0"
If the signal contains many low-frequency components with a small number of inversions, it is converted to data that suppresses this. However, since the input data and output data have the same number of bits, the data patterns of the input and output are of the same type. Had been assigned.

The present invention has been made in view of such circumstances, and an object thereof is to provide a difference information data conversion method capable of converting difference information data into information data having a small number of low frequency components by a simple method.

[Means for solving problems]

The difference information data conversion method of the present invention collects n-bit (n is a positive integer) difference information data indicating the difference value of a plurality of data for every m pieces (m is a positive integer) and corresponds to the combination. When the data is converted into new m × n-bit information data that has been allocated in the above manner, the m × n-bit information data is not allocated to a combination that does not occur among the m combinations of difference information data, and the combination is generated. The combinations are assigned in order from the information data having the lower low frequency components in the m × n bit information data according to the occurrence frequency.

[Action]

According to the above-described method, since m × n bit information data is not assigned to a combination that does not occur among the m pieces of difference information data, the low frequency component is small in the m × n bit information data. The information data can be sequentially assigned according to the frequency of occurrence of the combination of the m pieces of difference information data, and the m pieces of difference information data corresponding to the combination have m × n bits of low frequency components. You will be able to convert it to data.

[Examples] Hereinafter, the present invention will be described based on Examples.

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention.

The analog information signal input in FIG. 1 is converted into an 8-bit digital signal by the A / D converter 1 which operates by the clock pulse (FIG. 2 (a)) generated from the clock generator 6 and the differential encoding circuit. Entered in 2. The differential encoding circuit 2 is a well-known circuit and nonlinearly quantizes the differential data between the input 8-bit information data and the representative value data, and outputs it as 4-bit differential information data, for example. Here, the 8-bit information data is compressed and output as 4-bit difference information data. The representative value data is generated by predicting the previous value or the like by using the information data input immediately before the input information data as the representative value data.

The 4-bit difference information data output as described above is input to the latch circuits 4 and 5 via the 1-data delay 3. The 1-data delay 3 is for delaying the 4-bit difference information data by 1-data input period.

The latch circuits 4 and 5 perform the latch operation by the latch pulse (Fig. 2 (b)) obtained by halving the frequency of the clock pulse (Fig. 2 (a)) of the clock pulse generator 6 by the 1/2 divider 7. As shown in FIG. 2, since the latch pulse (b) is generated once every two clock pulses (a), the 4-bit difference information data output from the difference encoding circuit 2 is 2 times. It is output to the memory table 8 as a total of 8 bits of data.

Here, the conversion data stored in the memory table 8 will be described. The memory table 8 holds the conversion data corresponding to the pattern of the 8-bit data generated as described above, and the conversion data is read and output by this address data using the 8-bit data as the address data. Will be done.

However, since the address data is a combination of 4-bit difference information data as described above, there are combinations that do not occur.

FIG. 3 is a diagram showing a specific example of the differential encoding circuit of FIG.

First, in FIG. 3A, the input 8-bit image data a has a level of “0 to +255” and is input to the subtractor 9.

The 8-bit prediction data b output from the prediction circuit 10 is input to the subtractor 9, and this prediction data b is "0".
It has a level of "-255 to +255" including. Then, the prediction data b is subtracted from the information data a in the subtracter 9 to obtain 9-bit subtraction data (ε _i-1 ) ₉ as a compression circuit 11
Is output to The possible values of the subtraction data (ε _i-1 ) ₉ are "-255 to +255".

Now, assuming that the value of the information data a is “0” and the value b of the prediction data is “−255”, the value of the subtraction data (ε _i-1 ) ₉ is a−b =
(0)-(-255) = (+ 255). The subtraction data (ε _i-1 ) ₉ is compressed by the compression circuit 11 into 4-bit difference data (ε _i-1 ) ₄ and output. Also, the difference data (ε
_i-1 ) ₄ is the original subtraction data (ε _i-1 ) _{9 in the} decompression circuit 12.
The returned adder circuit 13 adds the prediction data b output from the prediction circuit 10.

In other words, when the prediction data b + the subtraction data (ε _i-1 ) ₉ = (− 255) + (+ 255) = (0) = information data a from the addition circuit 13 becomes the prediction data 10 and, for example, the previous value prediction is performed. The information data a is output as prediction data.

Next, as shown in FIG. 3 (b), 8-bit information data c
Is input, the subtractor 9 next inputs the information data c, and the subtractor 9 then subtracts the information data c and the prediction data a.

However, since the information data c also has a level of "0 to +255", the value of the subtraction data (ε _i ) ₉ becomes "0 to +255", which is a subtraction data that takes a value larger than "+255". (Ε _i ) ₉ does not occur.

Figure 4 is subtraction data (ε _{i-1) 9,} representing the combination of (epsilon _{i) 9} levels is taken up in each vertical axis and the horizontal axis subtraction data (ε _{i-1) 9} and the (epsilon _{i) 9} It is a figure. However, in this case, the levels of the subtraction data (ε _i-1 ) ₉ and (ε _i ) ₉ are both “0 to +255”, and other subtraction data (ε _i ).
_{Both i−1} ) ₉ and (ε _i ) may be “−255 to 0”, but they are omitted here.

The combinations shown above the dotted line in FIG. 4 do not occur as described above. Further, in FIG. 4, it is divided into a grid by solid lines, but each divided portion is obtained by subtracting 8-bit subtraction data (ε _i-1 ) ₉ , (ε _i ) ₉ by the compression circuit 11 in FIG. 4-bit difference data (ε _i-1 ) ₄ ,
The differential data (ε _i ) ₄ is compressed into subtraction data (ε _i-1 ) ₉ and (ε _i ) ₉ level “0 to +255” is nonlinearly divided into 8
_{i-1) 4, (ε} i) the difference data when expressed in ₄ levels _{"0~ + 7" (ε i} -1) 4, shows a combination of (epsilon _{i) 4.} That is, the combination of the difference data (ε _i-1 ) ₄ , (ε _i ) ₄ which is above the dotted line and does not occur is the shaded portion in FIG. 4 and is {(ε _i-1 ) ₄ , (ε _i ) ₄ } is (7.7),
It is a combination of the levels (7.6) and (6.7). In addition, such a combination of difference data that does not occur is such that when the subtraction data (ε _i-1 ) ₉ and (ε _i ) ₉ both have a level of “−255 to 0”, {(ε _i-1 ) ₄ , (ε _i ) ₄ } is (-7, -7), (-
The combination is 7, -6) and (-6, -7).

Therefore, in the memory table 8, since the combination of difference data as described above is not input as 8-bit address data, it is not necessary to allocate conversion data corresponding to these address data on the table, and conversion data that cannot be allocated. The number of memory of can be reduced.

In addition, since the number of converted data patterns is larger than that of the input address data, the converted data that cannot be assigned has a pattern including many low frequency components,
If it is not stored in the memory table, it can be converted into conversion data having a high low-frequency suppression effect.

Further, the unallocated converted data may be used for other purposes such as DSV control and error detection.

〔The invention's effect〕

As described above, according to the present invention, it is possible to provide a difference information data conversion method capable of converting difference information data into information data having a small number of low frequency components by a simple method.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of an embodiment of the present invention. FIG. 2 is a time chart of the latch operation of FIG. FIG. 3 is a diagram showing a specific example of the differential encoding circuit of FIG. FIG. 4 is a diagram showing a combination pattern of the subtracted data (ε _i-1 ) ₉ and (ε _i ) ₉ shown in FIG. 1 ... Analog-digital converter, 2 ... Differential coding circuit, 3 ... 1 data delay, 4,5 ... Latch circuit, 6
...... Clock generator, 7 …… 1/2 divider, 8 …… Memory table.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomohiko Sasaya 3-30-2 Shimomaruko, Ota-ku, Tokyo Canon Inc. (56) Reference JP-A-56-161587 (JP, A) JP-A-59-184941 (JP, A) JP 59-184942 (JP, A) JP 59-225444 (JP, A)

Claims (1)

[Claims] 1. An n-bit (n is a positive integer) difference information data indicating a difference value of a plurality of data is collected every m pieces (m is a positive integer) and assigned corresponding to the combination. When converting to new m × n bits of information data,
The m × n bit information data is not assigned to a combination that does not occur in the combination of m pieces of difference information data,
Regarding the combinations that occur, the above-mentioned m
A difference information data conversion method characterized by allocating in order from the information data of low frequency components in n bits of information data.