JPH0844622A - Information processing device - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide an information processing device using a flash memory that can reduce the power consumption during operation by utilizing the non-volatility of the flash memory. [Structure] A central processing unit, a main storage unit, a display unit, an external interface, a power supply control unit, and a bus connecting them, and a part of the main storage unit is composed of a plurality of flash memories. In the information processing apparatus, the power control unit turns on / off the power of the plurality of flash memories.
It is characterized by controlling OFF.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing device such as a computer and a personal digital assistant, and more particularly to an information processing device using a flash memory as a part of a main memory.

[0002]

2. Description of the Related Art Storage elements used in information processing apparatuses are roughly classified into read only memories (ROM) and random access memories (RAM).

The read-only memory (ROM) includes a mask ROM, a programmable ROM (PROM), an erasable PROM (EPROM), an electric erasable PROM (EEPROM), and a flash memory.

Random access memory (RAM)
Includes a dynamic RAM (DRAM) and a static RAM (SRAM).

The read-only memory (ROM) is characterized by being non-volatile and capable of holding information without being powered on, but on the other hand, it is a random access memory (RA).
In M), the stored information is lost unless power is supplied.

As a personal information device, a notebook computer or a portable information terminal device is used.

[0007] A common feature of these two devices is that they are used while moving, but in that case, a power source cannot be obtained from a general commercial power source, and battery operation is the basis.

In this case, it is necessary to increase the power supply capacity or reduce the power consumption in consideration of long-term use.

In the current notebook computer or portable information terminal, the type of memory used for the main memory is determined in consideration of reduction of power consumption.

That is, an inexpensive mask ROM with low power consumption is used in an area that does not need to be rewritten, for example, an operating system area, and a static RAM (S) is used in an area that can be rewritten.
RAM) is used.

Static RAM (SRAM) is a dynamic RAM used in general computers.
Compared to (DRAM), it consumes very little power and is suitable for battery drive, but on the other hand, it has the drawbacks of large chip area and high cost.

Therefore, a flash memory has recently been attracting attention.

Since the flash memory is non-volatile, it does not require a power source for holding data, and the chip area can be reduced due to its element structure, and it is an inexpensive and large-capacity memory.

Application of a flash memory to a main storage section of an information processing apparatus by utilizing its characteristics of large capacity, rewritability, and low power consumption is described in, for example, Japanese Patent Laid-Open No. 05-334168. ing.

[0015]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
-334168), the flash memory is applied to the main memory unit, and the non-volatility of the flash memory is used to reduce the power consumption only when the power supply of the information processing apparatus including the flash memory is turned off. I am trying to do it.

However, the above-mentioned publication (Japanese Patent Laid-Open No. 05-3
No. 34168) does not consider reducing the power consumption by taking advantage of the non-volatility of the flash memory during the operation of the information processing apparatus including the flash memory.

An object of the present invention is to provide, in an information processing apparatus using a flash memory, a technique capable of reducing power consumption during operation of the information processing apparatus.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0019]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

(1) A central processing unit, a main storage unit, a display unit, an external interface, a power supply control unit, and a bus connecting them, and a part of the main storage unit has a plurality of flash memories. An information processing device comprising
The power supply control unit controls ON / OFF of power supplies of the plurality of flash memories.

(2) In the above-mentioned means (1), the power supply control unit calculates an address on an address bus to control ON / OFF of the power supplies of the plurality of flash memories.

(3) In the means (1) and (2), there is provided power supply monitoring means for detecting the sleep mode of the central processing unit, and the power supply monitoring means detects the sleep mode of the central processing unit. In this case, the power supply control unit turns off the power supplies of the plurality of flash memories.

(4) In the above (1) to (3) means, a cache memory is provided inside or outside the central processing unit, and the power supply is provided only during an access time for accessing the plurality of flash memories from the cache memory. The control unit turns on the power supplies of the plurality of flash memories.
It is characterized by

[0024]

According to each of the above means, in the information processing apparatus using the flash memory, the non-volatile property of the flash memory is used to turn off the power of the flash memory which is not accessed by the power control unit. It is possible to reduce the power consumption of the flash memory which is not accessed.

As a result, it is possible to further reduce the power consumption in the information processing device using the flash memory.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numerals, and the repeated description thereof will be omitted.

[Embodiment 1] FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus using a flash memory which is an embodiment (Embodiment 1) of the present invention.

As shown in FIG. 1, the information processing apparatus according to the first embodiment includes a central processing unit (CPU) 1, a mask ROM 2,
Flash memory 3, power supply control unit 5, random access memory (RAM) 6, display memory 7, liquid crystal display control unit 8, liquid crystal display 9, IC card interface 10, IC card 11, data buffer 12, communication interface 13, peripherals. Device control unit 15, external storage device 16, keyboard 17, and system bus 14
Consists of

The central processing unit 1 has a mask ROM 2, a flash memory 3 and an RA via the system bus 14.
The program stored in M6 is read and executed.

Further, the central processing unit 1 is the system bus 1
Information is transferred to and from the display memory 7, the liquid crystal display controller 8, the IC card interface 10, and the data buffer 12 via the memory 4.

The external storage device 16 and the keyboard 17 are also provided.
Are connected to the central processing unit 1 via the peripheral device control unit 15 and the system bus 14.

The liquid crystal display control unit 8 displays on the liquid crystal display 9 using the information stored in the display memory 7.

In the first embodiment, an IC card 11 can be connected via the IC card interface 10, and various communication devices can be connected to the communication interface 13 connected via the data buffer 12. It is possible to connect.

The power supply controller 5 outputs a power supply control signal 4 to the flash memory 3, and the power supply control signal 4 turns on / off the power supply of the flash memory 3.

For example, when the central processing unit 1 is not accessing the flash memory 3, the power of the flash memory 3 is turned off by the power control signal 4 from the power control unit 5, and the central processing unit 1 is flash memory. 3 is accessed, the power supply control signal 4 from the power supply control unit 5 turns on the power supply of the flash memory 3.

FIG. 2 shows the power supply controller 5 in the first embodiment.
3 is a diagram showing an example of connection between the flash memory 3 and the flash memory 3.

As shown in FIG. 2, the flash memory 3 according to the first embodiment includes a plurality of flash memories (20,
21, 22, 23).

The power supply control section 5 and the plurality of flash memories (20, 21, 22, 23) respectively have power supply control signals 1 (24) to 4 (27) and enable signal 1 (28).
4 through (31).

Further, it is connected to the central processing unit 1 via the enable signal 32 and the clock 33, and can receive the address information via the system bus 14.

Next, the operation of the power supply controller 5 will be described.

The power supply controller 5 receives the address indicated by the central processing unit 1 from the central processing unit 1 via the system bus 14, performs the address calculation, and operates the flash memory (20, 21, 22, Turn on the power of 23).

For example, when the flash memory (20, 21, 22, 23) that needs to be operated is the flash memory 1 (20), power is supplied to the power supply control signal 1 (24), and the flash memory 1 (20) is supplied. Can be operated.

Since the enable signal 1 (28) is issued from the flash memory 1 (20) when the flash memory 1 (20) becomes operable, the enable signal 32 is generated from this enable signal 1 (28). , To the central processing unit 1.

FIG. 3 shows the power supply control unit 5 in the first embodiment.
It is a figure which shows the internal structure of.

As shown in FIG. 3, the power supply controller 5 operates the address from the central processing unit 1 by the address decoder 34 to generate chip select signals 1 (36) to 4 (39), and outputs the chip select signals 1 (36) to 4 (39). The power supply control signals 1 (24) to 4 (4) to
Output as (27).

Each flash memory (20, 21, 22,
The enable signals 1 (28) to 4 (31) of 23) are logically ANDed in the power supply control unit 5 and the flash memory (2
0, 21, 22, 23) can operate even one,
The enable signal 32 is output to the central processing unit 1 as being operable.

[Embodiment 2] In Embodiment 2, the power supply controller 5
The operation of the address decoder 34 is different from that of the first embodiment, but other configurations are the same as those of the first embodiment.

In the second embodiment, the flash memory (20, 21, 22,
Only 23) is operable.

FIG. 4 is an operation flowchart of the address decoder 34 in the power supply controller 5 in the second embodiment.

The operation of the address decoder 34 in the power control unit 5 in the second embodiment will be described below with reference to FIG.

In step 101, the power supply controller 5 acquires an address from the central processing unit 1, and in step 102,
The address decoder 34 in the power supply controller 5 bit-calculates the acquired address.

Next, in step 103, the flash memory (20, 21, 22, 23) including the acquired address
Only the chip select signal (36, 37, 38, 39) of No. is turned on, and in step 104, it is output to the flash memory (20, 21, 22, 23) as the power supply control signal (24, 25, 26, 27). To do.

For example, when the address indicated by the central processing unit 1 in FIG. 3 is the flash memory 1 (20), only the chip select signal 1 (36) is turned on, and this is latched to supply the power control signal 1 (24). Only the flash memory 1 (20) can be operated by being supplied with power.

[Third Embodiment] In the third embodiment, the power supply controller 5 is used.
Although the group table 40 is provided therein and the operation of the address decoder 34 is different from that of the first embodiment, other configurations are the same as those of the first embodiment.

In the third embodiment, the flash memory (20, 21, 22,
23) and flash memory (20, 2, 2) grouped with
1, 22, 23) are operable.

FIG. 5 shows the power supply controller 5 in the third embodiment.
It is a figure which shows the internal structure of.

As shown in FIG. 5, in the third embodiment, a group table 40 is provided inside the power control unit 5.

FIG. 6 is an operation flowchart of the address decoder 34 in the power supply controller 5 in the third embodiment.

The operation of the address decoder 34 in the power supply controller 5 in the third embodiment will be described below with reference to FIG.

In step 111, the power supply controller 5 acquires an address from the central processing unit 1, and in step 112,
Performs bit operation on the acquired address.

Next, in step 113, the flash memory (20, 21, 22, 23) including the acquired address
Of the grouped flash memories (20, 2) by referring to the group table 40 from the information.
1, 22, 23).

Next, the obtained flash memory (20,
21, 22, 23) chip select signals (36, 3
(7, 38, 39) is turned on and is output to the flash memory (20, 21, 22, 23) as a power supply control signal (24, 25, 26, 27).

For example, when the address indicated by the central processing unit 1 in FIG. 3 is the flash memory 1 (20) and the flash memory 2 (21) is grouped,
Only the chip select signal 1 (36) and the chip select signal 2 (37) are turned on and latched, and only the power supply control signal 1 (24) and the power supply control signal 2 (25) are supplied with power, and the flash memory 1 Only (20) and the flash memory 2 (21) can operate.

[Embodiment 4] In Embodiment 4, the power supply controller 5
The operation of the address decoder 34 is different from that of the first embodiment, but other configurations are the same as those of the first embodiment.

In the fourth embodiment, when a large program is read / written, the flash memory (20, 21, 22, 2) including the address indicated by the central processing unit 1 is used.
3) and the flash memories (20, 21, 22, 23) located at the addresses before and after it are operable.

FIG. 7 is an operation flowchart of the address decoder 34 in the power supply controller 5 in the fourth embodiment.

The operation of the address decoder 34 in the power supply controller 5 in the fourth embodiment will be described below with reference to FIG.

In step 121, the power supply controller 5 acquires an address from the central processing unit 1, and in step 122,
Information on the flash memory (20, 21, 22, 23) including the acquired address is calculated by bit operation on the acquired address, and the relative information in the flash memory (20, 21, 22, 23) including the acquired address Get the correct location address.

Next, in step 123, the flash memory (20, 21, 22, 23) including the acquired address
Only the chip select signals (36, 37, 38, 39) of are turned on.

Next, in step 124, it is judged whether or not the acquired relative position address is larger than the changeable value HADD. If it is larger, in step 125 the flash memory (20) including the acquired address. , 21, 2
Flash memory (20, 21, 22, 23) located at the address after the address
The chip select signals (36, 37, 38, 39) of
Let N.

If the relative position address acquired in step 124 is smaller than the changeable value HADD, it is checked in step 127 whether the acquired relative position address is smaller than the changeable value LADD. If it is determined to be smaller, in step 128, the flash memory (20, 21, 22, 23) including the acquired address has a continuous address, and the flash memory (20, 21, 22, The chip select signals (36, 37, 38, 39) of 23) are turned on.

Next, the chip select signals (36, 37, 38, 39) which are turned on are supplied with the power control signals (24,
25, 26, 27) as a flash memory (20, 2
1, 22, 23).

For example, when the address indicated by the central processing unit 1 in FIG. 3 is the flash memory 2 (21) and the relative position address in the flash memory 2 (21) is larger than HADD, the flash memory 2 ( 21)
Also, only the chip select signal 2 (37) and the chip select signal 3 (38) of the flash memory 3 (22) are turned on, and they are latched, and the power supply control signal 2 (2
5) and the power supply control signal 3 (26) are supplied with power, and only the flash memory 2 (21) and the flash memory 3 (22) can operate.

Alternatively, when the address indicated by the central processing unit 1 in FIG. 3 is the flash memory 2 (21) and the relative position address in the flash memory 2 (21) is smaller than LADD, the flash memory 1 ( Two
0) and the chip select signal 1 (36) and the chip select signal 2 (37) of the flash memory 2 (21).
Only ON, latch this, power control signal 1
Only (24) and the power supply control signal 2 (25) are supplied with power, and only the flash memory 1 (20) and the flash memory 2 (21) can operate.

[Fifth Embodiment] The fifth embodiment is the same as the first embodiment.
In the fourth embodiment, the power is not supplied to the flash memories (20, 21, 22, 23) when the information processing device is in the stopped state.

FIG. 8 shows the power supply controller 5 in the fifth embodiment.
It is a figure which shows the example of a connection with the flash memory (20, 21, 22, 23).

Since the other structure of the fifth embodiment is the same as that of the first embodiment, detailed description thereof will be omitted.

The power controller 5 and the flash memory (20,
21, 22, 23) means the power supply control signal 1 (2
4) to 4 (27), enable signals 1 (28) to 4 (3)
1) is connected.

Further, it is connected to the central processing unit 1 via the power supply monitoring signal 2 (43), and further, it is possible to receive address information from the central processing unit 1 via the system bus 14. .

The power supply monitoring circuit 41 is connected via the power supply monitoring signal 1 (42).

The power supply monitoring circuit 41 detects the sleep mode of the central processing unit 1 when there is no input to the information processing device for a certain period of time, and generates a power supply monitoring signal 1 (42),
The power supply monitoring signal 1 (42) is output to the central processing unit 1 as the power supply monitoring signal 2 (43).

The operation of the power supply controller 5 in this embodiment is as follows.

As described in the first to fourth embodiments, the power supply controller 5 causes the central processing unit 1 to use the flash memory (2) according to the address indicated by the central processing unit 1.
0, 21, 22, 23) power source is controlled.

When the power supply monitoring signal 1 (42) is received from the power supply monitoring circuit 41 and the power supply monitoring signal 1 (42) is ON, the power supply control signals 1 (24) to 4 (27) can be output. When it is OFF, output is stopped.

FIG. 9 shows the power supply controller 5 in the fifth embodiment.
It is a figure which shows the internal structure of.

Incidentally, in FIG. 9, the generation circuit for generating the enable signal 32 in FIG. 3 is omitted.

Power supply monitoring signal 1 from the power supply monitoring circuit 41
By (42), the power supply in the power supply controller 5 is controlled.

That is, when the power supply monitoring signal 1 (42) is ON, the address decoder 34 and the latch 35 operate, and the output signals from the latch 35 are the power supply control signals 1 (24) to 4 (4).
(27) is output from the power supply control unit 5, and when the power supply monitoring signal 1 (42) is OFF, the power supply control signal 1 (2)
All of 4) to 4 (27) are also turned off.

According to the fifth embodiment, the power supply monitoring circuit 41 detects the stopped state of the information processing apparatus, and when the information processing apparatus is in the stopped state, the flash memory (20, 21, 22,
Since power is not supplied to 23), power consumption can be suppressed.

In the fifth embodiment, the power supply monitoring circuit 41 and the power supply control section 5 are separately constructed.
It is also possible to integrate these functions.

[Sixth Embodiment] The sixth embodiment is the same as the first embodiment.
In the fifth embodiment, the flash memory (20, 2,
, 22, 23) to the cache memory, until the data transfer is completed,
The flash memory (20, 21, 22, 23) is supplied with power.

FIG. 10 is a diagram showing an example of connection between the power supply controller 5 and the flash memories (20, 21, 22, 23) in the sixth embodiment.

Since the other structure of the sixth embodiment is the same as that of the first embodiment, the detailed description thereof will be omitted.

The power controller 5 and the flash memory (20,
21, 22, 23) means the power supply control signal 1 (2
4) to 4 (27), enable signals 1 (28) to 4 (3)
1) is connected.

Further, it is connected to the central processing unit 1 via the enable signal 32 and the cache signal 51, and it is possible to receive address information from the central processing unit 1 via the system bus 14.

In the central processing unit 1, there is a cache memory 50, which is a flash memory (20, 21, 22, 2).
The data in 3) is once transferred to the cache memory 50 and processed in the central processing unit 1.

The operation of the power supply controller 5 in the sixth embodiment is as follows.

When it is necessary to transfer data from the flash memory (20, 21, 22, 23) to the cache memory 50 from the central processing unit 1 to the power supply control unit 5, the cache is kept until the data transfer is completed. Signal 51 is issued.

In the power supply control unit 5, the power supply control signals 1 (24) to 4 (4) only while the cache signal 51 is being input.
(27) is output to the flash memory (20, 21, 2
It is assumed that the enable signals 1 (28) to 4 (31) of 2, 23) are output to the central processing unit 1 as the enable signal 32.

Further, as described in the first to fifth embodiments, the power control unit 5 uses the flash memory (20, 21, 22, 23) from the central processing unit 1 to the address indicated by the central processing unit 1. Control the power supply.

FIG. 11 is a diagram showing the timing of the cache signal 51, the power supply control signals 1 (24) to 4 (27) and the enable signal 32 in the sixth embodiment.

The operation timing in the sixth embodiment will be described with reference to FIG.

Cache signal 51 from central processing unit 1
Accordingly, the power supply controller 5 outputs the power supply control signals 1 (24) to 4 (27) after the time t1.

Thus, the flash memory (20, 2,
1, 22, 23) are powered and enable signal 1
(28) to 4 (31) are output to the power supply controller 5.

As a result, the power supply control unit 5 outputs the enable signal 32 after a time t2 from the output of the power supply control signal.

After the data transfer, the cache signal 51 is OF
As it becomes F, the power supply control signals 1 (24) to 4 (2
7) is turned off and the flash memory (20, 21, 2)
2, 23) is stopped.

As described above, according to the sixth embodiment, from the cache memory 50 to the flash memory (2
The power of the flash memory (20, 21, 22, 23) is turned on only when a data transfer request occurs in (0, 21, 22, 23), so that power consumption can be suppressed.

In the sixth embodiment, the cache memory 50 can be provided outside the central processing unit 1.

Furthermore, in the sixth embodiment, the power supply of the power supply control unit 5 can be controlled by the cache signal 51.

In each of the above embodiments, the case where the data is read from the flash memory (20, 21, 22, 23) has been described.
Also when writing data to (1, 22, 23),
It goes without saying that the present invention is applicable.

Although the present invention has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and it goes without saying that various modifications can be made without departing from the scope of the invention.

[0113]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) In an information processing device having a flash memory, the non-volatility of the flash memory is used,
Since the power supply control unit turns off the power of the flash memory which is not accessed, the power consumption of the flash memory which is not accessed can be reduced.

As a result, the power consumption can be further reduced in the information processing device using the flash memory.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of an information processing apparatus using a flash memory which is an embodiment (embodiment 1) of the present invention.

FIG. 2 is a diagram showing an example of connection between a power supply control unit and a flash memory according to the first embodiment.

FIG. 3 is a diagram illustrating an internal configuration of a power supply control unit according to the first embodiment.

FIG. 4 is an operation flowchart of an address decoder in the power supply control unit according to the second embodiment.

FIG. 5 is a diagram showing an internal configuration of a power supply control unit in the third embodiment.

FIG. 6 is an operation flowchart of an address decoder in the power supply control unit according to the third embodiment.

FIG. 7 is an operation flowchart of the address decoder in the power supply control unit according to the fourth embodiment.

FIG. 8 is a diagram showing an example of connection between a power supply control unit and a flash memory according to a fifth embodiment.

FIG. 9 is a diagram illustrating an internal configuration of a power supply control unit according to the fifth embodiment.

FIG. 10 is a diagram showing an example of connection between a power supply control unit and a flash memory in the sixth embodiment.

FIG. 11 is a diagram showing timings of a cache signal, a power supply control signal, and an enable signal in the sixth embodiment.

[Explanation of symbols]

1 ... Central processing unit, 2 ... Mask ROM, 3, 20, 2
1, 22, 23 ... Flash memory, 4, 24, 25,
26, 27 ... Power supply control signal, 5 ... Power supply control unit, 6 ... RA
M, 7 ... Display memory, 8 ... Liquid crystal display control unit,
9 ... Liquid crystal display, 10 ... IC card interface, 11 ... IC card, 12 ... Data buffer, 13 ...
Communication interface, 14 ... System bus, 15 ... Peripheral device control unit, 16 ... External storage device, 17 ... Keyboard,
28, 29, 30, 31, 32 ... Enable signal, 33
... clock, 34 ... address decoder, 35 ... latch,
36, 37, 38, 39 ... Chip select signal, 40 ...
Group table, 41 ... Power supply monitoring circuit, 42, 43 ...
Power supply monitoring signal, 50 ... Cache memory, 51 ... Cache signal.

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI Technical display location G11C 16/06 G11C 17/00 309 D

Claims (7)

[Claims] 1. A central processing unit, a main storage unit, a display unit, an external interface, a power supply control unit, and a bus connecting them, and a part of the main storage unit is a plurality of flash memories. An information processing device configured, wherein the power supply control unit controls ON / OFF of power supplies of the plurality of flash memories. 2. The information processing apparatus according to claim 1, wherein the power supply control unit calculates an address on an address bus to turn on / off the power supply of the plurality of flash memories.
An information processing device characterized by controlling OFF. 3. The information processing apparatus according to claim 1 or 2, wherein the power control section controls the information processing apparatus.
An information processing apparatus, wherein the flash memory that is turned on is a flash memory including an address output by the central processing unit. 4. The information processing apparatus according to claim 1, wherein the flash memory whose power is turned on under the control of the power control unit includes a flash including an address output by the central processing unit. An information processing apparatus comprising a memory and a flash memory including an upper address or a lower address that is continuous with an address output by the central processing unit. 5. The information processing apparatus according to claim 1, further comprising a group table for grouping the plurality of flash memories in a power supply control unit, the power supply being controlled based on the control of the power supply control unit. An information processing apparatus, wherein the flash memory whose ON is ON is a plurality of flash memories grouped based on the group table. 6. The information processing device according to claim 1, further comprising a power supply monitoring unit for detecting a sleep mode of the central processing unit, wherein the power supply monitoring unit is provided. An information processing apparatus, wherein the power supply control unit turns off the power supplies of the plurality of flash memories when a sleep mode of the central processing unit is detected. 7. The information processing apparatus according to claim 1, further comprising a cache memory inside or outside the central processing unit, the cache memory including the plurality of flash memories. The information processing apparatus, wherein the power supply control unit turns on the power supplies of the plurality of flash memories only during an access time for accessing the.