JPH0845809A - Exposure method and exposure apparatus thereof - Google Patents

Abstract

(57) [Summary] [Object] To provide an exposure method and apparatus capable of forming a semiconductor device pattern without disconnection. An exposure method for forming a pattern on a semiconductor substrate which is divided at a boundary portion between adjacent exposure fields, and the divided portions are connected to each other to form a pattern formed over two exposure fields. The patterns are exposed such that the ends of the patterns respectively provided in the two exposure fields overlap each other at the boundary portion of the exposure fields.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an exposure method and an exposure apparatus for exposing a mask pattern formed on a semiconductor substrate with an electron beam or the like in a semiconductor manufacturing process.

[0002]

2. Description of the Related Art FIG. 12 is a diagram showing an example of a process of exposing a mask pattern formed on a wafer in a semiconductor manufacturing process by using an electron beam apparatus. FIG.
In the process shown in FIG. 2, pattern design is first performed, and a semiconductor device pattern is created here. Next, the exposure data is created by converting the data of the semiconductor device pattern into a format that can be recognized and exposed by the electron beam exposure apparatus, and the exposure data is exposed on the semiconductor substrate using the electron beam exposure apparatus. And a desired pattern is formed. Further, in creating the exposure data, as shown in FIG. 13, the semiconductor pattern 1 is divided in units of the exposure field 2, and the exposure apparatus sequentially repeats the exposure in units of the exposure field 2 to form the semiconductor device pattern 1. The whole is formed on a semiconductor substrate.

[0003]

As described above, in the conventional exposure apparatus, the entire semiconductor device pattern 1 is formed on the semiconductor substrate by sequentially repeating the exposure in units of the exposure field 2. In this case, the positioning accuracy of each exposure field 2 and its stability are very important for forming the semiconductor device pattern 1 on the semiconductor substrate. This will be further described with reference to FIGS. 14 and 15.

That is, FIG. 14 is an enlarged view of a part of the exposure field 2. In the figure, an AB line connecting points A and B, and points C and D are shown. A CD line connecting with and indicates a boundary between the exposure fields 2 and 2, and FIG. 15 is an enlarged view showing a part of the semiconductor device pattern formed around the point B on the semiconductor substrate. . Then, in the conventional semiconductor device pattern, the correction error of the beam deflection system and its change with time, the positioning error of the exposure field 2 which is respectively caused by the vibration of the exposure stage, the plane distortion of the semiconductor substrate, and the variation thereof, and so on are shown in FIG. As shown by the patterns P1 and P2, the boundary portions AB and BC are separated from each other, and disconnection is likely to occur, which may cause a fatal defect in operating the semiconductor device.

Therefore, the boundary portion is most required to have a positioning accuracy, but the positioning accuracy has a limit, and it is necessary to sufficiently cope with the manufacturing of semiconductor devices in which the miniaturization tends to progress more and more in the future. There is a risk that it will not be possible, which is a problem.

The present invention has been made in view of the above problems, and an object thereof is to provide an exposure method and an apparatus therefor capable of forming a semiconductor device pattern without disconnection.

[0007]

According to the method of the present invention, this object is divided at the boundary portion between adjacent exposure fields, and the divided portions are connected to each other to extend over two exposure fields. In the exposure method of forming a pattern provided on a semiconductor substrate, the patterns are exposed such that the ends of the patterns provided in the two exposure fields overlap each other at the boundary portion of the exposure fields. Will be achieved.

Further, in the apparatus of the present invention, this object is divided at the boundary portion between adjacent exposure fields,
In an exposure apparatus that connects the divided portions to each other to form a pattern formed over two exposure fields on a semiconductor substrate, the patterns are divided at adjacent exposure field boundary portions, and the divided portions are divided. This is achieved by providing a boundary processing circuit for processing each end of each pattern of the part so as to overlap each other at the boundary part of the exposure field.

[0009]

According to this, since there is a pattern in which the exposure fields are overlapped and exposed, the correction error of the beam deflection system and its change over time, the vibration of the exposure stage, and the plane distortion of the semiconductor substrate. Even if a positioning error of the exposure field and its variation occur due to such factors, disconnection does not occur.

[0010]

Embodiments of the present invention will be described in detail below with reference to the drawings. 1 to 4 show a first embodiment of the present invention, and FIG. 1 is an enlarged view showing a part of a device pattern formed on a semiconductor substrate by using this exposure procedure.
2 to 4 are diagrams showing a procedure until the device pattern shown in FIG. 1 is created. Next, a procedure for forming the device pattern shown in FIG. 1 will be described with reference to FIGS.

First, in the device pattern formed on the semiconductor substrate, there is a pattern p formed across the two exposure fields 2a and 2b across the boundary BC as shown in FIG. Divides the pattern p into the exposure field 2a side and the exposure field 2b side at the boundary portion B-C, the pattern existing on the exposure field 2a side is pa (see FIG. 3), and the pattern existing on the exposure field 2b side is divided. pb (see FIG. 4).

Next, patterns pa and p which are adjacent to each other
After the end of b is extended by d = 0.15 μm on the signal data (see FIGS. 3 and 4), it is output in the format of the exposure apparatus to create exposure data. After inputting this exposure data into the exposure device, each exposure field 2a
, 2b, the size at the end is d = 0.15 μm
Expand and expose on a semiconductor substrate. Then, the device pattern shown in FIG. 1 is formed. That is, in the device pattern shown in FIG. 1, 2d = 0.3 μm is overlapped between the exposure fields 2a and 2b and exposed as shown in FIG. 1, and the double-exposed region (2d) is exposed on the semiconductor substrate. Will have.

Therefore, the first embodiment has a pattern in which 2d = 0.3 μm is overlapped and exposed between the exposure fields 2a and 2b, so that the correction error of the beam deflection system and its time elapse. Even if a change occurs, a positioning error of the exposure field 2 caused by a vibration of the exposure stage, a plane distortion of the semiconductor substrate, or the like, a variation thereof, or the like does not cause a disconnection. Further, even if the miniaturization progresses in the future, it will be possible to sufficiently cope with it.

FIGS. 5 to 7 show a second embodiment of the present invention. FIG. 5 shows a device pattern formed on a semiconductor substrate by using this exposure procedure, and FIGS. FIG. 6 is a diagram showing each procedure until the device pattern shown in FIG. 5 is created. Therefore, next, a procedure for forming the device pattern shown in FIG. 5 will be described with reference to FIGS. 6 and 7. 5 to 7, the same symbols as those in FIGS. 1 to 4 indicate the same components as those in FIGS. 1 to 4.

First, in the device pattern formed on the semiconductor substrate, as in the case of the first embodiment, the boundary portion B is formed.
When there is a pattern p formed across two exposure fields 2a and 2b across -C, the pattern p is divided into the exposure field 2a side and the exposure field 2b side at the boundary portion BC, and the exposure is performed. The pattern existing on the field 2a side is pa1 (see FIG. 6), and the exposure field 2b
The pattern existing on the side is designated as pb1 (see FIG. 7).

Next, patterns pa1 and p which are adjacent to each other
The end of b1 is extended by d1 = 0.15 .mu.m on the signal data. Next, each pattern is divided on the opposite side at a position separated by d2 = 0.15 μm, and a pattern pa2 (see FIG. 6) is created on the exposure field 2a side and a pattern pb2 (see FIG. 7) is created on the exposure field 2b side. To do. Further, a prescribed exposure amount Q1 corresponding to the resist sensitivity is assigned to the patterns pa1 and pb1, and an exposure amount Q2 = (Q1 / 2) is assigned to the patterns pa2 and pb2, respectively, and then output in the format of the exposure apparatus. Create exposure data.

Next, after inputting this exposure data into the exposure apparatus, the sizes of the exposure fields 2a and 2b are respectively d.
= 0.15 μm extension and exposed on the semiconductor substrate. Then
The device pattern shown in FIG. 5 is formed. That is,
In the device pattern shown in FIG. 5, 2d = 0.3 μm is overlapped between the exposure fields 2a and 2b as shown in FIG.
d). Further, the exposure amount in the double-exposed region (2d) becomes the specified exposure amount Q1.

Therefore, even in the case of the second embodiment, since there is a pattern in which 2d = 0.3 μm is overlapped and exposed between the exposure fields 2a and 2b, a correction error of the beam deflection system and Even if there is a positioning error of the exposure field 2 caused by such changes over time, vibration of the exposure stage, plane distortion of the semiconductor substrate, fluctuations thereof, etc., disconnection will not occur. Further, even if the miniaturization progresses in the future, it will be possible to sufficiently cope with it. Further, since the exposure amount in the double-exposed region (2d) is the same prescribed exposure amount Q1 as in the other regions, it is possible to eliminate the pattern thickening in the overlapping portion and obtain a device pattern with high dimensional accuracy. be able to.

In the second embodiment, the pattern p
I disclosed the case where a2 and pb2 were created once, respectively.
If the same pattern is created at the same position twice or three times and the exposure doses to be assigned are Q2 = Q1 / 4 and Q1 / 6, it is possible to form a device pattern without disconnection and with high dimensional accuracy.

8 to 10 show a third embodiment of the present invention. FIG. 8 shows a device pattern formed on a semiconductor substrate by using this exposure procedure, and FIGS. 9 and 10 show FIG.
FIG. 6 is a diagram showing a procedure until the device pattern shown in FIG. Therefore, next, a procedure for forming the device pattern shown in FIG. 8 will be described with reference to FIGS. 9 and 10. 8 to 10 that are the same as those in FIGS. 1 to 4 are the same as those in FIGS. 1 to 4.

First, among the device patterns formed on the semiconductor substrate, as in the case of the first and second embodiments,
Two exposure fields 2a, 2 across the boundary B-C
When the pattern p formed over b is present, the pattern p is divided into the exposure field 2a side and the exposure field 2b side at the boundary portion BC, and the exposure field 2
The pattern existing on the a side is pa1 (see FIG. 9), and the pattern existing on the exposure field 2b side is pb1 (see FIG. 10).
And

Next, the patterns pa1 and pb1 are divided at positions separated from the boundary portion BC by d3 = 0.3 .mu.m to form patterns pa1, pa3, pb1 and pb3.
Further, the same pattern as the patterns pa3 and pb3 is created four times at the same position. Therefore, as a result, the pattern pa3,
This means that pb3 overlaps the same position five times. On the other hand, the exposure amount Q1 is assigned to the patterns pa1 and pb1, and the exposure amount Q2 = Q1 / 5 is assigned to the patterns pa3 and pb3, and thereafter, the exposure data is created in the format of the exposure apparatus to create exposure data.

Next, after inputting this exposure data into the exposure apparatus, the semiconductor substrate is exposed in the same manner as the conventional one without the overlap between the exposure fields 2a and 2b. Then, the device pattern shown in FIG. 8 is formed. In this device pattern, the patterns pa3 and pb3 are exposed five times to average the fluctuations in the positioning accuracy of the mutual exposure fields, resulting in stable position accuracy.

Therefore, also in the case of the third embodiment, the correction error of the beam deflection system and its change with time, the positioning error of the exposure field 2 caused by the vibration of the exposure stage, the plane distortion of the semiconductor substrate, and the like, and the fluctuation thereof. Even if the above occurs, the disconnection will not occur. Further, even if the miniaturization progresses in the future, it will be possible to sufficiently cope with it.
Furthermore, since the exposure amount in the five-fold exposed region (pa3, pb3) is the same prescribed exposure amount Q1 as in the other regions,
It is possible to eliminate the thickness of the pattern in the overlapping portion and obtain a device pattern with high dimensional accuracy.

FIG. 11 is a block diagram of the exposure apparatus shown as the fourth embodiment of the present invention. In FIG. 11, this exposure apparatus has a control unit (CPU) 11 for controlling the entire apparatus in a predetermined procedure, and the control unit 11 has a pattern memory 12, a graphic development circuit 13, and a field boundary processing circuit 14. A rectangular division circuit 15, a beam blanking control circuit 16, a beam shaping control circuit 17, a deflection control circuit 18, and a stage drive control circuit 19 are connected. The exposure data processing is performed by the pattern memory 12, the graphic development circuit 13, the field boundary processing circuit 14, and the rectangular division circuit 15, and the exposure processing on the semiconductor substrate is performed by the beam blanking control circuit 16 and the beam shaping control circuit 17. , The deflection control circuit 18 and the stage drive control circuit 19,
The exposure data process and the exposure process are controlled by the control unit 11.

In this exposure apparatus, after the exposure data is loaded into the pattern memory 12, the exposure data received from the pattern memory 12 in the exposure field unit in the figure developing circuit 13 is developed as a figure. At this time, the presence / absence of a pattern crossing the boundary line of the exposure field is confirmed, and if there is a pattern, the field boundary processing circuit 14 performs the same pattern division and generation process and exposure amount as those described in the third embodiment, for example. The allocation process of is executed. In addition, the graphic data for which the graphic development processing has been completed in this way is divided by the rectangular division circuit 15 into exposure unit rectangles, and the control unit 11 determines the beam blanking circuit based on the rectangular data that has passed through the rectangular division circuit 15. 16, each of the control data is sent to the beam forming control circuit 17, the deflection control circuit 18, and the stage drive control circuit 19 to expose the semiconductor substrate.

Therefore, also in the case of the fourth embodiment, as in the case of the third embodiment, due to the correction error of the beam deflection system and its change over time, the vibration of the exposure stage, the plane distortion of the semiconductor substrate, etc. It is possible to form a pattern that does not cause a disconnection or the like even if a positioning error of the exposure field 2 that occurs and its variation occur. In addition, since the exposure data is in the conventional format in which the boundary processing of the exposure field is not performed, the exposure data creation time can be shortened and the exposure data amount is also compressed as compared with the first to third embodiments. Therefore, the hard disk of the exposure data creating computer and the pattern memory 12 of the exposure apparatus can be reduced in capacity, and the economical efficiency is improved. In the case of the fourth embodiment, the processing contents in the field boundary processing circuit 14 are the same as those of the third embodiment, but not limited to the case of the third embodiment, the first and second Of course, the same processing as that in the embodiment can be performed.

[0028]

As described above, according to the present invention,
Since there are overlapping exposure patterns between the exposure fields, the exposure fields generated by the correction error of the beam deflection system and its change over time, the vibration of the exposure stage, the plane distortion of the semiconductor substrate, etc. Even if a positioning error and its variation occur, the disconnection will not occur. Further, even if the miniaturization progresses in the future, it will be possible to sufficiently cope with it.

[Brief description of drawings]

FIG. 1 is a diagram showing a pattern formed on a semiconductor substrate shown as a first embodiment of the present invention.

FIG. 2 is a diagram showing an exposure procedure of the first embodiment.

FIG. 3 is a diagram showing an exposure procedure of the first embodiment.

FIG. 4 is a diagram showing an exposure procedure of the first embodiment.

FIG. 5 is a diagram showing a pattern formed on a semiconductor substrate shown as a second embodiment of the present invention.

FIG. 6 is a diagram showing an exposure procedure of the second embodiment.

FIG. 7 is a diagram showing an exposure procedure of the second embodiment.

FIG. 8 is a diagram showing a pattern formed on a semiconductor substrate shown as a third embodiment of the present invention.

FIG. 9 is a diagram showing an exposure procedure of the third embodiment.

FIG. 10 is a diagram showing an exposure procedure of the third embodiment.

FIG. 11 is a block configuration diagram of an exposure apparatus shown as a fourth embodiment of the present invention.

FIG. 12 is a diagram showing an example of a conventional process for forming a mask pattern.

FIG. 13 is a diagram illustrating a conventional mask pattern forming method.

FIG. 14 is a diagram illustrating a conventional mask pattern forming method.

FIG. 15 is a diagram illustrating a conventional mask pattern forming method.

[Explanation of symbols]

1 semiconductor pattern 2 exposure field 2a exposure field 2b exposure field p pattern

Claims (4)

[Claims] 1. An exposure method for forming a pattern on a semiconductor substrate, which is divided at a boundary portion between adjacent exposure fields, and these divided portions are connected to each other to form a pattern provided over two exposure fields. An exposure method, wherein the patterns are exposed such that the ends of the patterns respectively provided in one exposure field overlap each other at the boundary portion of the exposure fields. 2. The overlapped pattern portions are exposed at the same position by repeating n times with an exposure amount of 1 / n (where n is a positive integer) of an appropriate exposure amount in each exposure field. The exposure method according to claim 1. 3. An exposure method for forming a pattern on a semiconductor substrate which is divided at a boundary portion between adjacent exposure fields, and the divided portions are connected to each other to form a pattern provided over two exposure fields. It is characterized in that the exposure amount of the region part which is separated from the part by a predetermined amount inward is repeated n times with an exposure amount of 1 / n of the proper exposure amount (where n is a positive integer), and the same position is exposed. Exposure method. 4. An exposure apparatus for forming a pattern formed on a semiconductor substrate, which is divided at a boundary portion between adjacent exposure fields and which connects the divided portions to each other to form two exposure fields. A boundary processing circuit is provided for dividing a pattern at a boundary portion between adjacent exposure fields and processing each end of each pattern of the divided portion so as to overlap each other at the boundary portion of the exposure field. An exposure apparatus.