JPH0845867A - Semiconductor device manufacture and displaying device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device manufacturing which allows impurity doping to a semiconductor layer at a low temperature. CONSTITUTION:Ion shower using phosphine gas, which is diluted with hydrogen gas and helium, is used for forming a source/drain area 5. Since the ionization probability of helium gas is larger than that of hydrogen gas, helium gas is decomposed and ionized more easily than hydrogen gas. As a result, in addition to the fact that hydrogen gas and phosphine gas are ionized by high-frequency energy, molecules of hydrogen gas and phosphine gas collide with helium ions and ionization is accelerated. Therefore, the ionization probability of phosphine gas is remarkably improved, and the efficiency of phosphorus ion implantation to a polycrystal silicon film 2 is also improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device and a display device.

[0002]

2. Description of the Related Art In recent years, an active matrix type liquid crystal display (LCD) has attracted attention as a high quality display device. As a pixel driving element (pixel driving transistor) of the active matrix LCD, a thin film transistor using a polycrystalline silicon film formed on a transparent insulating substrate as an active layer (hereinafter,
Development of a polycrystalline silicon TFT (referred to as a thin film transistor) is in progress.

Polycrystalline silicon TFTs have the advantage of higher mobility and higher driving capability than thin film transistors using an amorphous silicon film as an active layer (hereinafter referred to as amorphous silicon TFTs). Therefore, polycrystalline silicon T
If the FT is used, a high-performance LCD can be realized, and not only the pixel portion (display portion) but also the peripheral drive circuit (driver) can be integrally formed on the same substrate.

Conventional polycrystalline silicon TFTs have been formed using a high temperature process of about 1000 ° C. (called a high temperature process). The high temperature process follows the LSI technology which has a sufficient technical accumulation for many years. Therefore, a polycrystalline silicon TFT formed by a high temperature process
(High temperature polycrystalline silicon TFT) has excellent device characteristics, reliability and reproducibility. However, since the high temperature process has a high process temperature, there is no choice but to use quartz glass for the substrate. Quartz glass becomes extremely expensive as it grows in size, and at the present time there is a limit to the size increase.
Substrate size is limited. Therefore, the panel size of the LCD, which is cost-effective, is 2 inches or less, and although it can be sufficiently used for a viewfinder of a video camera or a liquid crystal projector, it cannot be used for a direct view because the panel size is too small.

On the other hand, since the amorphous silicon TFT can be formed by using a low temperature process of 400 ° C. or lower, a normal glass can be used for the substrate. Although ordinary glass is about 1/10 the price of quartz glass and there is no limit in size, high heat-resistant glass commercially available for LCDs (for example, Corning Inc. in the United States).
"7059" made in Japan has a heat resistant temperature of about 600 ℃.

[0006] Therefore, a polycrystalline silicon TFT is set to 600 so that ordinary glass (high heat resistant glass) can be used for the substrate.
It is required to be formed by using a low temperature process of about ℃ or less (called a low temperature process). A polycrystalline silicon TFT formed by a low temperature process is called a low temperature polycrystalline silicon TFT. The problem with the low temperature polycrystalline silicon TFT is the method of forming the polycrystalline silicon film to be the active layer,
Examples include a method of forming a gate insulating film and a method of forming source / drain regions.

In the case of a normal MOS transistor (bulk transistor) formed on a single crystal silicon substrate, in order to form the source / drain regions, first, impurities are ion-implanted into the substrate, and then about 900 ° C. The implanted ions are activated by performing the above high-temperature heat treatment.

In order to form the source / drain regions in the polycrystalline silicon film in the same manner as described above, it is necessary to carry out heat treatment at a high temperature of about 900 ° C. or higher after ion implantation of impurities. When impurities are ion-implanted into the polycrystalline silicon film, the region into which the ions are implanted becomes amorphous. Therefore, in order to polycrystallize the amorphized region, heat treatment is performed at about 900 ° C. or higher. It is essential to do. Therefore, when a polycrystalline silicon TFT is manufactured by the same method as that of the bulk transistor, ordinary glass cannot be used for the substrate.

Therefore, there has been proposed a method of forming source / drain regions in a polycrystalline silicon film by using an ion shower with a phosphine (PH ₃ ) gas or a diborane (B ₂ H ₆ ) gas diluted with hydrogen gas. That is, as shown in FIG. 3, the polycrystalline silicon film 2 formed on the insulating substrate 1 is doped with phosphorus ions or boron ions, and at the same time, is irradiated with a hydrogen ion (proton) beam. Specifically, a non-mass spectrometric ion shower (ion implantation) device is used to apply high frequency energy to a mixed gas of hydrogen and phosphine or diborane to generate plasma. Then, hydrogen ions are generated, and phosphine or diborane is decomposed to generate phosphorus ions or boron ions. As a result, it becomes possible to diffuse and activate the impurities in the polycrystalline silicon film 2 without providing a special heat treatment step, and the source / drain regions can be formed. Even if the heat treatment is performed to ensure the diffusion of the impurities, the temperature is about 300 ° C. or lower. further,
When the ion shower is used, the impurity-doped region of the polycrystalline silicon film 2 is not amorphized as in the case of ion implantation. Therefore, a heat treatment for polycrystallizing the amorphized region is performed. Becomes unnecessary. Therefore, normal glass (high heat resistant glass) can be used for the insulating substrate 1.

Further, by irradiating the polycrystalline silicon film 2 with a hydrogen ion beam, the hydrogenation treatment of the polycrystalline silicon film 2 is simultaneously performed. That is, polycrystalline silicon has a defect that the bonding of silicon atoms in the crystal planes and crystal grain boundaries is not sufficient and many crystal defects (dangling bonds) are present. If there are crystal defects, fixed charges and interface states are likely to be formed, which makes it difficult to improve the electrical characteristics of the polycrystalline silicon TFT. Therefore, a treatment for stabilizing the crystal structure by reducing defects by bonding hydrogen atoms to defective portions of polycrystalline silicon is performed. This is hydrotreatment. Conventionally, as a method of hydrotreating,
A method of exposing a polycrystalline silicon film to hydrogen plasma, forming an amorphous silicon film or a silicon nitride film containing hydrogen on the polycrystalline silicon film, and then subjecting the hydrogen in the film to the polycrystalline silicon film by a subsequent heat treatment. The method of diffusion is used. However, if the polycrystalline silicon film 2 is irradiated with a hydrogen ion beam, the hydrogenation process is also performed at the same time, so that it is not necessary to provide a special process for the hydrogenation process
The manufacturing process is simplified and the throughput is also improved.

[0011]

However, when high-frequency energy is applied to a mixed gas of hydrogen and phosphine or diborane to generate plasma, the ionization probability of hydrogen gas is low, and therefore most of the applied high-frequency energy is generated. It is consumed for ionization of hydrogen gas. Therefore, the decomposition efficiency of the phosphine gas or diborane gas is lowered, the ionization probability is also lowered, and the implantation efficiency of phosphorus ions or boron ions into the polycrystalline silicon film 2 is deteriorated. as a result,
Since the polycrystalline silicon film 2 cannot be doped with a necessary amount of impurities, the source / source formed on the polycrystalline silicon film 2 cannot be doped.
It becomes difficult to sufficiently reduce the resistance of the drain region. When the resistance value of the source / drain region becomes high, the device characteristics of the polycrystalline silicon TFT deteriorate.

By the way, if the high-frequency energy is increased correspondingly in anticipation of the ionization energy of hydrogen gas, the polycrystalline silicon film can be sufficiently doped with impurities, so that the source / drain regions can be sufficiently lowered. It becomes possible to make resistance. However, since the high frequency energy (maximum accelerating voltage) that can be generated by the current non-mass spectrometry type ion shower device has a limit in the standard, the high frequency energy cannot be increased unnecessarily. Further, if the high-frequency energy is increased, the power consumption is also increased, which increases the production cost.

The present invention has been made to solve the above problems, and has the following objects. 1) To provide a method for manufacturing a semiconductor device capable of improving throughput in doping a semiconductor layer with impurities by a low temperature process.

2) To provide a method of manufacturing a semiconductor device capable of sufficiently reducing the resistance of a semiconductor layer when doping the semiconductor layer with impurities by a low temperature process. 3) To provide a method for manufacturing a semiconductor device capable of manufacturing a transistor having excellent element characteristics with high throughput.

4) To provide a method for manufacturing a display device having excellent image quality, and particularly to provide a high-throughput manufacturing method.

[0016]

The gist of the present invention is to provide a step of doping an impurity into a semiconductor layer by irradiating an ion shower of impurities.

According to a second aspect of the invention, the semiconductor layer is irradiated by irradiating an ion shower with a mixed gas of a gas containing a p-type or n-type impurity and a gas containing an element compensating for a grain boundary of the semiconductor layer. The gist of the invention is that it includes a step of doping impurities.

According to a third aspect of the present invention, an ion shower is irradiated with a mixed gas of a gas containing a p-type or n-type impurity, a gas containing an element compensating the grain boundaries of the semiconductor layer, and an inert gas. Therefore, the gist of the present invention is to provide a step of doping the semiconductor layer with impurities.

In a fourth aspect of the present invention, high frequency energy is applied to a gas containing p-type or n-type impurities diluted with a mixed gas of a gas containing an element compensating for grain boundaries of a semiconductor layer and an inert gas. Plasma is generated to dope the semiconductor layer with impurity ions, and at the same time, the semiconductor layer is irradiated with an ion beam of an element that compensates for grain boundaries of the semiconductor layer and an ion beam of an inert gas. Is the gist.

According to a fifth aspect of the invention, a step of forming a gate insulating film on the semiconductor layer, a step of forming a gate electrode on the gate insulating film, and a self-alignment technique using the gate electrode are applied to the semiconductor layer. In order to form the source region and the drain region, by irradiating an ion shower with a mixed gas of a gas containing a p-type or n-type impurity, a gas containing an element compensating for the grain boundary of the semiconductor layer, and an inert gas. The gist is that the semiconductor layer is provided with a step of doping impurities.

According to a sixth aspect of the present invention, the step of forming a gate insulating film on the semiconductor layer, the step of forming a gate electrode on the gate insulating film, and the self-alignment technique using the gate electrode are applied to the semiconductor layer. In order to form the source region and the drain region, high-frequency energy is applied to a gas containing p-type or n-type impurities diluted with a mixed gas of a gas containing an element that compensates for grain boundaries of a semiconductor layer and an inert gas, and plasma is generated. At the same time that the semiconductor layer is irradiated with an impurity ion and an inert gas ion beam for compensating the grain boundaries of the semiconductor layer. The summary will be given.

A seventh aspect of the invention is characterized in that, in the method of manufacturing a semiconductor device according to the fifth or sixth aspect, a gate electrode made of the same material as the semiconductor layer is formed.

The eighth aspect of the invention is characterized in that, in the method of manufacturing a semiconductor device according to the fifth or sixth aspect, a gate electrode made of a metal material is formed. A ninth aspect of the invention is summarized in the method for manufacturing a semiconductor device according to any one of the fifth to eighth aspects, including a step of forming a semiconductor layer on an insulating substrate.

The tenth aspect of the present invention is characterized in that the semiconductor device manufactured by the method for manufacturing a semiconductor device according to the ninth aspect is used as a pixel driving element.

[0025]

According to the first aspect of the invention, by irradiating the ion shower of impurities, it is possible to diffuse and activate the impurities in the semiconductor layer without providing a special heat treatment step. When a polycrystalline silicon film is used as the semiconductor layer, the polycrystalline silicon film doped with impurities is not amorphized, so that heat treatment for polycrystallizing the amorphized region is unnecessary. become. As a result, the manufacturing process can be simplified and the throughput can be improved. Further, even if the heat treatment is performed to make the diffusion of the impurities more reliable, the low-temperature treatment is sufficient, so that the throughput does not decrease.

According to the invention of claim 2, claim 1
In addition to the effect of the invention described in (1), when a polycrystalline silicon film is used as a semiconductor and hydrogen gas is used as a gas containing an element that compensates for grain boundaries of a semiconductor layer, doping and hydrogenation of impurities into the polycrystalline silicon film The processing and the processing can be performed simultaneously. Therefore, it is not necessary to provide a special step for hydrotreating, and the throughput can be improved.

The invention described in claim 3 has the same operation as the invention described in claim 2. Further, in the invention described in claim 3, if each gas is selected so that the ionization probability of the inert gas is higher than the ionization probability of the gas containing the element that compensates the grain boundary of the semiconductor layer, The active gas is decomposed and ionized more easily than the gas containing the element that compensates the grain boundary of the semiconductor layer. As a result, the ionization probability of the gas containing impurities is significantly improved, and the efficiency of implanting impurity ions into the semiconductor layer is also improved. Therefore, the resistance of the semiconductor layer can be sufficiently lowered.

The invention described in claim 4 has the same operation as the invention described in claim 2. Further, in the invention according to claim 4, if each gas is selected so that the ionization probability of the inert gas is larger than the ionization probability of the gas containing the element that compensates the grain boundary of the semiconductor layer, the high frequency is selected. When energy is applied to generate plasma, the inert gas is decomposed and ionized more easily than the gas containing the element that compensates the grain boundaries of the semiconductor layer. As a result, the gas containing the element that compensates the grain boundaries of the semiconductor layer and the gas containing the impurities are ionized by the high frequency energy, and the molecules of the gas containing the element and the gas containing the impurities that compensate the grain boundaries of the semiconductor layer. Ionization is also promoted by the collision of the ions with the ions of the inert gas. Therefore, the ionization probability of the gas containing impurities is significantly improved, and the efficiency of implanting impurity ions into the semiconductor layer is also improved. for that reason,
The resistance of the semiconductor layer can be sufficiently lowered without unnecessarily increasing the high-frequency energy. Further, since it is not necessary to increase the high frequency energy, it is possible to reduce the power consumption, and it is possible to keep the production cost low.

According to the invention of claim 5, claim 3
With the same operation as the invention described in (1), the resistance of the source region and the drain region formed in the semiconductor layer can be sufficiently lowered, and a transistor having excellent device characteristics can be obtained.

According to the invention of claim 6, claim 4
With the same operation as the invention described in (1), the resistance of the source region and the drain region formed in the semiconductor layer can be sufficiently lowered, and a transistor having excellent device characteristics can be obtained.

According to the invention of claim 7, by forming the gate electrode made of the same material as the semiconductor layer,
The work function of the semiconductor layer to be the active layer is the same as that of the gate electrode, so that the threshold voltage of the transistor can be lowered.

According to the eighth aspect of the invention, the resistance of the gate electrode can be reduced by using a low resistance metal as the gate electrode. According to the invention described in claim 9, a thin film transistor having excellent device characteristics can be manufactured with high throughput.

According to the tenth aspect of the invention, by using the thin film transistor having excellent element characteristics as the pixel driving element, a display device having excellent image quality can be manufactured with high throughput.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A manufacturing method of an embodiment in which the present invention is embodied in a planar type polycrystalline silicon TFT will be described below with reference to FIGS. In this embodiment, the same components as those of the conventional example shown in FIG.

Step 1 (see FIG. 1A): A non-doped polycrystalline silicon film 2 (film thickness: 500 Å) to be an active layer is formed on an insulating substrate (quartz glass, high heat resistant glass) 1.
There are the following methods for forming the polycrystalline silicon film 2.

A method for directly forming the polycrystalline silicon film 2; normal pressure CVD method, low pressure CVD method, plasma CVD method,
Photoexcitation CVD method, vapor deposition method, EB (Electron Beam) vapor deposition method, MBE (Molecular Beam Epitaxy) method, sputtering method and the like are used.

Among them, a reduced pressure CV utilizing the thermal decomposition of monosilane (SiH ₄ ) or disilane (Si ₂ H ₆ ).
The D method is general and the highest quality polycrystalline silicon film 2
Can be formed. In the low-pressure CVD method, the processing temperature is amorphous at 550 ° C. or lower, and polycrystalline at 620 ° C. or higher.

A plasma CVD method utilizing thermal decomposition of monosilane or disilane in plasma is also used. The processing temperature of the plasma CVD method is about 300 ° C. When hydrogen is added, the reaction is accelerated and an amorphous silicon film is formed. Then, when an inert gas (helium, neon, argon, krypton, xenon, radon) is added, plasma is excited and a polycrystalline silicon film is formed even at the same processing temperature.

A method of forming a polycrystalline silicon film 2 by polycrystallizing after forming an amorphous silicon film; a solid phase growth method or a melt recrystallization method is used. The solid phase growth method is a method in which an amorphous silicon film is subjected to heat treatment at about 600 ° C. for a long time of about 20 hours to polycrystallize it in a solid state to obtain a polycrystalline silicon film.

In the melt recrystallization method, only the surface of the amorphous silicon film is melted to achieve recrystallization and the substrate temperature is set to 60.
This is a method of keeping the temperature below 0 ° C.
(Rapid Thermal Annealing) method. The laser annealing method is a method in which the surface of an amorphous silicon film is irradiated with a laser to be heated and melted. The RTA method is a method in which the surface of an amorphous silicon film is irradiated with lamp light to be heated and melted.

Step 2 (see FIG. 1B): A gate insulating film 3 (thickness: 1000Å) is formed on the polycrystalline silicon film 2. There are the following methods for forming the gate insulating film 3.

[1] Method of forming silicon oxide film using oxidation method; high temperature oxidation method (dry oxidation method using dry oxygen, wet oxidation method using wet oxygen, oxidation method in steam atmosphere), low temperature Oxidation method (oxidation method in high-pressure steam atmosphere, oxidation method in oxygen plasma), anodic oxidation method, or the like is used.

Among them, the low temperature oxidation method at about 600 ° C. is general. When the high temperature oxidation method is used, it is necessary to use quartz glass for the insulating substrate 1. [2] Silicon oxide film, silicon nitride film,
Method for forming silicon oxynitride film (SiO _x N _y ); C
The VD method or PVD method is used. There is also a method of combining each film into a multilayer structure.

As the CVD method, an atmospheric pressure CVD method and a low pressure CVD method are used.
Method, plasma CVD method, photo-excited CVD method. For the formation of the silicon oxide film, thermal decomposition of monosilane or disilane, thermal decomposition of organic oxysilane (TEOS or the like), hydrolysis of silicon halide and the like are used. Ammonia and dichlorosilane (SiH ₂
Cl ₂ ), ammonia and monosilane, and thermal decomposition of nitrogen and monosilane are used. The silicon oxynitride film has the characteristics of both an oxide film and a nitride film, and can be formed by introducing a small amount of nitrogen oxide (N ₂ O) into the system for forming the silicon nitride film.

The PVD method includes vapor deposition method, EB vapor deposition method, MBE method.
Method and sputtering method. Then, the gate electrode 4 is formed on the gate insulating film 3 and patterned into a desired shape. As the material of the gate electrode 4, polycrystalline silicon (doped polysilicon) doped with impurities, metal silicide, polycide, refractory metal simple substance, other metals (aluminum, gold, silver, copper, etc.) are used.

There are the following methods for forming polycrystalline silicon doped with impurities. (1) First, a non-doped polycrystalline silicon film is formed in the same manner as the method for forming the polycrystalline silicon film 2 described above.
Next, the non-doped polycrystalline silicon film is doped with impurities to reduce the resistance before it can be used as the gate electrode 4. The method of doping impurities into the polycrystalline silicon film is as follows: (a) a film serving as an impurity diffusion source (PSG (Phospho-Silicate Glass) film, BSG) on the polycrystalline silicon film.
(Boro-Silicate Glass) film, etc.) and then heat treatment is performed to diffuse the impurities in the film that will become the impurity diffusion source into the polycrystalline silicon film. (B) Ion implantation or ion shower is there. It should be noted that the polycrystalline silicon film to be the gate electrode 4 may be doped with impurities simultaneously with the formation of the source / drain regions described later. In that case, in this step 2, the gate electrode 4 is formed only by patterning after forming the non-doped polycrystalline silicon film, and it is not necessary to dope the gate electrode 4 with impurities.

(2) When a polycrystalline silicon film is formed by the CVD method, a raw material gas is mixed with a gas containing impurities to simultaneously form the polycrystalline silicon film and dope the impurities.

Further, when the gate electrode 4 is formed of metal silicide, polycide, a single refractory metal, or another metal, the CVD method or the PVD method is used. Step 3 (see FIG. 1C): The self-alignment technique is used to form a source on the polycrystalline silicon film 2 using the gate electrode 4 as a mask.
The drain region 5 is formed. To form the source / drain regions 5, an ion shower using phosphine gas diluted with hydrogen gas and helium is used. That is, the polycrystalline silicon film 2 is irradiated with a hydrogen ion beam and a helium ion beam at the same time as phosphorus ion doping is performed. Specifically, a non-mass spectrometry type ion shower device is used to apply high frequency energy to a mixed gas of hydrogen, helium and phosphine to generate plasma.
Then, hydrogen ions and helium ions are generated, and phosphine is decomposed to generate phosphorus ions.
As a result, it is possible to diffuse and activate the impurities in the polycrystalline silicon film 2 without providing a special heat treatment step, and the source / drain regions 5 can be formed. Even if the heat treatment is performed to ensure the diffusion of the impurities, the temperature is about 300 ° C. or lower. Further, when the ion shower is used, the source / drain region 5 is not made amorphous as in the case of ion implantation, and therefore the heat treatment for polycrystallizing the amorphized region is also unnecessary. Therefore, normal glass (high heat resistant glass) can be used for the insulating substrate 1.

Here, when high frequency energy is applied to a mixed gas of hydrogen, helium and phosphine to generate plasma, the ionization probability of helium gas is higher than that of hydrogen gas, so that helium gas is more hydrogen gas. It is more easily decomposed and ionized. As a result, the hydrogen gas and the phosphine gas are ionized by the high frequency energy, and the ionization is also promoted by the collision of the molecules of the hydrogen gas and the phosphine gas with the helium ions.

Therefore, the ionization probability of the phosphine gas in the present example (mixed gas of hydrogen, helium, and phosphine) is significantly improved compared to the ionization probability of the phosphine gas in the conventional example (mixed gas of hydrogen and phosphine). It will be. As a result, the implantation efficiency of phosphorus ions into the polycrystalline silicon film 2 is also improved.

The present inventor has studied amorphous silicon at 600.degree.
An experiment was conducted under the following conditions for the polycrystalline silicon film 2 that was solid-phase grown for a long time. Experiment 1; When using only phosphine gas (5% diluted hydrogen gas base) (phosphine gas flow rate: 20 sccm, high frequency power (RF power); 80 W, accelerating voltage; 55 kV, lindose amount; 1 × 10 ¹⁶
dose / cm ² , pressure; 359.1 × 10 ^-4 Pa) The sheet resistance of the polycrystalline silicon film 2 (source / drain region 5) after doping was measured by the four-terminal method under the above conditions, but the resistance value was too high. It was impossible to measure. It is considered that this is because the polycrystalline silicon film 2 was made amorphous by the doping. That is, it is understood that the resistance of the polycrystalline silicon film 2 (source / drain region 5) cannot be lowered unless hydrogen gas is added to the phosphine gas.

Experiment 2: Using a mixed gas of phosphine gas (5% diluted hydrogen base) and hydrogen gas (corresponding to the conventional example) (phosphine gas flow rate: 8 sccm, hydrogen gas flow rate: 42 scc
m, RF power; 80 W, accelerating voltage; 55 kV, lindose amount; 1 × 10 ¹⁶ dose / cm ² , pressure; 532.0 × 10 ^-4 Pa) Sheet resistance of the polycrystalline silicon film 2 after doping under the above conditions is four terminals As a result of measurement by the method, it was 680 Ω / □.

Experiment 3: Phosphine gas (5% diluted hydrogen gas)
(Base) and a mixed gas of hydrogen gas and helium gas
(Corresponding to the present embodiment) (phosphine gas flow rate: 8 sccm, hydrogen gas flow rate: 22 scc
m, helium gas flow rate: 20 sccm, radio frequency (RF) power
ー ； 80W, Accelerating voltage ； 55kV, Lind dose ： 1 × 10 ¹⁶do
se / cm², Pressure; 532.0 x 10^-FourPa) Sheet of polycrystalline silicon film 2 after doping under the above conditions
As a result of measuring the resistance by the four-terminal method, it was 247 Ω / □.

As described above, in Experiment 3 (this embodiment), the sheet resistance of the polycrystalline silicon film 2 can be reduced to about 1/3 of Experiment 2 (conventional example) with the same high-frequency energy (RF power). it can. By the way, in Experiment 2, Experiment 3
To obtain the same sheet resistance as, the RF power is 80W →
It had to be increased to 200W. In other words, regarding the RF power, the implantation efficiency of phosphorus ions in Experiment 3 is 2.5 times that in Experiment 2. This injection efficiency can be further improved by optimizing the mixing ratio of hydrogen gas and helium gas. That is, the mixing ratio of hydrogen gas and helium gas; H ₂ / (H ₂ + He) =
0.01 to 0.8 is suitable, preferably 0.2 to 0.7, and particularly preferably 0.2 to 0.5. If it is smaller than this range, the sheet resistance of the polycrystalline silicon film 2 tends to be high, and if it is wide, the surface roughness of the polycrystalline silicon film 2 tends to be large.

Further, by irradiating the polycrystalline silicon film 2 with a hydrogen ion beam, the hydrogenation treatment of the polycrystalline silicon film 2 is simultaneously performed. Step 4 (see FIG. 2): An interlayer insulating film 6 is formed on the entire surface of the device. As the interlayer insulating film 6, a silicon oxide film formed by a CVD method or a PVD method, various silicate glasses, a silicon nitride film, or the like is used.

After that, contact holes 6a contacting the source / drain regions 5 are formed in the interlayer insulating film 6 and the source / drain electrodes 7 are formed to complete the n-channel polycrystalline silicon TFT.

As described above, according to this embodiment, by improving the implantation efficiency of phosphorus ions into the polycrystalline silicon film 2, the polycrystalline silicon film 2 can be efficiently doped with the necessary amount of impurities. . Therefore, even if the high frequency energy is not unnecessarily increased, the polycrystalline silicon film 2
The resistance of the (source / drain region 5) can be sufficiently lowered. Therefore, it is possible to form a low temperature polycrystalline silicon TFT having excellent device characteristics. Further, since it is not necessary to increase the high frequency energy, it is possible to reduce the power consumption, and it is possible to keep the production cost low.

Further, by using the ion shower,
There is no need to provide a heat treatment step for forming the source / drain regions 5. Further, since the hydrogenation process is performed at the same time when the source / drain regions 5 are formed, it is not necessary to provide a special process for the hydrogenation process. As a result, according to this embodiment, the manufacturing process can be simplified and the throughput can be improved. Even when a heat treatment step is provided to form the source / drain regions 5, a low temperature treatment of about 300 ° C. is sufficient, so that the time required for raising and lowering the temperature is short and the throughput is not lowered.

By using such a polycrystalline silicon TFT having excellent element characteristics as a pixel driving element of an active matrix type LCD, the image quality of the LCD can be improved. Further, the throughput of the LCD can be improved by improving the throughput of the polycrystalline silicon TFT.

By the way, when polycrystalline silicon is used as the material of the gate electrode 4, the gate electrode 4 and the active layer (polycrystalline silicon film 2) are made of the same material and have the same work function. It is possible to reduce the threshold voltage (Vth). On the other hand, when a metal is used as the material of the gate electrode 4, the resistance of the gate electrode 4 can be reduced.

The above embodiment may be modified as follows, and in that case, the same operation and effect can be obtained. (1) The phosphine gas is replaced with another gas containing an n-type impurity. Examples of such gas include PF ₃ and P
F ₅ , PCl ₃ , PCl ₅ , AsH ₃ , AsF ₃ , As
F ₅ , AsCl ₃ , AsCl ₅ and the like.

(2) Phosphine gas containing p-type impurities
P-channel polycrystalline silicon TFT
To form Examples of such gas include diborane gas,
BF ₃, BCl₃, BBr₃and so on.

(3) Replace the helium gas with another inert gas (neon, argon, krypton, xenon, radon). Since the ionization probability of each inert gas is higher than that of hydrogen gas, the same action and effect as those of the above-described embodiment can be obtained with any inert gas. However, the greater the molecular weight of the inert gas, the greater the damage to the polycrystalline silicon film 2 caused by the plasma. Therefore, an inert gas having a smaller molecular weight is preferable, and helium gas is most preferable.

(4) The hydrogen gas is replaced with a gas containing an appropriate element that compensates the grain boundaries of the polycrystalline silicon film 2. Such elements include hydrogen, fluorine, chlorine, and bromine. Since the ionization probabilities of these elemental gases are higher than those of the respective inert gases, the same action and effect as those of the above-described embodiment can be obtained with any elemental gas. However, when hydrogen gas is used as a compensating gas, the bond is broken at about 400 ° C.
When chlorine or bromine is used, the feature is that the bond can be maintained up to about 450-500 ℃.

(5) The channel region 2a of the polycrystalline silicon film 2 is doped with impurities to control the threshold voltage of the polycrystalline silicon TFT. In the polycrystalline silicon TFT formed by the solid phase growth method, the threshold voltage tends to shift in the depletion direction in the n-channel transistor and the threshold voltage tends to shift in the enhancement direction in the p-channel transistor. Especially, when the hydrogenation treatment is performed, the tendency becomes more remarkable. In order to suppress the shift of the threshold voltage, the channel region 2a may be doped with impurities.

(6) The present invention is applied not only to the planar type, but also to an inverted planar type, a staggered type, an inverted staggered type polycrystalline silicon TFT or an amorphous silicon TFT. (7) The insulating substrate 1 is replaced with a ceramic substrate or an insulating layer such as a silicon oxide film, and is applied to a contact image sensor, a three-dimensional IC or the like instead of the LCD.

(8) The polycrystalline silicon film 2 is replaced with an amorphous silicon film to form an amorphous silicon TFT. (9) The polycrystalline silicon film 2 is replaced with a single crystal silicon film. Further, the polycrystalline silicon film 2 is replaced with a single crystal silicon substrate to form a bulk transistor.

(10) The polycrystalline silicon TFT is replaced by an LCD
Instead, it is used as a charge transfer element in a memory cell of a dynamic RAM (DRAM) or a load element in a memory cell of a static RAM (SRAM).

Although the respective embodiments have been described above, the technical idea other than the claims which can be understood from the respective embodiments is as follows.
The effects will be described below. (A) In the method of manufacturing a semiconductor device according to claim 9, a step of forming an interlayer insulating film on the entire surface of the device, and a step of forming a contact hole in the interlayer insulating film to contact the source region and the drain region, And a step of forming a source electrode and a drain electrode.

In this way, the thin film transistor can be completed. (B) A method of manufacturing a semiconductor device according to any one of claims 5 to 9, comprising a step of doping an impurity into a portion of the semiconductor layer corresponding to a channel region.

By doing so, the threshold voltage of the transistor can be controlled. By the way, in this specification, a member according to the constitution of the invention is defined as follows.

(A) The insulating substrate includes not only a substrate made of any insulating material such as quartz glass, high heat-resistant glass, high heat-resistant resin, and ceramics, but also a metal substrate having an insulating layer such as a silicon oxide film on its surface. It also includes a conductive substrate such as.

(B) The semiconductor layer includes not only a polycrystalline silicon film but also an amorphous silicon film, a single crystal silicon film, and a single crystal silicon substrate.

[0074]

【The invention's effect】

1) It is possible to provide a method for manufacturing a semiconductor device capable of improving throughput when doping a semiconductor layer with impurities by a low temperature process.

2) It is possible to provide a method for manufacturing a semiconductor device capable of sufficiently reducing the resistance of a semiconductor layer when doping the semiconductor layer with impurities by a low temperature process.

3) It is possible to provide a semiconductor device manufacturing method capable of manufacturing a transistor having excellent element characteristics with high throughput. 4) A display device with excellent image quality can be manufactured with high throughput.

[Brief description of drawings]

FIG. 1 is a schematic sectional view for explaining a manufacturing method according to an embodiment.

FIG. 2 is a schematic cross-sectional view for explaining the manufacturing method of the embodiment.

FIG. 3 is a schematic sectional view for explaining a manufacturing method of a conventional example.

[Explanation of symbols]

1 Insulating Substrate 2 Polycrystalline Silicon Film as Semiconductor Layer 3 Gate Insulating Film 4 Gate Electrode 5 Source Region or Drain Region (Source / Drain Region)

Claims (10)

[Claims] 1. A method of manufacturing a semiconductor device, which comprises a step of doping an impurity into a semiconductor layer by irradiating an ion shower of impurities. 2. A step of doping an impurity into a semiconductor layer by irradiating an ion shower with a mixed gas of a gas containing a p-type or n-type impurity and a gas containing an element compensating for a grain boundary of the semiconductor layer. For manufacturing a semiconductor device. 3. A semiconductor layer is doped with impurities by irradiating an ion shower with a mixed gas of a gas containing a p-type or n-type impurity, a gas containing an element that compensates for grain boundaries of the semiconductor layer, and an inert gas. A method of manufacturing a semiconductor device including a step of doping. 4. A semiconductor is generated by applying high frequency energy to a gas containing p-type or n-type impurities diluted with a mixed gas of an inert gas and a gas containing an element compensating for grain boundaries of a semiconductor layer to generate plasma. A method for manufacturing a semiconductor device, which comprises a step of irradiating a semiconductor layer with an ion beam of an element for compensating a grain boundary of the semiconductor layer and an ion beam of an inert gas at the same time as doping a layer with impurity ions. 5. A step of forming a gate insulating film on a semiconductor layer, a step of forming a gate electrode on the gate insulating film, and forming a source region and a drain region in the semiconductor layer by a self-alignment technique using the gate electrode. Therefore, the semiconductor layer is doped with an impurity by irradiating an ion shower with a mixed gas of a gas containing a p-type or n-type impurity, a gas containing an element compensating for the grain boundary of the semiconductor layer, and an inert gas. A method of manufacturing a semiconductor device, comprising: 6. A step of forming a gate insulating film on a semiconductor layer, a step of forming a gate electrode on the gate insulating film, and forming a source region and a drain region in the semiconductor layer by a self-alignment technique using the gate electrode. Therefore, high-frequency energy is applied to a gas containing p-type or n-type impurities diluted with a mixed gas of a gas containing an element compensating the grain boundaries of the semiconductor layer and an inert gas to generate plasma, A method of manufacturing a semiconductor device, comprising the steps of irradiating the semiconductor layer with an ion beam of an element that compensates for grain boundaries of the semiconductor layer and an ion beam of an inert gas at the same time as performing doping with impurity ions. 7. The method of manufacturing a semiconductor device according to claim 5, wherein a gate electrode made of the same material as the semiconductor layer is formed. 8. The method of manufacturing a semiconductor device according to claim 5, wherein the gate electrode made of a metal material is formed. 9. The method of manufacturing a semiconductor device according to claim 5, further comprising the step of forming a semiconductor layer on an insulating substrate. 10. A display device using the semiconductor device manufactured by the method for manufacturing a semiconductor device according to claim 9 as a pixel driving element.