JPH0845902A - Dry etching method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a dry etching method in which a Si-based material layer such as a polycrystalline silicon layer has a constant cross-sectional taper shape regardless of the position on the substrate to be etched. [Structure] A mixed gas of a halogen-based gas other than F-based gas and O ₂ gas is used as an etching gas, and a rare gas, O ₂ Alternatively, a gas added with N ₂ is used. [Effect] Since the deposition amount of the side wall protection film 5a of the polycrystalline silicon pattern 3a near the center of the substrate to be etched and the deposition amount of the side wall protection film 5b of the peripheral pattern 3b are almost the same, the taper angle α and β is also the same.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dry etching method, and more particularly to a dry etching method for polycrystalline silicon or the like applied to electrodes and wirings of semiconductor devices.

[0002]

2. Description of the Related Art As the design rules of semiconductor devices such as LSI are miniaturized from half micron to quarter micron, the demand for microfabrication technology such as dry etching is becoming more severe. The improvement in processing accuracy in dry etching is usually directed to anisotropic etching in which the pattern conversion difference from the mask layer is eliminated as much as possible. However, depending on the device structure, the cross-section of the lower layer wiring may be intentionally taper-shaped, such as a polycrystalline silicon electrode / wiring used as an internal electrode / wiring of a highly integrated CCD image pickup device or the like. This is because the step coverage of the upper layer wiring is improved and the etching residue at the time of patterning the upper layer wiring is reduced by forming the cross section of the lower layer wiring and the insulating layer formed on the lower layer wiring in a forward tapered shape. Such a residue is called a stringer residue because it is formed like a string along the side surface of the step, and unless the stringer residue is removed, an accident such as a short circuit or a poor insulation occurs between the adjacent wirings. Usually, this stringer residue is removed by over-etching the upper wiring for a long time, but under the fine design rules, damage to the lower insulating layer and the upper wiring cannot be prevented. A problem such as a pattern conversion difference due to side etching occurs again.

Cross-section of electrodes and wiring made of polycrystalline silicon
Patterning to form a forward tapered shape and
Then SiO₂Using a mask, HBr / O₂Mixed gas
Disclosed in Japanese Patent Application Laid-Open No. 2-89310.
Have been. This is because the polycrystalline
Oxidize the exposed surface of the insulator, and ionize this oxide film.
While remaining only on the side of the pattern where there is little
By etching while gradually expanding the mask width,
Achieving taper etching. With side wall protective film
The oxide film, etc. that contributes to taper etching by
SiO by oxidation of recon_xIn addition to the etching gas
Reaction product of SiBr_xAnd SiO _xBr_yAttached
Or the attached reaction products are further oxidized.
In fact, these are mixed and used as a side wall protective film.
Is exerting the function of.

In the dry etching method in which the reaction product is deposited on the substrate to be etched to control the processed shape, the temperature of the substrate to be etched is precisely controlled to make the amount of the reaction product deposited constant. This is very important. Therefore, in general, the vapor pressure of the reaction product is lowered to promote the adhesion of the reaction product onto the substrate to be etched, so that the substrate to be etched is cooled. In the publication mentioned above,
Although there is no description about the temperature control of the substrate to be etched, generally, the cooling of the substrate to be etched is performed by bringing the substrate to be etched into close contact with the electrostatic chuck or a mechanical clamper on the substrate stage cooled by the circulation of the refrigerant, and further heating the substrate. In order to improve the exchange efficiency, a heat conducting gas such as He flows out from the central portion of the upper surface of the substrate stage toward the back surface of the substrate to be etched. The heat-conducting gas is discharged from the peripheral portion of the substrate to be etched into the etching chamber along minute radial grooves formed on the upper surface of the substrate stage, and is then exhausted to the outside of the chamber.

[0005]

In the above-described method for cooling a substrate to be etched, the in-plane distribution of the substrate temperature is not necessarily uniform, and the amount of reaction products deposited varies, so that the processed shape of the layer to be etched is also changed. The taper angle may not be constant. This problem is shown in FIG. 4 and FIG.
This will be described with reference to (a) and (b).

FIG. 4 shows the diametrical position of the substrate to be etched on the horizontal axis, and the temperature of the substrate to be etched at that position on the left vertical axis. The vertical axis on the right side shows the amount of reaction products deposited. As shown in this figure, the temperature of the substrate to be etched tends to be lower in the central part and higher in the peripheral part. It is considered that this is due to the temperature distribution of the substrate stage and the flow velocity distribution of the heat transfer gas. As a result, the amount of reaction products deposited is large in the central portion of the substrate to be etched and small in the peripheral portion.

Problems in patterning a polycrystalline silicon layer on a substrate to be etched having such temperature distribution and deposition characteristics of reaction products will be described with reference to FIGS. 5 (a) and 5 (b). . As an etching sample, Fig. 5 (a)
As shown in FIG. 3, a base insulating layer 2 having an ONO (oxide film / nitride film / oxide film) structure and a polycrystalline silicon layer 3 are formed on a semiconductor substrate 1 such as Si, and a resist mask 4 is formed. The left side of the drawing shows the vicinity of the central portion of the substrate to be etched, and the right side shows the peripheral portion of the substrate to be etched. The thickness of each material layer and the width of the resist mask 4 are the same in the central portion and the peripheral portion.

When this polycrystalline silicon layer 3 is patterned by using a parallel plate type RIE apparatus with HBr / O ₂ mixed gas, the result shown in FIG. 5B is obtained. That is, the side wall protective film 5a adheres much in the vicinity of the central portion, and the side wall protective film 5b adheres little in the peripheral portion. As a result, the taper angle β of the polycrystalline silicon pattern 3b in the peripheral portion becomes larger than the taper angle α of the polycrystalline silicon pattern 3a in the vicinity of the central portion. As a matter of course, the widths of the lower surfaces of the polycrystalline silicon patterns 3a and 3b at the boundary with the insulating layer 2 are different. This difference in the width of the polycrystalline silicon pattern causes, for example, fluctuations in the channel length under the gate electrode, fluctuations in the step coverage of the upper wiring formed on the gate electrode through the upper insulating layer, and the degree of stringer residue generation. Results in These fluctuation factors are unacceptable problems especially in recent highly integrated semiconductor devices using a large-diameter substrate.

Therefore, an object of the present invention is to provide a dry etching method for patterning a layer to be etched made of a Si-based material layer so that its cross section has a forward taper shape.
It is an object of the present invention to provide a dry etching method that can obtain a uniform taper angle and an arbitrary taper angle regardless of the location of the substrate to be etched.

Another object of the present invention is to improve the step coverage of the upper wiring formed on the lower wiring composed of the Si-based material layer via the upper insulating layer, and to prevent the occurrence of stringer residue and to be etched. Regardless of the board location,
An object of the present invention is to provide a dry etching method capable of manufacturing a highly reliable semiconductor device. Other problems of the present invention will be made clear by the description of the present specification and the description of the accompanying drawings.

[0011]

The dry etching method of the present invention was devised in order to solve the above-mentioned problems, and a heat-conducting gas flows out from the cooled upper surface of the substrate stage toward the lower surface of the substrate to be etched. By controlling the temperature of the substrate to be etched, the mixed gas containing halogen-based gas other than F-based gas and O-based gas can be used for Si.
A dry etching method for patterning a system material layer, characterized in that the heat conduction gas contains a rare gas and an O system gas.

In the dry etching method of the present invention, the temperature of the substrate to be etched is controlled by flowing out the heat conducting gas from the cooled upper surface of the substrate stage toward the lower surface of the substrate to be etched, and the temperature other than that of the F type is used. A dry etching method for patterning a Si-based material layer with a mixed gas containing a halogen-based gas and an O-based gas, wherein the heat-conducting gas contains a rare gas and an N-based gas.

The dry etching method of the present invention can be applied to patterning of Si-based material layers such as single crystal silicon, polycrystalline silicon, amorphous silicon, refractory metal silicide and refractory metal layer polycide.

The halogen-based gas other than F-based gas in the present invention means Cl-based gas, Br-based gas and I-based gas, and examples thereof include Cl ₂ , HCl, BCl ₃ and CC.
l ₄ , CHCl ₃ , Br ₂ , HBr, BBr ₃ , CBr
₄ , CHBr ₃ , HI and interhalogen compounds such as IBr and ICl ₃ and halogenated sulfur-based gases such as S ₂ Cl ₂ and S ₂ Br ₂ may be used alone or in combination.

An example of the O-based gas in the present invention is as follows.
Then O₂, O₃And NO_xEtc. can be used alone or in combination.
Can be used. An example of the N-based gas in the present invention is
N ₂, NH₃And N₂H_FourEtc. alone or in a mixture
Can be used. Further, as the rare gas in the present invention, H
e, Ne, Ar, Kr and Xe alone or in combination
Can be used.

[0016]

The point of the present invention is to contribute to the forward taper etching as the side wall protective film by using the gas containing the rare gas and the O-based gas or the gas containing the rare gas and the N-based gas as the heat conduction gas. This is to promote the formation of oxides such as SiO _x , SiO _x Br _y and SiO _x N _{y in the} peripheral portion of the substrate to be etched.

Conventionally, the heat-conducting gas flowing out from the cooled upper surface of the substrate stage toward the lower surface of the substrate to be etched has been used only for increasing the heat exchange efficiency between the substrate stage and the substrate to be etched. In the present invention,
In addition to this function, the O-based gas and the N-based gas are added to give the function of forming the sidewall protective film. The heat-conducting gas flowing into the etching chamber from the peripheral portion of the lower surface of the substrate to be etched circulates to the peripheral portion of the upper surface of the substrate to be etched, and oxidizes or nitrides the exposed surface of the etched layer together with the mixed gas for etching. Alternatively, S attached as a reaction product of etching
iBr _x and SiO _x Br _y are further oxidized or nitrided to promote and strengthen the formation of the side wall protective film in this portion.
The description so far has been made on the case where a mixed gas of Br-based gas and O-based gas is used as an etching gas, but a mixed gas of Cl-based gas / O-based gas or I-based gas / O-based gas is used as an etching gas. The same applies in the case where the reaction product is SiCl
₄ and SiO _x Cl _y , SiI _x and SiO _x I _y are the only differences.

On the other hand, the heat-conducting gas does not reach the central portion of the substrate to be etched as much as the peripheral portion because of the distance limitation. Therefore, the heat-conducting gas almost contributes to the formation of the side wall protective film in the central portion of the substrate to be etched. do not do. Due to these effects, the formation amount of the side wall protective film in the central portion and the peripheral portion of the substrate to be etched is made uniform, and the Si-based material layer is patterned with a uniform taper angle. Further, the taper angle can be arbitrarily controlled by controlling the ratio of the O-based gas or the N-based gas in the heat transfer gas.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Specific embodiments of the present invention will be described below with reference to the accompanying drawings. First, a configuration example of a substrate bias application type ECR plasma etching apparatus used in the following examples will be described with reference to schematic sectional views shown in FIGS.

2.4 generated by a magnetron (not shown)
A microwave of 5 GHz is guided by a microwave waveguide 11 into a bell jar 13 made of a dielectric material such as quartz, and is 0.0875T generated by a solenoid coil 12 here.
ECR plasma is generated by its interaction with the magnetic field.
The lower part of the bell jar 13 is an etching chamber, and the substrate to be etched 15 placed on the substrate stage 17 is set in the etching chamber. In FIG. 3A, details of an etching gas introduction nozzle, a vacuum pump, a substrate bias power source, and the like are omitted.

FIG. 3B is an enlarged schematic sectional view of the substrate stage 17 portion described above. Although not shown, a cooling pipe may be incorporated in the substrate stage 17 and a cooling medium such as ethanol may be circulated to control the cooling to a desired temperature. An electrostatic chuck 18 is provided on the upper surface of the substrate stage 17, and the substrate to be etched 1 is mechanically clamped together with the mechanical clamper 14.
5 is tightly fixed to the substrate stage 17. The clamper 14 may be released after the substrate 15 to be etched is electrostatically attracted. The heat conduction gas introduction hole 16 is provided in the central shaft portions of the substrate stage 17 and the electrostatic chuck 18, and the heat conduction gas is caused to flow toward the back surface of the substrate 15 to be etched. The flow of the heat conductive gas is discharged from the peripheral edge of the substrate to be etched 15 into the etching chamber via fine grooves (not shown) formed radially on the upper surface of the electrostatic chuck 18. Yes, this flow is schematically indicated by an arrow in FIG. 3 (b). In FIG. 3B, the electrostatic chuck 1
8 to the upper surface of the substrate stage 17 and the substrate 1 to be etched
Although the lower surfaces of 5 are shown separated for the sake of explanation, there are practically no gaps.

Example 1 This example is an example in which a heat conductive gas containing He and O ₂ is used to pattern electrodes and wirings made of polycrystalline silicon in a forward tapered shape, and this is shown in FIGS. b) and FIG. 2
Will be described with reference to.

The etching sample shown in FIG.
This is the same as FIG. 5A referred to in the description of the conventional technique,
Is omitted, but for a semiconductor substrate made of 8 inch diameter Si
It is a sample composed of more. This etching sample is
A substrate bias application type E shown in FIG.
It is kept on the substrate stage 17 of the CR plasma etching system.
Of the polycrystalline silicon layer 3 under the following conditions as an example.
Patterning was performed. 100 as heat transfer gas
He-20% maintained at 0 Pa (~ 8 Torr) pressure
O₂To improve the responsiveness of the temperature control of the substrate to be etched.
I have HBr 120 sccm O₂ 2 sccm Gas pressure 0.7 Pa Microwave power 600 W (2.45 GHz) RF bias power 35 W (2 MHz) Substrate stage temperature 0 ° C. Substrate stage temperature controls the central part of the substrate stage 17.
Is the temperature. The principle of this etching process is basically the same as the conventional example.
However, in the present embodiment, the group to be etched is
Heat released from the periphery of the plate 15 into the etching chamber
O in conduction gas ₂But reaches the periphery of the substrate to be etched 15.
It is different from the conventional example in that it reaches.

O increased around the substrate 15 to be etched.
₂ concentration is obtained by oxidizing the exposed surface of the polycrystalline silicon layer 3
In addition to forming an O _x film, etching reaction product SiBr _x
Further, the side wall protective film 5 formed by adhering a part of SiO _x Br _y or SiO _x Br _y is further oxidized to improve ion irradiation resistance. Due to these effects, the adhesion amount of the sidewall protective film 5b in the peripheral portion of the substrate to be etched 15 is enhanced, and the substrate to be etched 15 is etched.
The adhesion amount of the side wall protective film 5a at the central portion was almost the same. This state will be described with reference to FIG.

In FIG. 2, as in FIG. 4, the diametrical position of the substrate to be etched is plotted on the horizontal axis, and the temperature of the substrate to be etched at that position is plotted on the left vertical axis. In addition, the vertical axis on the right side shows the deposition amount of the side wall protective film. As shown in this figure, the temperature of the substrate to be etched tends to be lower in the central portion and higher in the peripheral portion, as in the prior art. Therefore, the amount of reaction products deposited is originally large in the central portion of the substrate to be etched and small in the peripheral portion, but in the present embodiment, due to the effect of the increased O ₂ concentration in the peripheral portion of the substrate to be etched, the side wall is reduced. The deposition amount of the protective film is almost constant regardless of the position.

As a result, the pattern cross section of the polycrystalline silicon after the dry etching is completed is as shown in FIG.
The taper angle β of the polycrystalline silicon pattern 3b in the peripheral portion of the etched substrate 15 and the taper angle α of the polycrystalline silicon pattern 3a in the central portion of the etched substrate 15 are substantially the same.

According to this embodiment, the conventional heat transfer gas is
By adding 0% O ₂ , it became possible to form a polycrystalline silicon pattern having a uniform taper angle over the entire surface of the large-diameter substrate to be etched. The amount of O ₂ added to the heat transfer gas was 20% in this embodiment.
However, the optimum addition amount may be appropriately used depending on the substrate stage temperature and the composition of the etching mixed gas.

Example 2 This example is an example in which a heat conductive gas containing He and N ₂ was used and the same etching sample as in Example 1 was patterned in a forward taper shape. b) and FIG. 2 will be described.

The etching sample shown in FIG.
A substrate bias application type E shown in FIG.
It is kept on the substrate stage 17 of the CR plasma etching system.
Of the polycrystalline silicon layer 3 under the following conditions as an example.
Patterning was performed. 100 as heat transfer gas
He-20% maintained at 0 Pa (~ 8 Torr) pressure
N₂To improve the responsiveness of the temperature control of the substrate to be etched.
I have HBr 120 sccm O₂ 2 sccm Gas pressure 0.7 Pa Microwave power 600 W (2.45 GHz) RF bias power 35 W (2 MHz) Substrate stage temperature 0 ° C. Substrate stage temperature controls the central part of the substrate stage 17.
Is the temperature. The principle of this etching process is basically the same as the conventional example
However, in the present embodiment, the group to be etched is
Heat released from the periphery of the plate 15 into the etching chamber
N in conduction gas ₂But reaches the periphery of the substrate to be etched 15.
It is different from the conventional example in that it reaches.

The N ₂ selectively released to the periphery of the substrate 15 to be etched is the etching reaction products SiBr _x and S.
The side wall protective film 5 formed by adhering a part of iO _x Br _y is nitrided to improve ion irradiation resistance. As a result, the remaining amount of the side wall protective film 5b in the peripheral portion of the substrate to be etched 15 was increased, and became almost the same as the amount of the side wall protective film 5a attached to the central portion of the substrate to be etched 15. This state will be described again with reference to FIG.

In FIG. 2, as in FIG. 4, the diametrical position of the substrate to be etched is plotted on the horizontal axis, and the substrate temperature to be etched at that position is plotted on the left vertical axis. In addition, the vertical axis on the right side shows the deposition amount of the side wall protective film. As shown in this figure, the temperature of the substrate to be etched tends to be lower in the central part and higher in the peripheral part, as in the prior art. Therefore, the deposition amount of the reaction product is originally large in the central portion of the substrate to be etched and is small in the peripheral portion, but in the present embodiment, the effect of N ₂ supplied to the peripheral portion of the substrate to be etched protects the side wall. The deposition amount of the film is almost constant regardless of the position.

As a result, the pattern cross section of the polycrystalline silicon after the completion of dry etching is as shown in FIG.
The taper angle β of the polycrystalline silicon pattern 3b in the peripheral portion of the etched substrate 15 and the taper angle α of the polycrystalline silicon pattern 3a in the central portion of the etched substrate 15 are substantially the same.

According to this embodiment, the conventional heat transfer gas is
By adding 0% N ₂ , it became possible to form a polycrystalline silicon pattern having a uniform taper angle over the entire surface of the large-diameter substrate to be etched. The amount of N ₂ added in the heat transfer gas was 20% in this embodiment.
However, the optimum addition amount may be appropriately used depending on the substrate stage temperature and the composition of the etching mixed gas.

Although the present invention has been described with reference to the two examples, the present invention is not limited to these examples.

For example, HBr has been described as a representative of halogen-based gas other than F-based gas.
Other than Br-based gas, Br-based gas, and I-based gas may be used. A mixed gas of a halogen-based gas and an O-based gas other than the F-based gas can be suitably used in the present invention for patterning the Si-based material layer while depositing a part of the reaction product on the substrate to be etched. .

In the above embodiment, HBr / O ₂ was used as the mixed gas used for etching, but this mixing ratio is increased or decreased according to the desired taper angle. That is, if the mixing ratio of O ₂ is increased, the taper angle becomes small, that is, becomes gentle, and if the mixing ratio is decreased, the taper angle becomes large, that is, anisotropic etching approaches. In addition, the addition ratio of the O-based gas or the N-based gas in the heat transfer gas may be increased or decreased according to the mixing ratio so that a uniform taper angle can be obtained.

Although He was used as the rare gas in the heat conduction gas, other rare gases such as Kr, Ar, Ne and Xe may be used. Among them, the photon energy of the plasma emission spectrum due to the neutral excited species of Xe is as small as 8.4 eV, and thus the light irradiation damage given to the substrate to be etched is the smallest. This is, for example, 21.2 eV for He, Ar
Is 11.6 eV and Kr has a photon energy of 10.0 eV. For example, since the band gap energy of silicon oxide frequently used for the gate insulating film is 8.8 eV, the kind of rare gas may be selected according to the constituent material layer of the substrate to be etched.

Polycrystalline silicon has been exemplified as the Si-based material layer, but it may have a laminated structure of single-crystal silicon, amorphous silicon, silicide of other refractory metal such as W, Mo, or polycide of refractory metal layer. Good. When the refractory metal silicide layer is the surface of the layer to be etched, providing an antireflection layer such as SiON is effective for fine patterning of the gate electrode / electrode.

Although the substrate bias application type ECR plasma etching apparatus is used as the etching apparatus, a parallel plate type RIE apparatus or a magnetron RIE apparatus may be used. If a high-density plasma etching device such as a helicon wave plasma etching device, a TCP etching device, an ICP etching device, etc. is used, further uniformity in the substrate to be etched, low damage, high etching rate, etc. can be expected.

[0040]

As is apparent from the above description, according to the present invention, in a dry etching method of patterning a layer to be etched made of a Si-based material layer so that its cross section has a forward taper shape, a large diameter layer is to be coated. It has become possible to provide a dry etching method that can obtain a uniform and arbitrary taper angle regardless of the position on the substrate to be etched even if it is an etching substrate.

Further, according to the present invention, there is provided a dry etching method which improves the step coverage of the upper wiring formed on the lower wiring composed of the Si-based material layer through the upper insulating layer and does not generate a stringer residue. It is now possible to provide. These effects can be uniformly enjoyed regardless of the central portion or the peripheral portion of the large-diameter substrate to be etched.

The dry etching method of the present invention has a great effect particularly when patterning fine gate electrodes / wirings in the sub-half micron class, and has high integration and high reliability in MIS type semiconductor devices and CCD image pickup devices. The significance of contributing to sexualization is great.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view illustrating a dry etching method according to embodiments 1 and 2 to which the present invention is applied in the order of steps, in which (a) shows a resist mask formed on a layer to be etched made of polycrystalline silicon. The state (b) is a state in which the etching target layer made of polycrystalline silicon is patterned into a tapered cross section.

FIG. 2 is a diagram showing a temperature of a substrate to be etched and a deposition amount of a sidewall protective film in a dry etching method according to the first and second embodiments to which the present invention is applied, with respect to a position in a diameter direction of the substrate to be etched.

FIG. 3 is a diagram showing an example of the configuration of a dry etching apparatus applied to the dry etching methods of Examples 1 and 2 to which the present invention is applied, in which (a) is a schematic sectional view thereof,
(B) is an enlarged schematic sectional view of a substrate stage portion.

FIG. 4 is a diagram showing a temperature of a substrate to be etched and a deposition amount of a side wall protective film in a conventional dry etching method with respect to a position in a diameter direction of the substrate to be etched.

5A and 5B are schematic cross-sectional views illustrating a conventional dry etching method in the order of steps, FIG. 5A is a state in which a resist mask is formed on a layer to be etched made of polycrystalline silicon, and FIG. The layer to be etched is patterned into a tapered cross section.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Insulating Layer 3 Polycrystalline Silicon Layer 3a, 3b Polycrystalline Silicon Pattern 4 Resist Mask 5a, 5b Sidewall Protective Film 11 Microwave Waveguide 12 Solenoid Coil 13 Belleger 14 Clamper 15 Etched Substrate 16 Thermal Conduction Gas Introduction Hole 17 Substrate stage 18 Electrostatic chuck

Claims (4)

[Claims] 1. The temperature of the substrate to be etched is controlled by flowing out a heat conductive gas from the cooled upper surface of the substrate stage to the lower surface of the substrate to be etched, and halogen-based gas other than F-based gas and O-based gas are also controlled. A dry etching method for patterning a Si-based material layer with a mixed gas containing: a heat-conductive gas containing a rare gas and an O-based gas. 2. The temperature of the substrate to be etched is controlled by flowing out a heat-conducting gas from the cooled upper surface of the substrate stage to the lower surface of the substrate to be etched, and halogen-based gas other than F-based gas and O-based gas are also controlled. A dry etching method for patterning a Si-based material layer with a mixed gas containing, wherein the heat conduction gas contains a rare gas and an N-based gas. 3. The dry etching method according to claim 1, wherein the processed cross section of the Si-based material layer is patterned into a forward tapered shape. 4. The Si-based material layer is at least one selected from the group consisting of single crystal silicon, polycrystalline silicon, amorphous silicon, refractory metal silicide, and refractory metal layer polycide. The plasma etching method according to claim 1 or 2.