JPH0846485A - Digital filter - Google Patents

Abstract

PURPOSE:To provide a filter output with the lump up/down data added to the burst-state input digital signal without increasing the capacity of a memory in the digital filter equipped with a shift resistor and a memory which stores the data to be used as a filter output. CONSTITUTION:The digital filter is provided with an address signal generation circuit 5 operated by a burst timing signal and generating an address signal which reads out the data adequate to prepare lump up signals and lump down signals before and after the burst signal from d memory 2 and an address signal switching circuit 6 operated by a burst timing signal and outputting the address signal generated by the circuit 5 instead of the n-bit data kept in a shift resistor 1 to the memory 2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital filter.

[0002]

2. Description of the Related Art An example of a digital filter is disclosed in, for example, Japanese Patent Laid-Open No. 3-150917. The digital filter had a predetermined shift register, a predetermined memory and a predetermined counter. Here, the predetermined shift register shifts the input digital signal bit by bit by the first clock signal and holds it for n bits. Further, the predetermined memory stores data used as a filter output, and further, n-bit data held by the shift register is inputted as an address signal and a storage corresponding to the address signal is stored. It was a memory that outputs data according to the output instruction signal from the counter. Further, the predetermined counter outputs a signal (output instruction signal) for instructing the memory to output data. Specifically, a signal generated by counting a second clock signal having a cycle of s times (s is an integer of 2 or more) of the first clock signal is output to the memory as an output instruction signal. It was output.

[0003]

By the way, in the processing by the digital filter, there are many cases in which a burst-shaped input digital signal is processed. In that case, the output signal from the digital filter is preferably a signal in which the ramp-up portion is added to the front side of the burst signal portion and the ramp-down portion is added to the rear side. This is to prevent the spectrum of the signal from being broadened if the signal is suddenly cut off.
Then, in order to use the filter output having the ramp-up portion and the ramp-down portion with, for example, the above-described conventional digital filter, a configuration described below with reference to FIGS. 4 and 5 is conceivable. Here, FIG. 4 is a block diagram of a digital filter. In FIG. 4, 1 is the above-mentioned n-bit scale shift register, 2 is the above-mentioned memory, 3 is the above-mentioned counter, and 4 is a D / A for converting the data output from the memory 2 into an analog signal and outputting it as a filter A converter, CLK1 is the first clock signal,
CLK2 is the second clock signal. In addition, FIG.
FIG. 6 is a waveform diagram showing an example of a relationship among a first clock signal, an input digital signal, a burst timing signal, and a filter output. Here, the burst timing signal is
As shown in FIG. 5, a signal S for indicating that the burst signal portion S _A is to be input or that the burst signal portion S _A has ended in the input digital signal.
It is _B. The burst timing signal S _B can be prepared by various methods depending on the signal processing form, such as when the input digital signal is processed each time it is created or when it is prepared in advance according to the standard of the input digital signal. . Further, S _{RU of} FIG. 5 is a ramp-up unit in the filter output, and S _RD is a ramp-down unit in the filter output.

As shown in FIG. 4, a total of (n + 1) bits of the signal line of n bits from the shift register 1 and the signal line of the burst timing signal constitutes the address signal of the memory 2, and this memory also By setting 2 to a capacity read by (n + 1) bits, a filter output having a ramp-up portion and a ramp-down portion can be obtained. In this configuration, when there is no input of the burst timing signal S _B (0 level), the memory 2 is substantially addressed by the n-bit data held by the shift register 1. On the other hand, when the burst timing signal S _B is input (1 level), the memory 2 is addressed by (n + 1) -bit data. Here, the burst timing signal S
_By setting the address when _B is input to a predetermined address, it is possible to read from the memory 2 the data that is suitable for creating the ramp-up portion and the ramp-down portion among the data stored in the memory 2. As a result, the desired filter output can be obtained.

However, in the case of the structure described with reference to FIG. 4, there is a problem that the capacity of the memory 2 needs to be doubled by one bit for increasing the address signal of the memory 2. In particular, when the bit number n of the shift register is large, even if one bit is added to the address signal, the amount of increase in the memory becomes extremely large. That is, for example, when changing from 2 bits to 3 bits, 2
^{Since 3} −2 ² = 4, it is sufficient to increase the memory for 4 addresses, but if changing from 8 bits to 9 bits, for example, 2
⁹ the memory increased 256 address component because -2 ⁸ = 512-256 = 256.

[0006]

According to the first invention of this application, therefore, an input digital signal is input and is used as an n-bit scale shift register controlled by a first clock signal and a filter output. A digital filter comprising: a memory for storing n-bit data held by a shift register as an address signal and outputting stored data corresponding to the address signal in response to an output instruction signal. It is characterized by having the following (a) and (b).

(A) An address signal generation circuit which operates according to a burst timing signal and generates an address signal for reading data suitable for generating a ramp-up signal and a ramp-down signal before and after the burst signal from the memory.

(B) An address signal switching circuit which operates according to the burst timing signal and outputs the address signal generated by the address signal generating circuit to the memory instead of the n-bit data held by the shift register.

According to the second invention of this application, the data used as the filter output is stored, the input digital signal is input as the address signal, and the stored data corresponding to the address signal is used as the output instruction signal. In a digital filter with a memory that outputs according to
A digital signal processing unit to which a burst timing signal, a first clock signal and the input digital signal are input, and when the burst timing signal is not input, the input digital signal is input to the first clock signal. Each time it arrives, it shifts by one bit and outputs n bits as an address signal to the memory. When the burst timing signal is input, a ramp up signal and a ramp down signal before and after the burst signal are created. It is characterized by comprising a digital signal processing section for generating an n-bit address signal for reading out data suitable for the above purpose from the memory and outputting this to the memory.

[0010]

According to the first and second inventions, the following effects can be obtained. A large amount of data used as a filter output is stored in the memory, and these data also include data suitable for use in generating a ramp-up signal and a ramp-down signal (which can be used). Then, in the first and second inventions, when the burst timing signal arrives, an address signal for reading out the data suitable for creating the ramp-up signal and the ramp-down signal among the data stored in the memory is provided. Specially created,
The memory can be accessed by this address signal. Therefore, the ramp-up signal and the ramp-down signal can be created by diverting the data in the memory without increasing the capacity of the memory.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the first invention and the second invention of this application will be described below with reference to the drawings. In each drawing used for explanation, the same components as those of the conventional components are denoted by the same reference numerals.

1. First Embodiment of the Invention FIG. 1 is a diagram showing a configuration of a digital filter according to an embodiment of the first invention. The details of the digital filter of the first embodiment of the present invention will be described later, but a predetermined shift register 1, a predetermined memory 2, an output instruction signal generator 3, a D / A converter 4, and a predetermined address signal generation circuit 5. And a predetermined address signal switching circuit 6.

Here, the shift register 1 is an n-bit scale shift register controlled by the first clock signal CLK1 and stores the first bit of the input digital signal in the first stage thereof and then the first clock signal. The input digital signal is shifted bit by bit according to the signal. The output of each stage of the shift register 1 is connected to the address signal switching circuit 6. The number of stages n of the shift register 1 can be any number according to the design of the digital filter.

The memory 2 is a memory that stores a large number of data used as a filter output. Moreover, either the n-bit data held by the shift register 1 or the data generated by the address signal generation circuit 5 is input as an address signal, and the stored data corresponding to this address signal is responded to the output instruction signal S _OUT . Is a memory for outputting.

The output instruction signal S _OUT is generated by the output instruction signal generation unit 3 and input to the memory 2. The output instruction signal generator 3 can have any suitable configuration according to the design of the digital filter. In this embodiment, the first
Of the second clock signal CLK2 whose cycle is s times (s is, for example, a number of 2 or more) of the clock signal CLK1 of the counter 3 and the output signal of the counter 3 is output.
_OUT . That is, the oversampling technology is adopted. Of course, various modifications can be made, such as using the second clock signal CLK2 as the output instruction signal as it is, or using a signal that has the same period as the first clock signal but is out of phase.

The D / A converter 4 converts predetermined data output from the memory 2 into an analog signal. The D / A converter 4 is not particularly limited and may be a conventionally known one. If the filter output may be a digital signal, the D / A converter 4 may not be provided.

The address signal generation circuit 5 operates according to the burst timing signal S _B already described with reference to FIG. 5, and among the data stored in the memory 2,
An n-bit address signal for reading data suitable for generating a ramp-up signal and a ramp-down signal before and after the burst signal is generated. The address signal generating circuit 5 can be composed of, for example, a monitor bit of the burst timing signal S _B , a ROM in which a predetermined address signal is stored, and a predetermined logic circuit section. Here, the burst timing signal monitoring bit is a bit for monitoring whether the input burst timing signal S _B corresponds to the ramp-up portion or the ramp-down portion. For example, when one burst timing signal S _B is input, this monitor bit becomes “1”, and when the burst timing signal S _B is input next, this monitor bit becomes “0”.
Return to and configure this to be repeated. Then
It can be determined that the burst timing signal S _B with the monitoring bit changed to “1” corresponds to the ramp-up part, while the burst timing signal S _B with the monitoring bit changed to “0” corresponds to the ramp-down part. You can judge that you do. Further, the ROM storing the address signal has a plurality of addresses (details will be described later) here so that the data in the memory 2 can be accessed so that a ramp-up portion and a ramp-down portion having a desired inclination can be formed. The signals are written in order. Further, the predetermined logic circuit means here that the address signals are sequentially output from the ROM storing the address signals every time the first clock signal CLK1 is input while the burst timing signal S _B is input. It is read out and output to the address signal switching circuit 6. In this embodiment, FIG.
As described above, since the pulse width of the burst timing signal S _{B is set to} the width of 4 pulses of the first clock signal CLK1, the ROM stores four address signals as the address signal for the ramp-up section, Moreover, four address signals are stored as the address signals for the ramp-down section. The RO in which the address signal is stored in this way
Control of whether to read the ramp-up address signal or the ramp-down address signal from M may be performed by checking the burst timing signal monitoring bit. If the ramp-up and ramp-down may be reversed in inclination, the order of reading the address signals from the ROM may be reversed. In that case, the address signal prepared in the ROM is 8 above.
One half or four is enough. Of course, the number of address signals described here is just an example.

The address signal switching circuit 6 operates by a burst timing signal and outputs the address signal generated by the address signal generating circuit 5 to the memory instead of the n-bit data held by the shift register. It is a thing. Such an address switching circuit 6 can be configured by any suitable one. For example, a switching element that is turned on when the burst timing signal S _B is not input is provided between the significant output of the shift register 1 and the address signal input terminal of the memory 2, On the other hand, a switching element that is turned on when the burst timing signal S _B is input between the address signal generation circuit 5 and the address signal input terminal of the memory 2 (the switching element is turned on by the opposite logic to the switching element). A switching element).

The operation of the digital filter of the first embodiment of the present invention will be described below.

The address signal generating circuit 5 is in a non-operating state when the burst timing signal S _B is not input thereto. Further, the address signal switching circuit 6 enables the space between the shift register 1 and the address signal input terminal of the memory 2 when the burst timing signal S _B is not input thereto. Therefore, in this case, the n-bit data held in the shift register 1 is output to the memory 2 as an address signal. On the other hand, when the burst timing signal S _B is input, the address signal generation circuit 5 sequentially outputs a predetermined address signal according to the first clock signal. Further, the address signal switching circuit 6 enables between the address signal generating circuit 6 and the address signal input terminal of the memory 2. Therefore, the address signal generated in the address signal generating circuit 6 is stored in the memory 2
Is output to. Further, the memory 2 outputs the data corresponding to the address signal input from either the shift register 1 or the address signal generation circuit 5 to the output instruction signal S.
Output to D / A converter 4 according to _OUT . D / A converter 4
Converts this data sent from the memory 2 into an analog signal and outputs it as a filter output. The filter output thus formed has the ramp-up data and the ramp-down data added thereto, as shown in FIG.

2. Second Embodiment of the Second Invention FIG. 2 is a diagram showing a configuration of a digital filter of the second invention, and FIG. 3 is an operational flow chart for explaining a digital signal processing unit provided in a digital filter of the second invention. In the digital filter of the second invention, the shift register 1, the address signal generating circuit 5 and the address signal switching circuit 6 provided in the digital filter of the first invention are replaced with a predetermined digital signal processing section 7. is there. The digital signal processing unit 7 receives the burst timing signal S _B , the first clock signal CLK1 and the input digital signal. When the burst timing signal is not input, the input digital signal is converted into the first clock signal. When the burst timing signal is input, a ramp-up signal and a ramp-down signal before and after the burst signal are generated. In order to read the appropriate data from the memory 2, an n-bit address signal is generated and output to the memory 2. Such a digital signal processing unit 7 can be configured by, for example, a digital signal processor (DSP). Less than,
The operation of the digital signal processing section 7 will be described with reference to FIG.

The digital signal processing section 7 first inputs n-bit data from the input digital signal (see FIG. 3).
Step S1). In addition, the digital signal processing unit 7
It is determined whether or not the burst timing signal S _B has been input (step S2). When it is determined that the burst timing signal has been input, an n-bit address signal for reading the data suitable for creating the ramp-up signal and the ramp-down signal before and after the burst signal from the memory 2 is generated ( Step S3). Next, the digital signal processing unit 7 determines that the burst timing signal is input, the n-bit address signal generated in step S3, and determines that the burst timing signal is not input, the step 1
The n-bit data input in step 2 is sent to the memory 2 (step S4). Next, the digital signal processing unit 7
The n-bit data input in step S1 is shifted by 1 bit (step S5), and then 1 bit of new data is input from the input digital signal (step S).
6). Then, the processing of S2 to S6 is repeated as necessary for data processing.

The operations of the memory 2, the output instruction signal generator 3 and the D / A converter 4 are the same as those in the first aspect of the present invention, and will not be repeated here.

[0024]

As is apparent from the above description, according to the digital filter of the first invention of this application, a predetermined shift register, a predetermined memory, a predetermined address signal generation circuit and a predetermined address signal switching circuit are provided. Equipped. Further, according to the digital filter of the second invention, it is provided with a predetermined memory and a predetermined digital signal processing section.
Therefore, according to the first and second inventions, it is possible to specially create the address signal for reading the data suitable for creating the ramp-up signal and the ramp-down signal among the data stored in the memory. , And the memory can be accessed by this address signal. For this reason,
A burst signal in which ramp-up / down data is added to a burst-shaped input digital signal can be created without increasing the memory capacity.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of an embodiment of the first invention.

FIG. 2 is an explanatory diagram of an embodiment of the second invention.

FIG. 3 is an explanatory diagram of a digital signal processing unit in the second invention.

FIG. 4 is a diagram for explaining a problem.

FIG. 5 is an explanatory diagram of a conventional technique and the present invention.

[Explanation of symbols]

 1: shift register 2: memory 3: output instruction signal generator (counter) 4: D / A converter 5: address signal generator circuit 6: address signal switching circuit CLK1: first clock signal

Claims (2)

[Claims] 1. An n-bit shift register which receives an input digital signal and is controlled by a first clock signal and has a scale of n bits and data used as a filter output and which is held by the shift register. In a digital filter having a memory for inputting the data of as an address signal and outputting the stored data corresponding to the address signal according to an output instruction signal, the digital filter operates by a burst timing signal and ramps up and down before and after the burst signal. Address signal generating circuit for generating an address signal for reading data suitable for generating a signal and a ramp-down signal from the memory; and an address signal generated by the address signal generating circuit, which operates by the burst timing signal. Is stored in the shift register. Digital filter is characterized in that comprises an address signal switching circuit for outputting to the memory instead of bets data. 2. A digital filter comprising a memory for storing data used as a filter output, inputting an input digital signal as an address signal, and outputting stored data corresponding to the address signal in response to an output instruction signal. In the digital signal processing unit to which the burst timing signal, the first clock signal and the input digital signal are input, and when the burst timing signal is not input, the input digital signal is input to the first clock Each time a signal arrives, it shifts by one bit and outputs n bits as an address signal to the memory. When the burst timing signal is input, a ramp-up signal and a ramp-down signal before and after the burst signal are input. Suitable data for creating A digital filter comprising a digital signal processing unit for generating an n-bit address signal for reading from a memory and outputting this to the memory.