JPH0846492A - Phase synchronizing circuit - Google Patents

Abstract

PURPOSE:To detect the cycle of an input signal, to shorten the processing time of the detection result and to speed the operation. CONSTITUTION:The circuit is provided with plural 1st delay amplification elements DA11-DA1 (2n) connected vertically which delays an input signal IN by one cycle by receiving the input signal IN at the input terminal of the front stage. It is provided with a delay circuit 1 of an input signal cycle detection means which detects the output change state of these delay amplification elements and detects each cycle of the input signal IN and outputs cycle detection signals PD 1-PDn corresponding to each cycle, latch circuit 2, and edge detection circuit 3. And it is provided with an oscillation circuit 4 which responses to the cycle detection signals PD1-PDn, a ring oscillator including the 2nd delay amplification elements which is a half the 1st one corresponding to one cycle. Thus, the oscillation frequency can be controlled by detecting each cycle of the input signal in the shortest time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop circuit, and more particularly to a phase locked loop circuit composed of a digital circuit.

[0002]

2. Description of the Related Art A digital PLL circuit is well known as a phase-locked loop circuit composed of digital circuits. FIG. 5 shows an example of a conventional phase locked loop circuit of this type.

This phase synchronization circuit is composed of a plurality of NAND gates and outputs a up pulse UP when the phase of the output signal OUT is delayed with respect to the input signal IN, and outputs a down pulse DWN when the phase of the output signal OUT is advanced. And a ring oscillator type oscillation circuit 8 formed of a plurality of stages of amplifiers and a switch circuit including an inverter circuit and changing the frequency by switching the number of stages of the amplifiers by the switch circuit, and an up pulse PU is input. As the oscillating frequency increases, down pulse DW
An up / down counter 7 for switching the number of amplifier stages of the oscillation circuit 8 so that the oscillation frequency becomes low when N is input.
It is configured to have and.

In this phase locked loop circuit, 1 of the input signal IN is input.
The phase comparison with the output signal OUT is performed for each cycle, and the up pulse UP or the down pulse is output, and the number of stages of the amplifier of the oscillation circuit 8 is switched by these pulses to change the oscillation frequency. OUT
And the phase is synchronized.

[0005]

In this conventional phase locked loop circuit, the phase comparison is performed every cycle of the input signal IN, and the number of amplifier stages of the oscillation circuit 8 is switched to change the oscillation frequency. , The oscillation frequency is the input signal IN
There is a problem in that a plurality of cycles of the input signal IN are required to reach a frequency at which the output signal OUT and the output signal OUT are synchronized with each other, which makes high-speed operation difficult.

An object of the present invention is to provide a phase locked loop circuit capable of speeding up the operation.

[0007]

The phase-locked loop circuit of the present invention is connected in cascade to each other to receive the input signal at the input end of the frontmost stage, and delay the input signal for at least one cycle at the output end of the last stage. An input having a plurality of first delay elements for detecting the output change states of the plurality of first delay elements to detect each cycle of the input signal and outputting a cycle detection signal corresponding to each cycle. Signal period detection means,
Inverter circuits for inverting and amplifying the signal level at the input end, and a plurality of second delays connected in cascade to each other to connect the input end of the frontmost stage to the output end of the inverter circuit and delay the output signal of the inverter circuit for a predetermined time. An element and a plurality of switches, one end of which is correspondingly connected to the output terminals of the plurality of second delay elements and the other end of which is connected to the input terminal of the inverter circuit, and which are turned on and off in response to the cycle detection signal. And a ring oscillator type oscillation circuit that oscillates in a cycle corresponding to the cycle of the input signal.

Further, the first and second delay elements are delay elements having an amplifying function, and the input signal cycle detecting means are cascaded to each other to receive the input signal at the input terminal at the frontmost stage, and the last stage. A delay circuit provided with a plurality of first delay elements for delaying the input signal by at least one cycle at the output terminal of the output circuit, and a level of an output signal of a predetermined delay element among the plurality of first delay elements. A latch circuit having a plurality of flip-flops for latching and outputting at a falling edge (or rising edge) of the input signal, and a level of output signals of the plurality of flip-flops closer to the input end side of the input signal. Edge detection circuit that outputs the cycle detection signal that makes only the bit corresponding to the point that changes from low level to high level (or high level to low level) sequentially from the Bets are comprise constituting configured as an on the active level of the bit corresponding switch circuit only of the period detecting signal of the plurality of switch circuits of the oscillation circuit.

Further, instead of the oscillator circuit, a plurality of second delay elements corresponding to the plurality of first delay elements and connected in series with each other to receive an input signal at the input terminal of the frontmost stage, and a plurality of these second delay elements. 1 of the output signals of the second delay element
A second delay circuit provided with a switch circuit for selecting and outputting one of the first and second delay elements according to the cycle detection signal. The ratio of the numbers of the corresponding first and second delay elements is M: N (M, N). Are both natural numbers other than 0), and the delay time of the output signal (OUT) of the second delay circuit with respect to the input signal is configured as N / M of the cycle of this input signal.

[0010]

In the present invention, the cycle is detected for each cycle of the input signal, and a ring oscillator type oscillating circuit including a number of delay elements corresponding to the cycle is formed to oscillate, or the input signal is oscillated. Since the output signals of the delay elements of the number corresponding to the above-described cycle of the second delay circuit to be delayed are selected and output, each cycle is synchronized with the cycle in the shortest time at which the cycle can be detected. Therefore, it is possible to obtain a signal that has been processed, and thus to speed up the operation.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In this embodiment, an inverter IV is connected in cascade and receives an input signal IN at its input terminal on the front side.
11, IV12 and a plurality of cascade-connected input terminals IN which receive the input signal IN via the inverters IV11 and IV12 at the frontmost stage and which delay and amplify the input signal IN by at least one cycle at the output stage at the last stage. A delay circuit 1 including first delay amplification elements DA11 to DA1 (2n);
The plurality of delay amplification elements DA11 to DA1 (2
n), even-numbered delay amplifying elements DA12, DA1
4 to DA1 (2n) output signals (D1, D2, to, D
n) latches each level at the falling edge of the input signal IN and outputs the flip-flops FF1 and FF.
2, to FFn, and a plurality of flip-flops FF1, FF2 to FFn of the latch circuit 2.
Of the output signals Q1, Q2, ... Qn of the input signal IN
Of the cycle detection signals PD1 and PD, in which only the bit corresponding to the point changed from the low level to the high level is sequentially detected from the side closer to the input terminal side (that is, Q1) and becomes the active level.
2, to PDn, an edge detection circuit 3, an inverter IV41 for inverting and amplifying the signal level of the input terminal, and an input terminal IV4 connected in cascade to each other.
A plurality of second delay amplification elements DA41, DA42, ~ DA4n connected to the output terminal of No. 1 and sequentially delaying the output signal of the inverter IV41 and transmitted to the subsequent stage side, and one end of these delay amplification elements DA1, DA2, ~ DAn. A plurality of switch circuits SW1, SW2, ... SWn are connected corresponding to the respective output terminals and the other ends thereof are both connected to the input terminal of the inverter IV41 and turned on / off according to the corresponding bits of the cycle detection signals PD1, PD2, PDn. A ring oscillator type oscillation circuit 4 that oscillates in a cycle corresponding to the cycle of the input signal IN is provided.

In this embodiment, the delay circuit 1, the latch circuit 2 and the edge detection circuit 3 form an input signal cycle detecting means and oscillate every half of one cycle of the input signal IN. The first and second delay amplification elements DA1 are arranged so that the level of the output signal OUT of the circuit 4 is inverted.
1-DA1 (2n), DA41-DA4n are all made equal, and the ring oscillator is ½ of the number of the first delay amplification elements that can obtain the delay amount for one cycle of the input signal IN. Are formed.

A concrete circuit example of the edge detection circuit 3 is shown in FIG. In this way, AND gates AG1-
It can be formed by AGn and OR gates (OG1 to OG3, ...).

Next, the operation of this embodiment will be described.
FIG. 3 is a diagram showing waveforms and levels of signals at various parts for explaining the operation of this embodiment.

When the input signal IN is input to the input terminal of the delay circuit 1, the output signals (hereinafter, simply referred to as delay signals) D1, D2, Dn of the delay circuit 1 are the input signals IN,
The signal is sequentially delayed by the delay amount d. The levels of the delay signals D1, D2, to Dn are changed to the respective flip-flops FF1 and F of the latch circuit 2 at the falling edge of the input signal IN.
When it is taken into F2 to FFn, the delay signal D1 falls to a high level "1" after the time d, and the delay signals D2 and D3 fall to a high level "1" after the times 2d and 3d.
Since the delay signals D4, D5, D6 are "0" in the previous low level period and the delay signals D7, D8 are "1" in the high level period one cycle before, each flip-flop The levels of output signals (hereinafter referred to as latch outputs) Qj (j = 1 to n, the same applies hereinafter) of FF1, FF2, ... FFn are (1, 1, 1, 0, 0, 0, 1, 1, ...). . The point at which the level of the latch output Qj changes from "0" to "1" is the state immediately before the falling edge one cycle before the input signal IN, so that this point can be taken as the cycle of the input signal IN. .

The edge detection circuit 3 outputs the latch output Qj.
Detects a point whose level has changed from "0" to "1", and outputs a period detection signal PDj that sets only the bit (PD7 in the example of FIG. 3) corresponding to the point to the active level "1". By turning on the switch circuit SW7 of the oscillation circuit 4 corresponding to the bit PD7 of the cycle detection signal PDj, the number of 1/2 of the first delay amplification element that can obtain the delay time of one cycle of the input signal IN. Since the ring oscillator including the second delay amplifying element is formed, the oscillation cycle of the oscillation circuit 4 in which the ring oscillator is formed is substantially equal to the cycle of the input signal IN. That is, the oscillation output (OUT) synchronized with the input signal IN can be obtained.

As described above, when the falling edge of the input signal IN is the end of one cycle of the input signal IN, the oscillation cycle of the oscillator circuit 4 can be controlled at the fastest timing at which the cycle can be detected. Therefore, the operation speed of the phase locked loop can be increased.

In this embodiment, the end of one cycle of the input signal IN is the falling edge, but it may be the falling edge. In this case, the detection point of the cycle by the edge detection circuit is the point changed from "1" to "0".

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

This embodiment corresponds to each of the plurality of first delay amplification elements DA11 to DA1 (2n) of the delay circuit 1 of the first embodiment instead of the oscillation circuit 4 of the first embodiment. A plurality of second delay amplification elements DA51 to DA51 connected in cascade and receiving the input signal IN at the input terminal of the frontmost stage.
DA5n and the plurality of second delay amplification elements DA51
To one of the output signals of DA5n to the period detection signal PD
1 to PDn to select and output the switch circuit SW1
To SWn, the second delay circuit 5 is provided, and since the inverter (IV41) required in the oscillation circuit 4 in the first embodiment is not particularly required in the second delay circuit 5, Instead of the delay circuit 1 of the embodiment, a delay circuit 1a having a circuit configuration not including the inverters IV11 and IV12 is used.

In this embodiment, the input signal cycle detection means (delay circuit 1a, latch circuit 2, edge detection circuit 3) having the same configuration as that of the first embodiment is used to input the cycle detection signals PD1 to PDn. Since the configuration is such that the output signals of the second delay amplification elements DA51 to DA5n of the delay circuit 5 that delays and amplifies the signal IN are selected and output,
In the same manner as in the first embodiment, the operation speed can be increased, and the ratio of the number of corresponding delay amplification elements of the first and second delay circuits 1a and 5 is M to N (M and N are 0). Other than a natural number), the input signal I of the output signal OUT
The delay time for N is N / N of the cycle of the input signal IN.
There is an advantage that it can be set to M (when the cycle of the input signal IN changes, N / M of the changed cycle). In the case of FIG. 4, since N / M = 1/2, the output signal OU
T is a delay time of 1/2 of the cycle of the input signal IN.

In these embodiments, the first and second delay amplification elements DA11 to DA1 (2n) and DA51 to DA forming the first and second delay circuits 1, 1a and 5 are used.
5n may be a simple delay element that does not have an amplifying function. However, when a signal is delayed by delay elements connected in cascade in multiple stages, the signal waveform gradually becomes distorted. As in the example, it is desirable to have an amplifying function to shape the waveform.

[0025]

As described above, the present invention detects the cycle of each cycle of an input signal, forms a ring oscillator type oscillation circuit including a number of delay elements corresponding to the cycle, and oscillates the oscillation circuit. Or by detecting and outputting the output signals of the number of delay elements corresponding to the above-described cycle of the second delay circuit that delays the input signal, the cycle can be detected for each cycle of the input signal. Since a signal synchronized with the cycle can be obtained in the shortest time, there is an effect that the operation can be speeded up.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific example of an edge detection circuit of the embodiment shown in FIG.

FIG. 3 is a diagram showing waveforms and levels of signals at respective parts for explaining the operation of the embodiment shown in FIG.

FIG. 4 is a circuit diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing an example of a conventional phase synchronization circuit.

[Explanation of symbols]

1, 1a Delay circuit 2 Latch circuit 3 Edge detection circuit 4 Oscillation circuit 5 Delay circuit 6 Phase comparator 7 Up / down counter 8 Oscillation circuit AG1 to AGn AND gates DA12 to DA1 (2n), DA41 to DA4n, DA
51-DA5n Delay amplification element FF1-FFn Flip-flop IV11, IV12, IV41 Inverter OG1-OGn OR gate SW1-SWn switch circuit

Claims (6)

[Claims] 1. A plurality of first delay elements, which are cascade-connected to each other and receive an input signal at an input end of a frontmost stage thereof and delay the input signal by at least one cycle at an output end of a final stage thereof. The input signal cycle detecting means for detecting the cycle of the output change of the first delay element to detect the cycles of the input signal and outputting cycle detection signals corresponding to the cycles, and the signal level at the input end. Inverter circuits for inverting and amplifying, a plurality of second delay elements connected in cascade with each other, connecting the input end of the frontmost stage to the output end of the inverter circuit and delaying the output signal of the inverter circuit for a predetermined time, and one end thereof. A plurality of switch circuits that are correspondingly connected to the output terminals of the plurality of second delay elements, and the other ends of which are both connected to the input terminal of the inverter circuit to turn on and off in response to the cycle detection signal. And a ring oscillator type oscillating circuit which oscillates in a cycle corresponding to the cycle of the input signal. 2. The phase locked loop circuit according to claim 1, wherein the first and second delay elements are delay elements having an amplifying function. 3. A plurality of first input signal cycle detecting means are connected in cascade to each other to receive an input signal at an input end of the frontmost stage thereof and to delay the input signal by at least one cycle at an output end of the final stage. And a plurality of delay circuits each of which outputs a level of an output signal of a predetermined delay element of the plurality of first delay elements at a falling edge (or a rising edge) of the input signal. And a level of output signals of the plurality of flip-flops are sequentially detected from the side closer to the input end side of the input signal to shift from low level to high level (or high level to low level). And an edge detection circuit that outputs a cycle detection signal that sets only the bit corresponding to the changed point to an active level, The phase locked loop circuit according to claim 1, wherein only the switch circuit corresponding to the active level bit of the cycle detection signal is turned on. 4. The delay amounts of the first and second delay elements are made equal to each other, and 1
1/2 of the number of first delay elements that can obtain the delay amount for one cycle
2. The phase locked loop circuit according to claim 1, wherein one of the plurality of switch circuits is turned on so that a ring oscillator including the number of the second delay elements is formed. 5. A plurality of second delay elements, which correspond to the plurality of first delay elements and are connected in cascade to each other and receive an input signal at an input terminal at the frontmost stage, instead of the oscillation circuit, and a plurality of these delay elements. 2. The phase locked loop circuit according to claim 1, further comprising a switch circuit that selects and outputs one of the output signals of the second delay element according to the cycle detection signal. 6. The input of the output signal (OUT) of the second delay circuit, wherein the ratio of the number of corresponding first and second delay elements is M to N (M and N are both natural numbers other than 0). 6. The phase locked loop circuit according to claim 5, wherein the delay time for the signal is N / M of the cycle of the input signal.