JPH0850165A - Scan pass circuit - Google Patents

Abstract

PURPOSE:To reduce a scan test pattern, and suppress the number of input and output terminals for test at minimum by providing such a constitution that a plurality of shift resisters forming a plurality of branched scan chains, which are arranged in parallel to each other, perform inspections of circuit groups having the same function, respectively. CONSTITUTION:A scan pass is formed of a plurality of shift resisters 1a-1c, a scan input S1N is formed of only one scan input terminal 4, and a plurality of scan outputs Sout2-Soutn are outputted from scan output terminals 5b-5c corresponding to the shift resisters 1b-1c, respectively. The output of the shift resister 1a is commonly inputted to the shift resisters 1b-1c. The shift operation in the shift resisters 1a-1c is performed by a clock signal (CLOCK) inputted from a clock input terminal 3 after a scan mode switching control terminal 2 is laid into the active state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a scanpath circuit for facilitating test.

[0002]

2. Description of the Related Art A flip-flop in an integrated circuit is connected like a shift register to form a scan path, a test signal is input from an external terminal, and a combinational logic (Combinat) is formed.
The system that facilitates the test by reading the operation result of the ionalLogic) circuit is called the scan path method.

FIGS. 3 to 5 are block diagrams each showing an example of a conventional scan path circuit.

3 to 5, reference numerals 1a to 1c denote a plurality of shift registers # 1 to 1 constituting a scan path circuit.
#N, 2 is a scan mode switching control terminal for controlling switching between the normal mode and the scan mode, 3 is a clock input terminal for shifting data of the shift register, 4 is a scan input terminal, 5 is a scan output terminal. is there. Note that the shift registers # 1 to #n are also called scan registers.

The scan path circuit of FIG. 4 is provided with a plurality of scan input terminals 4a to 4c and a plurality of scan output terminals 5a to 5c corresponding to the plurality of shift registers # 1 to #n. 3 is different from the configuration of FIG.

FIG. 5 shows a configuration of a scan path circuit proposed in Japanese Patent Application Laid-Open No. Hei 1-217278, in which a demultiplexer 8 for distributing data input from a scan input terminal 4 to each shift register, A multiplexer 9 for selecting one of the outputs of the shift register and outputting it to the scan output terminal 5;
And a plurality of shift registers # 1 to # 3 based on the signal input to
A decoder 7 is added to generate a signal that puts only one of #n into the shift mode.

Next, the operation of these three conventional scan path circuits will be described.

In FIG. 3, during normal operation, the scan mode switching control terminal 2 is made inactive and the shift registers 1a to 1c are used as the only registers separated from the scan path. At this time, the clock input terminal 3, the scan input terminal 4, and the scan output terminal 5 are not used.

However, when the system clock and the scan clock are shared, the clock input terminal 3 is used even during normal operation.

During the scan path test, the scan mode switching control terminal 2 is activated, serial data is input from the scan input terminal 4 to the shift register, and the data is written into the shift register.
The data held in the shift register is output from the scan output terminal 5 as serial data by the shift operation.

As described above, data can be arbitrarily written in and read from the shift registers # 1 to #n in the scan path circuit, so that the test is facilitated. That is, during the scan path test, input data can be supplied to the combination logic circuit (not shown) and the output of the combination logic circuit can be read through the shift register # 1 of FIG. Each input to is controllable and each output of the combinational logic circuit is observable, which facilitates the testability of the integrated circuit.

In the scan path circuit of FIG. 4, basically the same operation as that of the scan path circuit of FIG. 3 is performed, but in FIG. 4, a chain of scan path circuits (also referred to as a "scan chain"). 3 in that a plurality of scan input terminals 4a to 4c and a plurality of scan output terminals 5a to 5c are provided corresponding to a plurality of chains.

In the scan path circuit shown in FIG. 4, when data is set in, for example, the shift register # 1 and the data of the other shift registers # 2 to #n are held as they are during the test, only the scan mode switching control terminal 2a is connected. Clock input terminal 3 with clock and data as active
When it is desired to input data from the scan input terminal 4a and read only the data of the shift register # 1, only the scan mode switching control terminal 2a is activated and a clock is supplied to the clock input terminal 3 to thereby provide a scan output terminal. The data of the shift register # 1 is output from 5a.

Next, in the scan path circuit of FIG. 5, the number of input / output terminals and the number of test terminals such as scan mode switching control terminals provided in the scan path circuit of FIG. 4 are reduced. The purpose is to reduce the number of input terminals and output terminals one by one, and the signals are distributed to a plurality of shift registers by the demultiplexer 8 and the multiplexer 9.

In the scan path circuit of FIG. 5, since the coded shift mode switching input signal is decoded by the decoder 7 and used, the number of terminals is reduced and a multiplexer is provided for each terminal for writing and reading data. Since it is distributed to a plurality of shift registers by the demultiplexer, data can be written and read for each shift register.

[0016]

Among the conventional scan path circuits, the configuration shown in FIG. 3 has a problem that the number of test patterns increases because all shift registers are serially connected. Even when reading data from only one shift register, shift clocks must be input from the clock input terminal 3 by the number of stages of all shift registers, and the number of test patterns increases, resulting in poor efficiency.

Further, the scan path circuit of FIG. 4 has a structure in which a plurality of chains are arranged in parallel, and data can be written and read individually for each shift register as compared with the structure of FIG. Therefore, it has an advantage that an efficient test pattern can be created and the number of serial test patterns is reduced, but there is a very important problem that the number of test terminals increases.

The scan path circuit shown in FIG.
Although the configuration is similar to that described above, since there is only one data input / output terminal, many serial test patterns are required, and additional circuits such as decoders, demultiplexers, and multiplexers are required. There are problems such as an increase in circuit scale and an increase in hardware overhead.

Therefore, an object of the present invention is to solve the above-mentioned problems, reduce the number of scan path test patterns, and
An object of the present invention is to provide a scan path circuit in which the number of test input / output terminals is minimized.

[0020]

To achieve the above object, the present invention provides a plurality of scan data input from a single scan input terminal after serially passing through a scan chain composed of at least one shift register. A scan path circuit, characterized in that the scan path circuit is configured to branch to a scan chain, and output from a plurality of scan output terminals respectively connected to a plurality of shift registers arranged in parallel with each other in a number equal to the number of branches. provide.

Further, in the scan path circuit of the present invention, the plurality of branched scan chains are formed.
It is characterized in that a plurality of shift registers arranged in parallel with each other are configured to inspect circuits having the same function.

In a preferred embodiment of the scanpath circuit of the present invention, a single scan input terminal, a plurality of scan output terminals, a plurality of shift registers forming the scanpath circuit, and a shift operation of the shift registers. And a scan mode switching control terminal, and in the scan mode, the scan data input from the one scan input terminal passes through at least one shift register and is then arranged in parallel with each other. To the plurality of shift registers in the final stage, the plurality of scan chains branch to a plurality of scan chains, the plurality of scan output terminals are connected to the outputs of the plurality of shift registers in the last stage, and the plurality of scan registers are arranged in parallel with each other Each shift register is a combinational logic circuit unit of the same function. It is configured to perform the list.

[0023]

According to the present invention, the scan input terminal of the scan path circuit is serially input to the shift register as one terminal, is connected to the shift registers arranged in parallel with each other in the subsequent stage of the shift register, and the scan output terminal is connected to the shift output terminal. By configuring to have multiple, it is possible to reduce the number of test patterns and significantly reduce the number of test terminals,
Furthermore, it enables a parallel test of the test target circuit group.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of an embodiment of a scan path circuit according to the present invention. In FIG. 1, terminals and circuit elements having the same functions as those in FIGS. 3 to 5 are given the same reference numerals.

As shown in FIG. 1, in this embodiment,
The scan path is composed of a plurality of shift registers # 1 to #n, and the scan input SIN is the scan input terminal 4
A plurality of scan outputs Sout2 to Soutn are output from the scan output terminals 5b to 5c corresponding to the shift registers # 2 to #n, respectively.

The output of the shift register # 1 is commonly input to a plurality of shift registers # 2 to #n.

The shift operation in the shift registers # 1 to #n is executed by the clock signal (CLOCK) input from the clock input terminal 3 with the scan mode switching control terminal 2 in the active state.

In this embodiment, with this configuration,
When there are a plurality of circuit groups having the same function to be tested in the integrated circuit (referred to as "same function group" and preferably composed of combinational logic circuit units), a shift register # is used for each test of the same function group. Two
The shift register #n can be used to test the same functional group in parallel.

FIG. 2 shows the same function group B in the integrated circuit.
When a plurality of # 1 to B # n-1 are present, a configuration example of the scan chain when performing the scan path test according to the present embodiment will be shown. In the figure, the same function groups B # 1 to B # n
-1 is a group of independent circuits having the same function, and data is set and read through the shift registers # 2 to #n, respectively. The circuit group A is a circuit group (preferably a combinational logic circuit unit) having a different function from the circuit groups B # 1 to B # n-1, and is connected via a shift register # 1 connected to the scan input SIN. Data setting and reading are performed.

In this embodiment, the number of test patterns required for the scan path is (the number of patterns in the shift register # 1) + (the number of patterns in the shift register # 2).

On the other hand, the number of test patterns in the case of the conventional example of FIG. 3 is (the number of patterns of the shift register # 1).
+ (The number of patterns to the shift register # 2) + ... + (the number of patterns to the shift register #n)
Compared with the conventional example of FIG. 3, the number of test patterns is greatly reduced.

For example, if the shift registers # 1 to #n are 10
(N = 10), and one shift register is 100
In the case of being composed of a chain of flip-flops, the conventional example of FIG. 2 requires a basic test pattern of 10 × 100, but in the present embodiment, it is significantly reduced to 2 × 100, and the test time is reduced. Greatly contributes to shortening

Further, in comparison with the conventional example of FIG. 4 in which all scan paths are configured in parallel, in this embodiment, both the scan input terminal and the scan mode switching control terminal are reduced to one, and the test is performed. This has the effect of minimizing the number of terminals for use (input terminals). Further, in comparison with the conventional example of FIG. 5, the present embodiment does not require circuits such as a demultiplexer and a multiplexer.

Although the present invention has been described with reference to the above embodiments, the present invention is not limited to the above embodiments and includes various embodiments according to the principle of the present invention. For example, a mode in which a plurality of shift registers are serially connected after the shift register # 1 and branches to a plurality of shift registers arranged in parallel at the final stage in which outputs are respectively connected to a plurality of scan output terminals, Alternatively, while the shift register # 1 and the final-stage shift register arranged in parallel are reached, a branch from the output of one shift register to a plurality of shift registers arranged in parallel may be provided in multiple stages on the way. The present invention also includes such a configuration.

[0036]

As described above, according to the present invention, the scan input terminal of the scan path circuit is a single terminal and is serially input to the shift register, and the output of the shift register branches at the subsequent stage and is parallel to each other. , The number of test patterns and the number of test terminals can be effectively reduced.

Further, according to the present invention, in the integrated circuit, it is possible to simultaneously test in parallel by using a plurality of shift registers arranged in parallel with respect to the same functional group to be tested, The number of test patterns is greatly reduced and the test time is shortened.

Further, according to the present invention, it is possible to reduce the number of test terminals and to perform a parallel test of functional blocks to be tested inside the integrated circuit without increasing the circuit scale.

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a scanpath circuit according to the present invention.

FIG. 2 is a diagram showing a configuration of a scan chain in the scan path circuit according to the present invention.

FIG. 3 is a diagram showing an example of a conventional scan path circuit.

FIG. 4 is a diagram showing another example of a conventional scan path circuit.

FIG. 5 is a diagram showing still another example of the conventional scan path circuit.

[Explanation of symbols]

 1a to 1c Shift register constituting scan circuit 2, 2a to 2c Scan mode switching control terminal 3 Clock input terminal 4, 4a to 4c Scan input terminal 5, 5a to 5c Scan output terminal 6 Shift mode switching input terminal 7 Decoder 8 Multiplexer 9 Multiplexer

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/822 H01L 27/04 T

Claims (3)

[Claims] 1. A scan data input from a single scan input terminal serially passes through a scan chain consisting of at least one shift register, and then branches into a plurality of scan chains, which is equal to the number of branches and parallel to each other. A scan path circuit configured to output from a plurality of scan output terminals respectively connected to a plurality of arranged shift registers. 2. A plurality of shift registers, which are arranged in parallel with each other and which form a plurality of branched scan chains, are configured to inspect circuits having the same function, respectively. The described scanpath circuit. 3. A scan input terminal, a plurality of scan output terminals, a plurality of shift registers forming a scan path circuit, a clock input terminal for shifting the shift registers, and a scan mode switching control terminal. In the scan mode, the scan data input from the one scan input terminal passes through at least one shift register, and then reaches the plurality of final-stage shift registers arranged in parallel with each other. The plurality of scan registers are branched into a plurality of scan chains, the plurality of scan output terminals are respectively connected to the outputs of the plurality of shift registers at the final stage, and the plurality of shift registers arranged in parallel with each other are combined logic circuit units having the same function. A scanpath circuit configured to perform a test.