JPH0850563A - Memory test circuit - Google Patents

Abstract

(57) [Summary] [Purpose] By providing a gate for supplying a test signal to an address line, test data is written to all the memories at once. An address decoder 1 for decoding an address and outputting a signal to a corresponding address line 11, an OR gate 2 provided for inputting a test signal for each address line 11, and an output signal for each OR gate 2 And a write enable signal (WE), and a logical operation of a signal on the address line 11 and a write enable signal (WE) The data from the data bus is stored or the output enable signal (OE) based on the result
And a multiplexer 5 for inputting the address, selecting one from the plurality of memory units 4 and outputting the data read from the same memory unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a static RAM.
(Random Access Memory) Test circuit for detecting stuck-at fault.

[0002]

2. Description of the Related Art For example, eight memory cells are used as one memory unit for a memory cell composed of a static RAM circuit in a gate array or the like, and an address is given to write or read one byte of data for each memory unit. May be provided as follows. At this time, a memory test is performed to confirm whether each memory cell operates normally.

The memory cell of the static RAM utilizes the operation of the bi-stable state by the flip-flop circuit. Normally, when a flip-flop circuit fails,
It is fixed to either "0" or "1". So-called
It often results in simple stuck-at failure.

By the way, conventionally, "0" or "1" is written in all the memory cells in the previous stage of the memory test, all the memory cells are read in the latter stage, and the written "0" or "1", A memory test for checking a "1" or "0" stuck-at fault has been carried out by the method of collating the data read from the memory cell.

The memory test will be described in detail.
FIG. 4 shows an embodiment of a conventional memory test circuit. 1
Decodes the supplied address and the corresponding address line 11
It is an address decoder that outputs a signal to. 4 is a signal of the address line 11 and a write enable signal (WE),
It is a plurality of memory units that store data from the data bus or output the read data to the data bus based on the supplied output enable signal (OE).

The operation of the test circuit of FIG. 4 will be described with reference to the time chart of FIG. A control unit (not shown) that controls the test circuit of this memory supplies an address to the address decoder 1. The address decoder 1 uses, for example, address 1, ...
.., signal "1" on address line 11 in the order of address k, etc.
('0') is output for a predetermined period. In synchronization with the predetermined period, "0"("1") is applied to the data bus and WE is set to "1"("0"). Therefore, "0"("1") is written in all the memory cells within this predetermined period (the above is the previous stage).

Next, a controller (not shown) supplies an address to the address decoder 1. Based on the supplied address, the address decoder 1 outputs a signal "1"("0") to the address line 11 in the order of, for example, address 1, ..., Address k for a predetermined period. The OE is set to '1'('0') in synchronization with the predetermined period. Therefore, all the memory cells are read within this predetermined period, and the read data is output to the data bus. Therefore, the value "0" written in the memory cell during this predetermined period.
If ('1') and the read data on the data bus are collated and matched, it is determined that there is no '1'('0') stuck-at fault (the above is the latter stage).

However, along with the demand for multi-functionalization of the system and the commercialization of large-scale gate arrays, the number of memory cells formed inside the gate array tends to increase. Therefore, in a large-scale memory test, the total time of the above-mentioned writing (pre-stage) and reading (post-stage) increases, which causes a problem of increasing the cost of the memory test.

[0009]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and by writing data to all memory cells in a short time, the time in the preceding stage can be shortened and the memory test time can be almost halved. It is an object to provide a memory test circuit.

[0010]

In order to achieve the above object, as a first structure, an address decoder for decoding a supplied address and outputting a signal to a corresponding address line, and a signal for the address line and writing A plurality of memories that store or read data based on the permission signal and the supplied output permission signal, and a selection unit that selects one memory from the memories connected based on the address and outputs the data read from the memory In a test circuit for a memory consisting of: a gate unit for supplying a test signal provided for each address line; an output signal and a write enable signal for each gate unit; and calculating the results in a corresponding memory. And a write control section for giving.

As a second configuration, an address decoder which decodes the supplied address and outputs a signal to a corresponding address line, a signal on the address line, a write enable signal, and the supplied output enable signal are input. Along with
In a memory test circuit including a plurality of memories connected to a data bus, the test circuit is an OR gate for inputting a test signal provided for each address line.

[0012]

With the above configuration, when writing "0" or "1" to all the memory cells before the memory test, the test signal "1" is supplied to the terminal of the OR gate of the gate section. Thus, in the first configuration, when the write enable signal '1' is applied to the NAND gate of the write control unit, the write enable signal is, for example,
When the write enable terminal of the memory unit is set to low active, all the memory cells are set to the writable state, so that the data existing on the data bus is written to all the memory cells at once. Further, by supplying the test signal '1' to the terminal of the OR gate of the gate unit, in the second configuration, for example, when the write enable terminal of the memory unit is set to low active, all the memories are Since the cells are in the selected state at the same time, by supplying the write enable signal to a predetermined terminal, the write enable signal puts all the memory cells in the write state. Is written. The above-mentioned OR gate, NAND
The same operation is achieved by constructing a relative circuit in which the gate is replaced with a different gate such as an AND gate, supplying a corresponding logic signal, and setting the memory write permission condition or the selection condition as required. it can.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A memory test circuit according to the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram of an embodiment of a memory test circuit according to the present invention. 1 decodes the supplied address and the corresponding address line 11
It is an address decoder that outputs a signal to. Reference numeral 2 is a gate provided for inputting a test signal for each address line 11, for example, an OR gate. Reference numeral 3 is a write control unit composed of, for example, a NAND gate, which calculates an output signal of each OR gate 2 and a write enable signal (WE) and gives the result to each memory unit. Reference numeral 4 captures and stores the data on the data bus based on the result of the logical operation of the signal of the address line 11 and the write enable signal (WE), or outputs a predetermined logical value to the output enable signal (OE). A plurality of memory units that read out stored data to a data bus when supplied with a signal. A multiplexer (selection unit) 5 selects one memory unit from the plurality of connected memory units 4 based on the address and outputs the data read from the memory unit.

The operation of the memory test circuit according to the present invention will be described with reference to FIGS. A control unit (not shown) that controls the test circuit of this memory supplies a logical value of "1" as a test signal, supplies a logical value of "1" to the write enable signal (WE), and outputs "1" to the data bus. 0 '
Give ('1'). Therefore, in this state, all the memory units 4 are in the write enable state, and "0"("1") is written in all the memory cells at once (the above is the previous stage).

Next, a control unit (not shown) supplies a required address to the address decoder 1. Based on the supplied address, the address decoder 1 determines the address line 11 in the order of address 1, ...
For example, the logical value "1" is output during a predetermined period. The output permission signal (OE) is set to, for example, “1” in synchronization with the predetermined period. Therefore, all the memory cells are read within this predetermined period. At this time, the multiplexer 5 to which the required address is input selects one memory unit from the plurality of connected memory units 4,
The data read from the memory unit 4 is output.
Further, the logic value “0” (“1”) written in the memory cell during this predetermined period can be collated with the read data to check the “1” (“0”) stuck-at fault. Yes (the latter is the latter stage).

FIG. 3 is a block diagram of another embodiment of the memory test circuit according to the present invention. Reference numeral 1 is an address decoder which decodes the supplied address and outputs a predetermined signal to the corresponding address line 11, and 2 is the address line 1
A gate provided for each 1 for inputting a test signal, for example, an OR gate, 4 has a write enable signal (WE) and an output enable signal (OE) with the output of the OR gate 2 as a selection signal. And a plurality of memory units connected to the data bus.

The operation is almost the same as the embodiment of FIG.
Only the differences will be explained. All the memory units 4 which are configured to be high active so that the input signal of the selection terminal is selected by "1" are brought into the selected state at the same time when the logic value "1" is supplied to the test signal. At this time, when a signal having a predetermined logical value is supplied to the write enable signal (WE), the data “1” (“0”) on the data bus is written to all the memory units 4 at once (the above is the previous stage).

Next, when the test signal is set to the logical value "0" and the required address is supplied, for example, the address 1 ...
.., the logical value "1" is output to the address line 11 in order of the address k, etc. for a predetermined period. The logical value of the output enable signal (OE) is set to "1" in synchronization with the predetermined period.
Therefore, all the memory cells are read within this predetermined period, and the read data is output onto the data bus.
In the above description, a circuit using an OR gate and a NAND gate is used, but it is configured by a relative circuit in which another gate such as an AND gate is replaced, and a corresponding logic signal is supplied, and a write permission condition of the memory unit, Alternatively,
By setting the selection condition to have a required logical value, for example, the embodiment of FIG. 1 can be configured by a circuit in which AND gates and OR gates are connected in cascade. Also, the embodiment of FIG. 3 can be configured with AND gates instead of OR gates. In addition, the normal write operation is performed by the address decoder 1
Address to the corresponding memory unit 4 individually,
This can be performed by supplying a signal having a predetermined logical value to the write enable signal (WE).

[0019]

As described above, the present invention provides a memory test circuit that reduces the test time of a memory by half by writing data to all memory cells in a short time. Therefore, as the cost of the system is reduced, the number of cases in which the hardware is replaced with the firmware to perform the software processing is increasing, so that the demand for increasing the memory capacity is increasing. In addition, high added value of the system is required,
Since it is required to have multiple functions, it is necessary to increase the memory capacity. Meanwhile, as large-scale gate arrays have been commercialized, the number of memory cells created inside the gate arrays tends to increase more and more.
In such a situation and environment, the high-speed memory test circuit of the present invention has an advantage that the inspection time can be shortened and the manufacturing cost can be reduced. Further, the circuit for realizing the test circuit of the present invention is only one-stage or two-stage increase in the number of gates and is easy to realize.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of a memory test circuit according to the present invention.

FIG. 2 is a time chart showing the operation of the test circuit of the memory according to the present invention.

FIG. 3 is a block diagram of another embodiment of a memory test circuit according to the present invention.

FIG. 4 is an example of a conventional memory test circuit.

FIG. 5 is a time chart showing the operation of a conventional memory test circuit.

[Explanation of symbols]

 1 Address Decoder 2 OR Gate 3 NAND Gate 4 Memory Unit 5 Multiplexer 11 Address Line

Claims (6)

[Claims] 1. An address decoder which decodes a supplied address and outputs a signal to a corresponding address line, and stores or reads data based on the signal of the address line, a write enable signal and a supplied output enable signal. In a test circuit of a memory, which comprises a plurality of memories and a selection unit which selects one memory from the memories connected based on the address and outputs the data read from the memory, a test signal provided for each address line And a write control unit that calculates an output signal and a write enable signal for each gate unit and supplies the results to a corresponding memory. 2. The gate unit is composed of an OR gate, the write control unit is composed of a NAND gate, and the memory is in a low active and write enable state. A logical value "1" is written as a test signal. 2. The memory test circuit according to claim 1, wherein a logic value "1" is supplied as a permission signal. 3. The gate unit is configured by an OR gate, the write control unit is configured by an AND gate, and the memory is set to a high active and write enabled state, and a logical value “1” is written as a test signal. 2. The memory test circuit according to claim 1, wherein a logic value "1" is supplied as a permission signal. 4. An address decoder which decodes a supplied address and outputs a signal to a corresponding address line, a signal of the address line, a write enable signal and a supplied output enable signal, and a data bus. A memory test circuit comprising a plurality of memories to be connected, wherein the memory test circuit comprises an OR gate for inputting a test signal provided for each address line. 5. The memory according to claim 4, wherein the gate portion is composed of an OR gate, the memory is configured to be in a high active selected state, and a logic value “1” is supplied as a test signal. Test circuit. 6. The memory according to claim 4, wherein the gate section is composed of an AND gate, the memory is configured to be in a low active selected state, and a logical value “0” is supplied as a test signal. Test circuit.