JPH0851157A - Anti-fuse and manufacture of anti-fuse - Google Patents

Abstract

PURPOSE:To obtain excellent programming characteristics having a small dispersion of dielectric breakdown voltage by reducing the dispersion of the deposited film thickness of an insulator used for an anti-fuse layer. CONSTITUTION:A lower electrode 26 consisting of tungsten is formed onto a first metallic wiring layer 22, and brought into contact with the first metallic wiring layer 22 in the lowermost section of the lower electrode 26. Width in the vertical direction and lateral direction of the lower electrode 26 is set in the width of the first metallic wiring layer or less, and the thickness of the lower electrode 26 is set in approximately 80% of the film thickness of inter- layer insulating films 25 on the first metallic wiring layer 22. The sidewall sections of the lower electrode are coated with the inter-layer insulating films 25. The uppermost section of the lower electrode is coated with the inter-layer insulating film 25 except a section brought into contact with an anti-fuse layer 23. The anti-fuse layer 23 is formed between the lower electrode 26 and a second metallic wiring layer 24.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an antifuse and a method for manufacturing the antifuse in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, as a prototype of a gate array or its substitute, the logic which can be programmed at hand has been developed.
PGA (Field-Programmable Gate Array) is used. FPGA (Field-Programmable Gate Array)
There are two main programming methods, a memory method and an anti-fuse method, and the anti-fuse method is regarded as promising from the viewpoint of high speed and high integration of FPGA.
Further, in order to increase the speed and integration of the FPGA, an antifuse element has been developed which has a structure sandwiched between metal wires as a substitute for the structure sandwiched between polycrystalline silicon and a silicon substrate. The anti-fuse element is normally in a closed circuit or in a high resistance state, and changes to a low resistance state by an electric programming signal.

An example of a conventional antifuse will be described below with reference to the drawings. FIG. 3 is a sectional structural view showing a conventional antifuse. In FIG. 3, reference numeral 1 is an insulating substrate. Reference numeral 2 is a first metal wiring layer made of an aluminum alloy. 3 is an antifuse layer made of an insulator. Reference numeral 4 is a second metal wiring layer made of an aluminum alloy. Reference numeral 5 is an interlayer insulating film that electrically insulates the first metal wiring layer 2 and the second metal wiring layer 4.

The operation of the antifuse having the above structure will be described below.

The antifuse usually has a first metal wiring layer 2 and a second metal wiring layer 4 via an antifuse layer 3.
The first metal wiring layer 2 and the second metal wiring layer 4 form a closed circuit.

Here, when forming a circuit composed of the first metal wiring layer 2 and the second metal wiring layer 4 which are electrically insulated by the anti-fuse layer 3, first of all, the first metal wiring layer 2 is formed. And an electrical programming signal is externally provided to the second metal wiring layer 4. A voltage is applied between the first metal wiring layer 2 and the second metal wiring layer 4 via the antifuse layer 3 by a programming signal provided from the outside. When the critical value of the voltage applied between the first metal wiring layer 2 and the second metal wiring layer 4 is established through the antifuse layer 3, the antifuse layer 3 causes a dielectric breakdown. As a result, a low resistance state is created between the first metal wiring layer 2 and the second metal wiring layer 4, and the first metal wiring layer 2 and the second metal wiring layer 4
A new circuit including the metal wiring layer 4 is formed.

A method of forming the conventional antifuse shown in FIG. 3 will be described below. 4A to 4E are process cross-sectional views showing the manufacturing process of the conventional antifuse.

In FIG. 4, 11 is an insulating substrate, 12 is a first metal wiring layer made of an aluminum alloy, 13 is a portion forming an antifuse, 14 is an antifuse layer made of an insulator, and 15 is an aluminum alloy. The second metal wiring layer 16 is an interlayer insulating film that electrically insulates the first metal wiring layer 12 and the second metal wiring layer 15.

First, an aluminum alloy is deposited on the insulating substrate 11 by a sputtering method. Subsequently, the deposited aluminum alloy is masked and etched to form a first metal wiring layer 12 made of an aluminum alloy.
Are formed (FIG. 4A).

Next, an interlayer insulating film 16 is deposited on the first metal wiring layer 12 and the first metal wiring layer 12 is flattened (FIG. 4B). After that, the interlayer insulating film 16 is masked and etched to expose the first metal wiring layer 12 only in the portion 13 where the antifuse is formed (FIG. 4C).

Next, the exposed first metal wiring layer 12
Then, an insulator is deposited on the interlayer insulating film 16 by the CVD method (FIG. 4D).

The deposited insulator is then masked and etched to form the antifuse site 13.
The deposited insulator in a region other than the above is removed, and the antifuse layer 14 made of the deposited insulator is formed (FIG. 4E).

Next, an aluminum alloy is deposited by the sputtering method. Subsequently, the deposited aluminum alloy is masked and etched to form the second metal wiring layer 15 that covers the antifuse layer (FIG. 4F).

[0014]

In the conventional antifuse as described above, the portion 13 forming the antifuse is formed.
Is equal to the film thickness of the interlayer insulating film 16. Therefore, as the deposited film thickness of the interlayer insulating film 16 is larger, the deposited film thickness of the insulator used as the antifuse layer 14 is smaller in the bottom portion and the side wall portion of the portion 13 where the antifuse is formed than in the upper portion thereof. Further, when the plurality of antifuses are formed, the thickness of the insulator deposited on the bottom and the side wall of each antifuse is greatly varied. Here, since the electric field that causes the dielectric breakdown of the antifuse layer 14 mainly depends on the film thickness of the antifuse layer 14, the above-mentioned variation in the deposited film thickness remains as it is as the variation in the dielectric breakdown voltage of the antifuse layer 14. Become. When the antifuse is used as the program element of the FPGA, the variation in the dielectric breakdown voltage of the antifuse layer 14 becomes a serious problem in programming and reliability. To solve the above problems, the film thickness of the interlayer insulating film 16 may be reduced. However, in the semiconductor integrated circuit, the parasitic capacitance between the wirings increases as the film thickness of the interlayer insulating film 16 decreases. Therefore, it is difficult to thin the interlayer insulating film.

In the antifuse of the present invention, it is possible to reduce the variation in the deposited film thickness of the insulator used as the antifuse layer 14 on the bottom and side walls of the portion 13 forming the antifuse. As a result, variations in the dielectric breakdown voltage of the antifuse layer 14 can be reduced, and good programming characteristics and high reliability can be obtained.

[0016]

In order to solve the above-mentioned problems, an antifuse of the present invention comprises a first wiring made of a first conductor and an insulator formed on a substrate made of a semiconductor or an insulator. An anti-fuse layer, a second conductor electrode formed on the first wiring and directly below the anti-fuse layer, and a third conductor formed on the anti-fuse layer.
A second metal wiring made of a conductor of the above, and an interlayer insulating film for insulating the first metal wiring and the second metal wiring, and the height of the electrode made of the second conductor is It is about the same as the interlayer insulating film thickness on the metal wiring.

In order to solve the above problems, the method of manufacturing an antifuse of the present invention comprises a step of depositing a first conductor on a substrate made of a semiconductor or an insulator, and a second conductor on the first conductor. A step of depositing the first conductor, a step of etching and patterning the second conductor deposited on the first conductor, a step of etching the first conductor, and a step of etching the first conductor on the first and second conductors. A step of depositing an insulating film, a step of planarizing the first insulating film, a step of etching the first insulating film to expose a part of the second conductor, and a step of exposing the exposed second conductor. And a step of depositing a second insulating film on the first insulating film, a step of etching the second insulating film, a step of depositing a third conductor on the second insulating film, and a third step.
The step of etching the conductor of FIG.

[0018]

The present invention can reduce the depth of the portion where the antifuse is formed by the above-mentioned structure. As a result, it is possible to reduce variations in the deposited film thickness of the insulator used for the antifuse layer at the bottom and side walls of the portion where the antifuse is formed. Therefore, in the antifuse of the present invention, it is possible to reduce variations in the dielectric breakdown voltage of the antifuse layer, and it is possible to obtain good programming characteristics and high reliability.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An antifuse of an embodiment of the present invention will be described below with reference to the drawings. 1A is a vertical sectional structure view of an antifuse according to an embodiment of the present invention, and FIG. 1B is a lateral sectional structure view of an antifuse according to an embodiment of the present invention.

In FIG. 1, reference numeral 21 is an insulating substrate, 22 is a first metal wiring layer made of an aluminum alloy, 23 is an antifuse layer made of an insulator, and 24 is a second metal wiring layer made of an aluminum alloy. Reference numeral 25 denotes an interlayer insulating film made of silicon dioxide, which is used for the first metal wiring layer 22 and the second metal wiring layer 22.
This is for electrically insulating the metal wiring layer 24. Reference numeral 26 is a lower electrode made of tungsten.

The structure of the antifuse in the embodiment of the present invention will be described below. In FIG. 1, the first metal wiring layer 22 and the second metal wiring layer 24 are circuit elements of the semiconductor integrated circuit device. In addition, the first metal wiring layer 22 and the second metal wiring layer 24 are insulated by the interlayer insulating film 25 in a region other than the portion where the antifuse is formed and the contact required for circuit design. There is.

The lower electrode 26 made of tungsten is on the first metal wiring layer 22 and is in contact with the first metal wiring layer 22 at the lowermost portion. The vertical and horizontal widths of the lower electrode 26 are less than or equal to the width of the first metal wiring layer, and
The thickness of 6 is the thickness of the interlayer insulating film 25 on the first metal wiring layer 22.
It is about 80% of the film thickness. The sidewall of the lower electrode 26 is covered with the interlayer insulating film 25. The uppermost portion of the lower electrode 26 is covered with the interlayer insulating film 25 except for the portion in contact with the antifuse layer 23. Antifuse layer 23
Is between the lower electrode 26 and the second metal wiring layer 24,
The upper part is in contact with the second metal wiring layer 24 and the lower part is in contact with the lower electrode 26, and insulates the first metal wiring layer 22 and the second metal wiring layer 24 from each other.

With such a structure, the film thickness of the interlayer insulating film 25 can be reduced only in the portion where the antifuse is formed.
Therefore, the film thickness of the antifuse layer 23 at the bottom and the side wall of the portion where the antifuse is formed is about the same as that at the top. As a result, it is possible to reduce variations in the film thickness of the antifuse layer 23 at the bottom and side walls of the portion where the antifuse is formed.
By reducing the variation in the thickness of the antifuse layer 23,
The dielectric breakdown voltage of the anti-fuse layer 23 is stable, and an anti-fuse having good programming characteristics and high reliability can be obtained. In addition, the antifuse layer 23
The thickness of the interlayer insulating film 25 between the first metal wiring layer 22 and the second metal wiring layer 24 is sufficiently large, and the reduction in the calculation speed of the semiconductor device due to the parasitic capacitance between the wirings does not pose a problem.

A method of manufacturing an antifuse in one embodiment of the present invention will be described below. 2A to 2I are cross-sectional views showing the manufacturing process of the embodiment of the present invention.

In FIG. 2, reference numeral 31 is an insulating substrate. Three
Reference numeral 2 is a first metal wiring layer made of an aluminum alloy. 33 is an antifuse layer made of an insulator. Three
Reference numeral 4 is a second metal wiring layer made of an aluminum alloy. 35 is the first metal wiring layer 32 and the second metal wiring layer 3
4 is an interlayer insulating film made of silicon dioxide for electrically insulating 4. 36 is a lower electrode made of tungsten. 37 is a portion forming an antifuse.

First, an aluminum alloy is deposited on the insulating substrate 31 by sputtering to a thickness of about 6000Å so that the composition of aluminum is 99% and silicon is 1%. Then, tungsten is deposited to a thickness of about 5000 Å by the CVD method (FIG. 2A).

Next, the tungsten deposited on the aluminum alloy is masked and etched with a fluorine-based gas to form a lower electrode 36 made of tungsten on the aluminum alloy (FIG. 2B). Aluminum alloys are hardly etched by fluorine-based plasma and radicals.

Next, the aluminum alloy under the lower electrode 36 is masked and etched to form the first metal wiring layer 32 of aluminum alloy on the insulating substrate 31 (FIG. 2C).

Next, on the substrate including the first metal wiring layer 32 and the lower electrode 36, silicon dioxide is deposited to a thickness of about 20000Å by the plasma CVD method to form an interlayer insulating film 35 layer (FIG. 2 (d)).

Next, the interlayer insulating film 35 is etched by using a known resist etch back method to flatten the first metal wiring layer 32 and form a portion 37 on the lower electrode 36 where an antifuse is formed. The film thickness of the interlayer insulating film 35 is set to about 0 to 2000 Å (FIG. 2E).

Next, the interlayer insulating film 35 is masked and etched to form an antifuse portion 37.
Only, the surface of the lower electrode 36 is exposed (see FIG. 2).
(F)).

Next, an amorphous silicon film is deposited to about 1500 Å by plasma CVD method. At this time, since the film thickness of the interlayer insulating film 35 in the portion 37 where the antifuse is formed is as thin as 2000 Å or less, the film thickness of the amorphous silicon in the bottom portion and side wall portion of the portion 37 where the antifuse is formed is approximately 1500 Å, which is the same as the upper portion. Subsequently, the amorphous silicon film is masked and etched,
The antifuse layer 33 is formed (FIG. 2G).

Next, an aluminum alloy (aluminum; 99%, silicon; 1%) is 600 by sputtering.
Deposit to a thickness of 0Å. Subsequently, by masking and etching the deposited aluminum alloy,
A second metal wiring layer 34 is formed on the interlayer insulating film 35 and the antifuse layer 33 (FIG. 2 (h)).

[0034]

According to the antifuse of the present invention, the antifuse is provided with a lower electrode pattern immediately below the antifuse layer, the height of which is about the same as the interlayer insulating film thickness on the first metal wiring layer. It is possible to reduce the variation in the deposited film thickness of the insulator used for the antifuse layer at the bottom and side walls of the portion where the is formed. as a result,
Less variation in the dielectric breakdown voltage of the antifuse layer,
It is possible to form an antifuse having good programming characteristics and high reliability.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of an antifuse of the present invention.

FIG. 2 is a process cross-sectional view of one embodiment of the method for manufacturing an antifuse of the present invention.

FIG. 3 is a sectional view of a conventional antifuse.

4A to 4C are process cross-sectional views for explaining a conventional method for manufacturing an antifuse.

[Explanation of symbols]

 21 Insulating Substrate 22 First Metal Wiring Layer 23 Antifuse Layer 24 Second Metal Wiring Layer 25 Interlayer Insulating Film 26 Lower Electrode 31 Insulating Substrate 32 First Metal Wiring Layer 33 Antifuse Layer 34 Second Metal Wiring Layer 35 Interlayer insulating film 36 Lower electrode 37 Antifuse forming part

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Shuichi Mayumi 1-1, Saiwaicho, Takatsuki City, Osaka Prefecture Matsushita Electronics Industrial Co., Ltd.

Claims (2)

[Claims] 1. A first wiring made of a first conductor, formed on a substrate made of a semiconductor or an insulator, an antifuse layer made of an insulator, and on the first wiring and immediately below the antifuse layer. An electrode made of a second conductor formed on the antifuse layer, a second metal wiring made of a third conductor formed on the antifuse layer, the first metal wiring, and a second metal wiring.
An interlayer insulating film for insulating the metal wiring from each other, and the height of the electrode made of the second conductor is approximately the same as the interlayer insulating film thickness on the first metal wiring. And antifuse. 2. A substrate made of a semiconductor or an insulator,
Depositing a first conductor, depositing a second conductor on the first conductor, and etching and patterning the second conductor deposited on the first conductor, Etching the first conductor; and the first
And depositing a first insulating film on the second conductor,
A step of planarizing the first insulating film, a step of etching the first insulating film to expose a part of the second conductor, and a step of exposing the exposed second conductor and the first conductor. Depositing a second insulating film on the insulating film; etching the second insulating film; depositing a third conductor on the second insulating film; A method for manufacturing an antifuse, comprising a step of etching a conductor.