JPH0851188A - Semiconductor integrated circuit device and manufacturing method thereof - Google Patents

Abstract

PURPOSE:To enhance the ESD endurability of an electrostatic discharge(ESD) prevention circuit by the use of parasitic bipolar transistor operation. CONSTITUTION:By ion-implanting P-type impurities into the P-type semiconductor region 4 of an electrostatic discharge prevention circuit with a mask of a photoresist 8, after forming the p-type semiconductor region 4 at the lower part of the field insulating film 3 of a p-type well 2, the impurity concentration of the p-type semiconductor region 4 just under the field insulating film 3 is made high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a manufacturing technique thereof, and is particularly effective when applied to a semiconductor integrated circuit device provided with an electrostatic discharge (ESD) prevention circuit utilizing the operation of a parasitic bipolar transistor. It is about technology.

[0002]

2. Description of the Related Art LSIs formed on a silicon substrate are
It is provided with an electrostatic breakdown prevention circuit for protecting the circuit from an excessive current input through an external terminal (bonding pad) of the chip. This kind of electrostatic breakdown prevention circuit,
For example, as described in JP-A-3-234055 and the like, it is configured by combining a MISFET, a resistance element, a bipolar transistor, etc., and is usually arranged between an external terminal and an input / output circuit.

One of the electrostatic breakdown prevention circuits utilizes a parasitic bipolar transistor operation. This circuit is composed of a p-type semiconductor region formed on a semiconductor substrate below a field insulating film for element isolation, and a pair of n-type semiconductor regions sandwiching the p-type semiconductor region.
One of the type semiconductor regions (the side connected to the external terminal)
Operates as a collector region, the other (side connected to GND) as an emitter region, and the p-type semiconductor region as a base region,
It absorbs the excessive current input through the external terminal to the GND side.

The p-type semiconductor region forming the electrostatic breakdown prevention circuit is formed simultaneously in the step of forming a p-type channel stopper region for inversion prevention on the semiconductor substrate below the field insulating film, and a pair of n-type semiconductor regions are formed. , N on the semiconductor substrate
It is formed at the same time in the process of forming the source region and the drain region of the channel type MISFET. As a result, the electrostatic breakdown prevention circuit can be formed without increasing the number of manufacturing steps.

[0005]

The inventor of the present invention has proposed the electrostatic breakdown (E) utilizing the operation of the parasitic bipolar transistor.
As a result of studying the SD) prevention circuit, it was found that the ESD resistance of this circuit is likely to deteriorate.

As described above, the p-type semiconductor region (base region of the parasitic bipolar transistor) of this electrostatic breakdown prevention circuit is formed by forming the p-type channel stopper region for inversion prevention on the semiconductor substrate below the field insulating film. Use it to form. Specifically, a silicon nitride film serving as a mask for thermal oxidation is deposited on the surface of a semiconductor substrate, the silicon nitride film in the field insulating film formation region is removed by etching, and then a p-type impurity (boron) is formed in the element isolation region. Is ion-implanted, and then the surface of the semiconductor substrate is steam-oxidized.
As a result, a thick field insulating film is formed on the semiconductor substrate in the element isolation region, and a p-type semiconductor region is formed thereunder by diffusion of the p-type impurities. This p-type semiconductor region constitutes the base region of the parasitic bipolar transistor in the electrostatic breakdown prevention circuit, and the channel stopper region in other circuits (peripheral circuits other than the electrostatic breakdown prevention circuit, memory circuits, etc.).

However, according to the study by the present inventor, when the p-type semiconductor region of the electrostatic breakdown prevention circuit is formed by the method as described above, a part of the p-type impurities becomes the field insulating film during the growth of the field insulating film. It was found that the impurities were sucked up and the impurity concentration immediately below the field insulating film was lowered as shown in FIG. As a result, when the parasitic bipolar transistor operates, the electric field concentrates immediately below the field insulating film, and crystal defects such as dislocation are generated in the semiconductor substrate in the n-type semiconductor region (collector region).
It was found by M (Transmission Electron Microscope) observation.

It is considered that the occurrence of the crystal defects as described above is caused by the local heat generation in the semiconductor substrate due to the electric field concentration directly under the field insulating film and the mechanical stress. However, if such a crystal defect occurs, the leak current increases, so that the driving capability of the parasitic bipolar transistor decreases and the ESD resistance deteriorates.

An object of the present invention is to provide a technique capable of improving the ESD resistance of an electrostatic breakdown prevention circuit using a parasitic bipolar transistor operation.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows.

According to another aspect of the semiconductor integrated circuit device of the present invention, a first conductive type semiconductor region is formed below a field insulating film of a first conductive type semiconductor substrate, and a pair of second conductive type semiconductor regions sandwiching the first conductive type semiconductor region. A channel formed in the lower portion of the field insulating film around the electrostatic breakdown prevention circuit by forming an electrostatic breakdown prevention circuit with the type semiconductor region and adjusting the impurity concentration of the first conductivity type semiconductor region immediately below the field insulating film. It is higher than the impurity concentration of the stopper region.

The method of manufacturing a semiconductor integrated circuit device according to the present invention includes the following steps when forming the electrostatic breakdown prevention circuit.
It includes (a) to (d).

(A) An insulating film serving as an oxidation mask is deposited on the main surface of the first conductivity type semiconductor substrate, the insulating film in the element isolation region is removed, and then a first film is formed on the semiconductor substrate in the element isolation region. Ion-implanting conductivity type impurities, (b) by thermally oxidizing the semiconductor substrate to form a field insulating film on the main surface of the semiconductor substrate in the element isolation region, and at the bottom of the field insulating film. A step of forming a first conductive type semiconductor region on a semiconductor substrate, (c) using a photoresist having a hole formed in an upper portion of the field insulating film in a region for forming an electrostatic breakdown preventing circuit as a mask, Ion implanting a first conductivity type impurity into the first conductivity type semiconductor region, (d) ion implanting a second conductivity type impurity into the semiconductor substrate, and then thermally diffusing the second conductivity type impurity. And a step of forming a pair of second conductivity type semiconductor regions sandwiching the first conductivity type semiconductor region.

In the method for manufacturing a semiconductor integrated circuit device of the present invention, in the step (d), the second conductivity type semiconductor region forming the source region and the drain region of the MISFET is formed.

[0016]

According to the above-mentioned means, the electric field concentration under the field insulating film can be prevented by increasing the impurity concentration of the first conductivity type semiconductor region of the electrostatic breakdown prevention circuit. It is possible to prevent the occurrence of such crystal defects and reduce the leak current.

Further, according to the above-mentioned means, since only the step of forming a photomask and performing ion implantation is added to the conventional process, the ESD resistance of the electrostatic breakdown prevention circuit can be improved with a minimum increase in steps. it can.

[0018]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 is a sectional view of a main part of a semiconductor substrate 1 showing an electrostatic breakdown prevention circuit of this embodiment. As shown in the figure, the electrostatic breakdown prevention circuit of this embodiment has a p-type semiconductor under a field insulating film 3 for element isolation made of silicon oxide formed on the main surface of a p-type well 2 of a semiconductor substrate 1. The region 4 and a pair of n-type semiconductor regions 5 and 6 sandwiching the p-type semiconductor region 4 are formed. Further, one of the pair of n-type semiconductor regions 5 and 6 (semiconductor region 5) is connected to an external terminal (bonding pad) BP, and the other (semiconductor region 6) is connected to GND.

The electrostatic breakdown prevention circuit is arranged, for example, between the external terminal BP and the input circuit I, and when an excessive current is inputted through the external terminal BP, the n-type semiconductor region 5 on the external terminal BP side. Is a collector region (C), the n-type semiconductor region 6 on the GND side is an emitter region (E), and the p-type semiconductor region 4 below the field insulating film 3 is a base region (B). This excessive current is absorbed on the GND side.

Next, an example of a method of manufacturing the above electrostatic breakdown prevention circuit will be described with reference to FIGS.

First, as shown in FIG. 2, p-type impurities (BF ₂ ⁺ ) are added to the semiconductor substrate 1 made of p-type single crystal silicon.
Are ion-implanted (60 keV, 4.7 × 10 ¹² / cm ⁻² ), and then the semiconductor substrate 1 is heat-treated (1200 ° C., 3 hours) to extend and diffuse the p-type impurities to obtain a p-type well. Form 2.

Next, as shown in FIG. 3, after depositing a silicon nitride film 3 on the main surface of the p-type well 2 by the CVD method,
The silicon nitride film 3 in the element isolation region is removed by dry etching using a photoresist as a mask.

Next, as shown in FIG. 4, the silicon nitride film 3 is used as a mask to p-type the p-type well 2 in the element isolation region.
Type impurities (BF ₂ ⁺ ) by ion implantation (60 keV, 2 ×
10 ¹³ / cm ⁻² ) and then steam-oxidizing the semiconductor substrate 1 (1000 ° C., 2 hours) to deposit a thick silicon oxide film on the main surface of the p-type well 2 in the element isolation region as shown in FIG. The field insulating film 3 is formed, and the p-type semiconductor region 4 is formed in the p-type well 2 below the field insulating film 3. This p-type semiconductor region 4 constitutes the base region of the parasitic bipolar transistor in the electrostatic breakdown prevention circuit, but is p-type in other circuits (peripheral circuits other than the electrostatic breakdown prevention circuit, memory circuits, etc.). The channel stopper region of.

Next, after the silicon nitride film 3 is removed by hot phosphoric acid, as shown in FIG. 6, a photoresist 8 having a hole formed in the upper portion of the field insulating film 3 in the region where the electrostatic breakdown preventing circuit is formed is formed. Using the mask as a mask, p-type impurities (B) are ion-implanted (240 keV, 5 × 10 ¹³ / cm ⁻² ) into the p-type semiconductor region 4 below the field insulating film 3.

As described above, in this embodiment, the p-type well 2 is used.
Of the p-type semiconductor region 4 of the electrostatic breakdown prevention circuit in the step of forming the channel stopper region under the field insulating film 3 of FIG.
After forming the p
By implanting p-type impurities into the type semiconductor region 4, the impurity concentration of the p-type semiconductor region 4 of the electrostatic breakdown prevention circuit is made higher than that of the channel stopper region.

Next, after the photoresist 8 is removed, as shown in FIG. 7, an n-type impurity (P) is ion-implanted into the entire surface of the p-type well 2 and then the n-type impurity is diffused. Thus, the n-type semiconductor regions 5 and 6 of the electrostatic breakdown prevention circuit shown in FIG. 1 are formed. Further, in this step, the n-channel type MISFET is formed in the other region of the p-type well 2.
Source region and drain region are formed.

FIG. 8 shows the impurity concentration profile of the p-type semiconductor region of the electrostatic breakdown prevention circuit measured by computer simulation. The white circles in the figure are the p-type semiconductor regions 4 manufactured by the method of this embodiment, and the black circles are. The impurity concentration along each substrate direction of the p-type semiconductor region manufactured by the conventional method is shown. As shown in the figure, it can be seen that the p-type semiconductor region 4 manufactured by the method of this embodiment has a higher impurity concentration immediately below the field insulating film than that of the conventional technique.

FIG. 9 shows the results of measuring the ESD withstand voltage of each of the electrostatic breakdown prevention circuit manufactured by the method of this embodiment and the electrostatic breakdown prevention circuit manufactured by the conventional method. As shown in the figure, it can be seen that the ESD breakdown voltage of the electrostatic breakdown prevention circuit manufactured by the method of this embodiment is significantly improved as compared with the conventional method.

As described above, according to this embodiment, the ESD resistance of the electrostatic breakdown prevention circuit can be significantly improved by increasing the number of manufacturing steps by one step as compared with the conventional method.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say.

In the above-mentioned embodiment, the case where the present invention is applied to the process of simultaneously forming the channel stopper region when forming the field insulating film on the main surface of the p-type well, is described, for example, on the main surface of the semiconductor substrate. It is also possible to apply to the process of forming the p-type well and the p-type channel stopper region (and the p-type semiconductor region of the electrostatic breakdown prevention circuit) at the same time by forming the p-type impurity by ion implantation after forming the. In this case, after forming the channel stopper region (and the p-type semiconductor region of the electrostatic breakdown prevention circuit), p-type impurities are introduced into the p-type semiconductor region of the electrostatic breakdown prevention circuit by ion implantation using a photoresist as a mask. Good.

Depending on the device, a p-type buried layer may be formed in the p-type well after forming the field insulating film (and the p-type channel stopper region). When the present invention is applied to such a device, p
By introducing the p-type impurity into the p-type semiconductor region of the electrostatic breakdown prevention circuit by using the step of forming the p-type buried layer in the well, the ESD resistance of the electrostatic breakdown prevention circuit can be greatly increased by the same manufacturing process as before. Can be improved.

In the above-mentioned embodiment, the case of applying to the electrostatic breakdown preventing circuit composed of the p-type semiconductor region under the field insulating film and the pair of n-type semiconductor regions sandwiching the field insulating film has been described. It can also be applied to an electrostatic breakdown prevention circuit composed of an n-type semiconductor region below a field insulating film formed on the main surface and a pair of p-type semiconductor regions sandwiching the n-type semiconductor region.

The present invention can also be applied to an electrostatic breakdown prevention circuit composed of a first conductivity type semiconductor region formed on the main surface of an active region and a pair of second conductivity type semiconductor regions sandwiching the first conductivity type semiconductor region. it can.

[0036]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the present invention, the E of the electrostatic breakdown prevention circuit is
Since the SD breakdown voltage can be improved, the reliability of the LSI can be improved. In addition, LS
It is possible to promote low standby power consumption of I.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a semiconductor substrate showing an electrostatic breakdown prevention circuit according to an embodiment of the present invention.

FIG. 2 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an electrostatic breakdown prevention circuit according to an embodiment of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an electrostatic breakdown prevention circuit according to an embodiment of the present invention.

FIG. 4 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an electrostatic breakdown prevention circuit according to an embodiment of the present invention.

FIG. 5 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing an electrostatic breakdown prevention circuit according to an embodiment of the present invention.

FIG. 6 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an electrostatic breakdown prevention circuit according to an embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of a semiconductor substrate showing a method for manufacturing an electrostatic breakdown prevention circuit according to an embodiment of the present invention.

FIG. 8 is a graph showing the impurity concentration profiles of the present invention and the conventional electrostatic breakdown prevention circuit measured by computer simulation.

FIG. 9: ES of the present invention and the conventional electrostatic breakdown prevention circuit
It is a graph which shows the measurement result of D withstand voltage.

FIG. 10 is a graph showing an impurity concentration profile below a field insulating film of a conventional electrostatic breakdown prevention circuit.

[Explanation of reference numerals] 1 semiconductor substrate 2 p-type well 3 field insulating film 4 p-type semiconductor region 5 n-type semiconductor region 6 n-type semiconductor region 7 silicon nitride film 8 photoresist BP external terminal (bonding pad) I input circuit

Front Page Continuation (72) Chiemi Hashimoto, Inventor, 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Inside Hitate Cho-LS Engineering Co., Ltd. (72) Kosuke Okuyama, Komizu-shi, Tokyo 5-20-1, Honmachi Ltd. Semiconductor Company, Hitachi Ltd. (72) Inventor Hiroyasu Ishizuka 3274, Yagibashi Higashi 3 Yanagibashi Higashi, Yonezawa, Yonezawa, Yamagata Prefecture

Claims (4)

[Claims] 1. A first conductivity type semiconductor region formed below a field insulating film of a first conductivity type semiconductor substrate, and a pair of second conductivity type semiconductor regions sandwiching the first conductivity type semiconductor region. A semiconductor integrated circuit device having an electrostatic breakdown prevention circuit according to claim 1, wherein an impurity concentration of the first conductivity type semiconductor region immediately below the field insulation film is formed under a field insulating film around the electrostatic breakdown prevention circuit. The semiconductor integrated circuit device is characterized in that the impurity concentration of the channel stopper region is increased. 2. The semiconductor integrated circuit device according to claim 1, wherein the electrostatic breakdown prevention circuit is arranged between an external terminal and an input / output circuit. 3. A method of manufacturing a semiconductor integrated circuit device comprising the electrostatic breakdown prevention circuit according to claim 1 or 2.
A method of manufacturing a semiconductor integrated circuit device, comprising the following steps (a) to (d). (a) An insulating film serving as an oxidation mask is deposited on the main surface of the first conductivity type semiconductor substrate, the insulating film in the element isolation region is removed, and then the first conductivity type impurity is added to the semiconductor substrate in the element isolation region. A step of ion-implanting (b) by thermally oxidizing the semiconductor substrate to form a field insulating film on the main surface of the semiconductor substrate in the element isolation region, and to the semiconductor substrate below the field insulating film. Forming a first conductive type semiconductor region, and (c) using the photoresist having an opening in the upper portion of the field insulating film in the region where the electrostatic breakdown prevention circuit is formed as a mask, the first portion of the lower portion of the field insulating film Ion implanting a first conductivity type impurity into the conductivity type semiconductor region, and (d) ion implanting a second conductivity type impurity into the semiconductor substrate, and then thermally diffusing the second conductivity type impurity. A step of forming a pair of second conductivity type semiconductor regions sandwiching the first conductivity type semiconductor region. 4. The method of manufacturing a semiconductor integrated circuit device according to claim 3, wherein the second conductivity type semiconductor region forming the source region and the drain region of the MISFET is formed in the step (d).