JPH0851203A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the subthreshold characteristics in a highly integrated vertical transistor. A transistor opening 16 is provided through the interlayer insulating film 15, and epitaxial layers 18, 19a and 19b serving as a source / channel / drain are stacked therein to form an active region 17, and A gate electrode opening 20 penetrating two layers is formed from above the active region 17, and a gate electrode 23 is formed therein with a gate insulating film 22 interposed therebetween.
To form.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS type semiconductor device, and more particularly to a vertical transistor having a channel in the vertical direction.

[0002]

2. Description of the Related Art In recent years, in accordance with the demand for higher integration and higher performance of VLSI, a crystal layer of Si is formed on a Si oxide film on the Si surface, and an SOI (Silicon) device is formed there.
On-insulator) structures and three-dimensional elements such as vertical MOS transistors having channels in the vertical direction are expected. FIG. 61 shows, for example, the document IEEE IEDM.
85 P. 694 is a cross-sectional view showing a structure of a memory cell of a DRAM using a conventional SOI transistor shown in 964, Hide Sunami. FIG. In the figure, 1 is a semiconductor substrate made of Si single crystal or the like, 2 is a cell plate,
3, 4 are n ⁺ type impurity diffusion layers, 5 and 6 are Si oxide films, 7
Is a p-type Si layer, 8 is a gate electrode serving as a word line, and 9 is a bit line.

As shown in the figure, a cell plate 2, an n ⁺ -type impurity diffusion layer 3a and a capacitor composed of a Si oxide film 5a sandwiched between these two electrodes, and an n ⁺ -type impurity diffusion layer 3 are formed.
A memory cell is constituted by a switching transistor having b and 4 as source / drain regions, and this switching transistor is an SOI transistor in which a p-type Si layer 7 serving as a channel region is formed on the Si oxide film 5b. In the SOI type transistor configured as described above, the depletion layer formed in the lower layer portion of the channel region is connected in series with the insulating film formed thereunder during the transistor operation, so that the substantial depletion layer capacitance is It is reduced, the subthreshold characteristic is improved, and high performance is obtained.

However, in the conventional SOI type transistor as described above, the source / channel / drain regions 3 are formed.
b, 7, and 4 are formed in the same plane, and as shown in the figure, L ₁
It requires a length of + L ₂ + L ₃ . For example, the gate length is 0.8
μm, the sidewall S formed on the sidewall of the gate electrode 8
When the width of the source / drain regions 3b and 4 including the width of the i oxide film (for example, 0.2 μm) is 1.2 μm, the length is typically 1.2 + 0.8 + 1.2 = 3.2 (μm). However, the area occupied by the transistor cannot be reduced.

Similarly, the document IEEE IEDM85
P. A conventional vertical MOS transistor shown in 696, Hide Sunami will be described. FIG. 62
FIG. 6 is a sectional view showing a structure of a memory cell of a DRAM using a conventional vertical MOS transistor. In the figure,
1-3, 5, 6, and 9 are the same as those in FIG. 61, 1
0 is p-type Si formed on the n ⁺ -type impurity diffusion layer 3b
A layer, 11 is an n ⁺ -type impurity diffusion layer formed on the p-type Si layer 10, and 12 is a columnar pattern composed of two n ⁺ -type impurity diffusion layers 3b and 11 and the p-type Si layer 10 therebetween. The gate electrode is a word line formed around the side surface via the Si oxide film 6.

As shown in FIG. 62, the capacitor constituting the memory cell is similar to that of FIG. 61, and the switching transistor has two n ⁺ -type impurity diffusion layers 3b and 11 as source / drain regions and p-type Si layer 10. Is a channel region, and these are formed in the vertical direction by using, for example, a selective epitaxial technique or the like to form a vertical MOS transistor. In the vertical MOS transistor thus configured, as shown in the drawing, the thickness L ₄ of the gate electrode 12 and the width of the columnar pattern formed by the source / drain and channel regions 3b, 11 and 10 are L _5. , Requires a region approximately L ₄ + L ₅ + L ₄ . For example, when the film thickness L ₄ of the gate electrode 12 is 0.3 μm and the width of the columnar pattern is 1.0 μm, typically 0.3 + 1.0 + 0.3 = 1.6 (μ
Since the transistor can be formed in the region of length m), the area occupied by the transistor is obviously reduced and the structure is suitable for high integration.

[0007]

However, in the conventional vertical MOS transistor as described above, there is an insulating film for reducing the depletion layer capacitance formed in the channel region like the conventional SOI type transistor described above. Not because
There is a problem that the subthreshold characteristics cannot be improved, and both the conventional SOI type transistor and the vertical type MOS transistor have high performance and high integration.
It couldn't meet one requirement.

The present invention has been made to solve the above problems, and an object of the present invention is to obtain a semiconductor device including a transistor having improved subthreshold characteristics, high performance, and high integration. Another object of the present invention is to provide a manufacturing method suitable for this device.

[0009]

According to a first aspect of the present invention, there is provided a semiconductor device comprising: an interlayer insulating film on a semiconductor substrate; Is formed so as to be surrounded by the interlayer insulating film, a semiconductor layer of the first conductivity type which becomes a channel region on the semiconductor substrate in the opening for transistor, and the semiconductor layer is sandwiched in the vertical direction. An active region formed by stacking three layers of a second conductivity type semiconductor layer to be a source / drain region and a central part of the opening for the transistor so as to penetrate at least two layers from above the active region. The gate electrode opening is formed, and the gate electrode is formed in the gate electrode opening via the gate insulating film.

A semiconductor device according to claim 2 of the present invention is
A semiconductor substrate is provided with a diffusion layer of the second conductivity type, an opening for a transistor is formed in the diffusion layer formation region so as to reach the diffusion layer, and the bottom layer of the active region is connected to the diffusion layer. Is.

A semiconductor device according to claim 3 of the present invention is
A metal silicide layer is formed on the surface of the diffusion layer provided on the semiconductor substrate, except for the region in contact with the active region.

A semiconductor device according to claim 4 of the present invention is
The active region is composed of an epitaxial layer.

A semiconductor device according to claim 5 of the present invention is
The semiconductor layer which becomes at least the channel region of the active region,
It is composed of an epitaxial layer made of a compound of Si and Ge.

According to a sixth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a transistor opening in the interlayer insulating film, and a transistor opening. A step of forming an active region by a selective epitaxial growth method, a step of forming a gate electrode opening so as to penetrate two layers from above the active region, and a gate insulating film on the inner wall of the gate electrode opening. After the formation, the step of forming the gate electrode so as to be embedded in the opening for gate electrode is performed.

A semiconductor device according to claim 7 of the present invention is
A wiring film connected to the uppermost layer of the active region is provided from above the active region to above the interlayer insulating film, and for the gate electrode such that this wiring film and two layers from above at least the active region are continuously penetrated. An opening is formed, and a gate insulating film is further formed on the inner wall of the opening for gate electrode and the surface of the wiring film.

According to an eighth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a transistor opening in the interlayer insulating film, and a transistor opening. A step of forming an active region by selective epitaxial growth in the portion and then forming a wiring film over the active region and the interlayer insulating film; and a step of penetrating the wiring film and the two layers from above the active region. And a step of forming a gate electrode opening after that, and then forming a gate insulating film and then forming a gate electrode.

A semiconductor device according to claim 9 of the present invention is
A recess of a predetermined depth is provided in the interlayer insulating film, a transistor opening penetrating the interlayer insulating film is formed in a part of the recessed region, and the uppermost layer of the active region formed in the transistor opening is formed. A wiring film to be connected is provided in the recess,
An opening for a gate electrode is formed so as to continuously penetrate the wiring film and at least two layers from above the active region, and a gate insulating film is formed on the inner wall of the opening for the gate electrode and the surface of the wiring film. It was formed.

According to a tenth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, including a step of forming an interlayer insulating film on a semiconductor substrate, forming a recess in the interlayer insulating film, and forming the interlayer in a part of the recess area. A step of forming a transistor opening penetrating the insulating film, and a step of forming an active region in the transistor opening by a selective epitaxial growth method,
Next, a step of forming a conductive film to be a wiring film on the entire surface so as to fill the concave portion, and flattening the entire surface by leaving the conductive film only in the concave portion; The method includes a step of forming a gate electrode opening so as to penetrate the two layers from above the active region, and a step of forming a gate insulating film and then forming a gate electrode.

According to an eleventh aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises the steps of forming an interlayer insulating film on a semiconductor substrate, forming a recess in the interlayer insulating film, and forming the interlayer in a part of the recess region. A step of forming a transistor opening penetrating the insulating film, and a step of forming an active region in the transistor opening by a selective epitaxial growth method,
Next, a step of forming a conductive film to be a wiring film on the entire surface so as to fill the inside of the recess and flattening the entire surface by leaving the conductive film only in the recess, and then further retreating the conductive film by etching. After that, a step of forming an insulating film on the entire surface and flattening the entire surface by leaving the insulating film only in the concave portion, and then forming a wiring film made of the insulating film and the conductive film on the active region. And a step of forming a gate electrode opening so as to penetrate through the two layers, and a step of forming a gate insulating film and then forming a gate electrode.

According to a twelfth aspect of the present invention, an active region is formed in the transistor opening so that the surface height of the active region is lower than the surface of the interlayer insulating film by a predetermined amount, and the transistor opening is formed. A recess is provided in the interlayer insulating film so as to surround the periphery of the upper layer at a depth that does not reach the second layer from the top of the active region. The gate electrode opening is formed in a self-aligned manner in the active region in the transistor opening, and a gate insulating film is formed on the inner wall of the gate electrode opening, the active region surface, and the wiring film surface. It was formed.

A method of manufacturing a semiconductor device according to a thirteenth aspect of the present invention is directed to a step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a transistor opening in the interlayer insulating film, and a step of forming the transistor opening. A step of forming an active region in the portion by a selective epitaxial growth method so that the surface height thereof is lower than the surface of the interlayer insulating film by a predetermined amount, and then Si is formed on the exposed portion of the interlayer insulating film on the inner wall of the transistor opening. A step of forming a sidewall of a nitride film, a step of etching the active region in a self-aligning manner using the sidewall of the Si nitride film and the interlayer insulating film as a mask, and forming a gate electrode opening, The step of burying the gate electrode opening with the burying layer of the Si nitride film and the step of filling the sidewall and burying layer of the Si nitride film with each other. Forming a recess in the interlayer insulating film using the strike pattern as a mask, and forming a conductive film to be a wiring film on the entire surface so as to fill the recess, and then leave the conductive film only in the recess. The method includes a step of flattening the entire surface, a step of removing the sidewalls and the buried layer of the Si nitride film thereafter, and a step of forming a gate insulating film and then forming a gate electrode.

According to a fourteenth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a transistor opening in the interlayer insulating film, and a transistor opening. A step of forming an active region in the portion by a selective epitaxial growth method so that the height of the surface thereof is lower than the surface of the interlayer insulating film by a predetermined amount, and then in an exposed portion of the interlayer insulating film on the inner wall of the opening for the transistor. A step of forming a sidewall of a Si nitride film, and a step of etching the active region in a self-aligning manner with the sidewall of the Si nitride film and the interlayer insulating film as a mask to form a gate electrode opening. ,
A step of filling the gate electrode opening with a burying layer of a Si nitride film; a step of forming a concave portion in the interlayer insulating film using the sidewall and filling layer of the Si nitride film and a resist pattern as a mask; After forming a conductive film to be a wiring film on the entire surface so that
A step of flattening the entire surface by leaving the conductive film only in the concave portion, and then further receding the conductive film by etching, and then forming an insulating film on the entire surface. A step of leaving it and flattening the entire surface,
After that, a step of removing the sidewall and the buried layer of the Si nitride film and a step of forming a gate insulating film and then forming a gate electrode are included.

According to a fifteenth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a concave portion in the interlayer insulating film, and a Si nitride film inside the concave portion The step of burying with the burying layer of
A step of forming a transistor opening penetrating the buried layer of the Si nitride film and the interlayer insulating film in a part of the recessed region, and S on the side wall in the transistor opening.
After forming a sidewall of the i-nitride film and then forming a Si oxide film on the entire surface so as to fill the inside of the transistor opening, the upper portion of the sidewall of the Si-nitride film is removed to remove the side wall of the Si-nitride film. Removing the entire surface until the width of the wall becomes constant and planarizing it, and forming a buried layer of the Si oxide film, and then removing the buried layer and sidewalls of the Si nitride film,
Next, a step of forming an active region around the buried layer of the Si oxide film by a selective epitaxial growth method in the opening for the transistor under the recess, and then a conductive film which becomes a wiring film over the entire surface so as to be buried in the recess. And forming the conductive film, the conductive film is left only around the buried layer of the Si oxide film in the recess to planarize the entire surface, and then the buried layer of the Si oxide film is removed using a resist mask. , And a step of forming a gate electrode opening, and then forming a gate insulating film and then forming a gate electrode.

A semiconductor device according to a sixteenth aspect of the present invention is such that a wiring film connected to the uppermost layer of the active region and an insulating film sufficiently thicker than the gate insulating film are provided on the wiring film.

A semiconductor device according to a seventeenth aspect of the present invention has the active region formed of a diffusion layer formed of a substrate semiconductor layer.

According to an eighteenth aspect of the present invention, in a method of manufacturing a semiconductor device, a step of forming a gate electrode opening in a semiconductor substrate and, after filling the gate electrode opening with an embedded layer of a Si nitride film, A step of etching the semiconductor substrate to project an upper layer portion of the Si nitride film burying layer; a step of forming a first Si oxide film sidewall on a side surface of the projecting portion of the Si nitride film burying layer; Etching the semiconductor substrate using the first Si oxide film side wall and the burying layer of the Si nitride film as a mask to form a substrate semiconductor layer so as to surround the periphery of the burying layer of the Si nitride film; A second silicon oxide film is formed around the first silicon oxide film side wall and the substrate semiconductor layer below the second silicon oxide film side wall.
And the step of forming the Si oxide film side wall, and the semiconductor substrate is etched again by using the first and second Si oxide film side walls and the buried layer of the Si nitride film as a mask, and the sidewall is surrounded by A step of forming a substrate semiconductor layer including a lower layer portion not formed so as to surround the buried layer of the Si nitride film, and then a lower layer portion of the substrate semiconductor layer by ion implantation and the semiconductor substrate around it. A step of forming an impurity diffusion layer to be the lowermost layer of the active region, a step of forming an interlayer insulating film over the entire surface, and then planarizing the entire surface until the substrate semiconductor layer surface is exposed, and then performing an ion implantation method. Forming a two-layered impurity diffusion layer on the substrate semiconductor layer from above the active region; Like this, a step of forming a recess in the interlayer insulating film to a depth that does not reach the second layer of the active region, then a step of filling a wiring film in the recess, and then removing the buried layer of the Si nitride film. And then forming the gate insulating film after forming the gate insulating film by forming the gate electrode opening.

According to a nineteenth aspect of the present invention, in a semiconductor device, a first interlayer insulating film, a gate electrode formed in a predetermined region on the first interlayer insulating film, and the gate electrode are provided on the semiconductor substrate. A second interlayer insulating film formed to cover the first interlayer insulating film, and the second interlayer insulating film, the gate electrode, and the first interlayer insulating film in the gate electrode formation region. A linear transistor opening formed so as to penetrate therethrough to reach the underlying semiconductor substrate, a gate insulating film formed on the inner wall of the transistor opening, and the transistor having the gate insulating film formed On the semiconductor substrate in the opening for use, three layers of a first-conductivity-type epitaxial layer to be a channel region and a second-conductivity-type epitaxial layer to be a source / drain region so as to sandwich the channel from above and below are laminated. , A vertical thin film which is formed in the active region, and has a.

In a semiconductor device according to a twentieth aspect of the present invention, a second conductive type diffusion layer is provided on a semiconductor substrate, and a transistor opening is formed in the diffusion layer forming region so as to reach the diffusion layer. The bottom layer of the active region is connected to the diffusion layer.

A semiconductor device according to a twenty-first aspect of the present invention has a transistor opening formed with a fine width with an upper limit value of 0.2 μm.

According to a twenty-second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, which comprises a step of forming a first interlayer insulating film on a semiconductor substrate and a step of forming a gate electrode on the first interlayer insulating film, A step of forming a second interlayer insulating film on the entire surface to cover the gate electrode, and penetrating the second interlayer insulating film, the gate electrode and the first interlayer insulating film in the gate electrode forming region. Forming a linear transistor opening, and then forming a gate insulating film, and then forming an active region in the transistor opening,
Is to have.

[0031]

According to the semiconductor device of the present invention, the active region is formed by vertically stacking three layers of source / channel / drain in the opening for the transistor surrounded by the interlayer insulating film, and at least the active region is formed. A transistor is formed by forming a gate electrode opening from the top through two layers and forming a gate electrode therein through a gate insulating film. Therefore, the active region has a gate electrode inside,
It has a cylindrical shape with an interlayer insulating film around it. That is, even in the channel region which is the second layer from the top of the active region, the gate electrode is formed on the inner side and the interlayer insulating film is formed on the outer side, and the same effect as that of the SOI type transistor is obtained. That is, the depletion layer formed in the channel region during transistor operation is connected in series with the surrounding interlayer insulating film, the depletion layer capacitance is reduced, and the subthreshold characteristic is improved. In addition, since it is a vertical transistor in which the active region is formed in the vertical direction, the area occupied by the transistor is very small.
Subthreshold characteristics are improved, and a semiconductor device with high performance and high integration can be obtained.

Further, according to the present invention, since the semiconductor substrate is provided with the diffusion layer of the second conductivity type and is connected to the lowermost layer of the active region, it is easy to take out the electrode of the lowermost layer of the active region which is one of the source / drain regions. Becomes Further, this diffusion layer can be used as it is as a wiring.

Further, according to the present invention, since the metal silicide layer is formed on the surface of the diffusion layer connected to the lowermost layer of the active region, the resistance of the electrode extraction layer of the lowermost layer of the active region can be reduced. In particular, when the diffusion layer is used as a wiring, the wiring has low resistance and is effective. Further, since the metal silicide layer is not formed in the portion in contact with the active region, good epitaxial growth can be performed when the active region is formed by epitaxial growth after forming the metal silicide layer in the manufacturing process.

Further, in the semiconductor device according to the present invention, since the active region is composed of the epitaxial layer, the high-quality semiconductor layers are stably laminated, and the highly reliable active region vertically laminated is obtained.

Further, according to the present invention, the channel region is formed of an epitaxial layer made of a compound of Si and Ge. Since the compound of Si and Ge has a high hole mobility, high speed can be achieved especially in a p-channel transistor.

Further, in the method for manufacturing a semiconductor device according to the present invention, after forming an interlayer insulating film, a transistor opening is formed in this interlayer insulating film, an active region is epitaxially grown therein, and then a gate electrode opening is formed. Forming a gate insulating film and a gate electrode therein. Therefore, the active region is formed into a cylindrical shape,
A structure in which a gate electrode is provided inside and an interlayer insulating film is provided outside can be easily realized. Therefore, the subthreshold characteristic is improved, and a high-performance and highly integrated semiconductor device can be easily manufactured.

Further, in the semiconductor device according to the present invention, a wiring film is formed from the active region in the transistor opening to the interlayer insulating film, and the wiring film and the two layers from the active region are continuously penetrated. A gate electrode opening is formed. Therefore, the wiring film can be surely connected and formed on the uppermost layer of the active region serving as the source / drain region. Furthermore, since the gate insulating film is also formed on the surface of the wiring film, the gate electrode and the wiring film can be reliably insulated. Also, after forming the wiring film,
Since the gate electrode opening is formed and then the gate insulating film is formed, the semiconductor device as described above can be easily manufactured.

Further, in the semiconductor device according to the present invention, since the wiring film connected to the uppermost layer of the active region is formed in the recess provided in the interlayer insulating film, there is no step due to the wiring film on the surface of the interlayer insulating film and the gate electrode is formed. Patterning is facilitated during formation and reliability is improved. Further, when the wiring film is formed in the recess, it is formed by forming a conductive film on the entire surface and then leaving it only in the recess to planarize the entire surface. Therefore, the semiconductor device can be easily manufactured. Also, in the previous step,
When the active region is formed in the opening for the transistor by the selective epitaxial growth, even if the selectivity is broken and Si particles are formed on the interlayer insulating film, it is not necessary to flatten the entire surface in the wiring film forming process. The Si particles are removed together with the conductive film. Therefore, the wiring film or the like is
Unnecessary short circuit due to the grains can be prevented and reliability is improved.

Further, in the method of manufacturing a semiconductor device according to the present invention, a conductive film to be a wiring film is formed in the concave portion of the interlayer insulating film, the conductive film is made to recede by etching, and an insulating film is formed on the entire surface of the conductive film. The entire surface is flattened by leaving it only in the recess. Therefore, an insulating film that is sufficiently thicker than the gate insulating film can be easily formed on the wiring film, and the parasitic capacitance can be easily reduced at the intersection of the wiring film and the gate electrode. Further, since the insulating film is formed by being buried in the recess, there is no step on the surface of the interlayer insulating film, and patterning at the time of forming the gate electrode becomes easy.

Further, in the semiconductor device according to the present invention, since the gate electrode opening is formed in the active region in the transistor opening in a self-aligning manner, there is no variation in the shape of the transistor due to mask misalignment and the like, which is stable. A highly reliable semiconductor device having performance can be obtained. In addition, an active region is formed lower than the surface of the interlayer insulating film in the transistor opening, a sidewall of a Si nitride film is formed on the inner wall of the transistor opening, and the sidewall is used as a mask to form a gate electrode. Forming an opening for use. Therefore, the gate electrode opening can be easily formed in a self-aligned manner, and the highly reliable semiconductor device having the stable shape and performance as described above can be easily manufactured.

Further, in the method for manufacturing a semiconductor device according to the present invention, after forming the gate electrode opening in a self-aligning manner, a recess of an interlayer insulating film is provided around the transistor opening, and a conductive film to be a wiring film is formed therein. After a film is formed, the conductive film is made to recede by etching to form an insulating film on the entire surface thereof, and then the insulating film is left only in the concave portion to planarize the entire surface. Therefore, it is possible to easily manufacture a highly reliable semiconductor device having a stable shape and performance, and having a reduced parasitic capacitance at the intersection of the wiring film and the gate electrode.

Further, in the method for manufacturing a semiconductor device according to the present invention, the transistor opening is formed in a part of the recessed region of the interlayer insulating film, and the sidewall of the Si nitride film is formed on the inner wall of the transistor opening to perform self-alignment. To form an opening. This opening is filled with a buried layer of a Si oxide film, and then an active region is formed under the recess and a wiring film is formed in the recess around the buried layer, and then the buried layer of the Si oxide film is formed. Is removed using a resist mask and the opening is opened again to form a gate electrode opening. In this way, the opening is formed in the opening for the transistor in a self-aligning manner, and then the buried layer of the Si oxide film buried in the opening is removed using the resist mask to form the opening for the gate electrode. To do. Since the upper portion of the buried layer of the Si oxide film is surrounded by the wiring film formed in the recess, the pattern of the resist mask used when removing the buried layer of the Si oxide film is
The margin for mask alignment at the time of formation is very large.
Therefore, the buried layer of the Si oxide film in the opening is surely removed, so that the gate electrode opening formed thereby has the same value as that formed in the transistor opening in a self-aligned manner. Therefore, there is no variation in the shape of the transistor, and a highly reliable semiconductor device having stable performance can be obtained.

Further, in the semiconductor device according to the present invention, since the wiring film connected to the uppermost layer of the active region is provided with the insulating film sufficiently thicker than the gate insulating film in the upper layer,
The parasitic capacitance can be reduced at the intersection of the wiring film and the gate electrode, and the speed of the device can be increased.

Further, in the semiconductor device according to the present invention, since the active region is constituted by the diffusion layer made of the substrate semiconductor layer, the crystallinity is better than that in the case of being made of the epitaxial layer and the performance of the transistor is improved. Further, in the case of the active region formed of the epitaxial layer, if the Si oxide film remains on the surface of the semiconductor substrate, epitaxial growth is impossible and formation becomes difficult. However, such a problem does not occur, and the active region can be reliably formed.

Further, in the method for manufacturing a semiconductor device according to the present invention, a gate electrode opening is formed in a semiconductor substrate, a Si nitride film burying layer is buried therein, and an active region is formed around the Si nitride film burying layer. A substrate semiconductor layer to be a region is formed. This substrate semiconductor layer is formed by the first and second
The semiconductor substrate is etched by performing the etching twice using the side wall of the Si oxide film to form a region where the sidewall is not formed in the lower layer portion of the substrate semiconductor layer, and the lower layer portion of the substrate semiconductor layer is formed. A diffusion layer to be one of the source / drain regions is formed by ion implantation on the semiconductor substrate and the surrounding semiconductor substrate. After that, an interlayer insulating film is formed so as to surround the periphery of the active region, and a diffusion layer to be the other of the channel region and the source / drain region is formed by ion implantation. In this manner, the gate electrode on the inner side and the cylindrical active region having the interlayer insulating film on the outer side, which are vertically stacked, can be constituted by the diffusion layer formed of the substrate semiconductor layer, and the degree of integration is high, A high-performance semiconductor device having improved subthreshold characteristics and good crystallinity can be manufactured.

The semiconductor device according to the present invention is the first
A gate electrode is formed between the second interlayer insulating film and the second interlayer insulating film thereon, and the second interlayer insulating film, the gate electrode, and the first interlayer insulating film are formed in the gate electrode forming region. A transistor opening is formed linearly therethrough, and an active region in which an epitaxial layer is laminated via a gate insulating film is formed in a vertical thin film shape. Therefore, a vertical thin film transistor in which both sides of the channel region are sandwiched by gate electrodes can be obtained, the channel region can be efficiently depleted, and the subthreshold characteristic is improved. Further, since it is a vertical type, a transistor occupying area is small, a subthreshold characteristic is improved, and a high performance and highly integrated semiconductor device can be obtained.

Further, according to the present invention, since the semiconductor substrate is provided with the diffusion layer of the second conductivity type and is connected to the lowermost layer of the active region, the vertical thin film transistor in which both sides of the channel region as described above are sandwiched by the gate electrodes. It is easy to take out the electrode of the lowermost layer of the active region, which is one of the source / drain regions. Further, this diffusion layer can be used as it is as a wiring.

Further, according to the present invention, since the transistor opening is formed with a fine width having an upper limit value of 0.2 μm, the active region is a vertical thin film having a width of 0.2 μm or less, of which the channel region is included. A transistor is obtained in which both sides are sandwiched by gate electrodes. Therefore, the channel region can be fully depleted, and the subthreshold characteristic is further improved.

Further, in the method for manufacturing a semiconductor device according to the present invention, after the first interlayer insulating film, the gate electrode and the second interlayer insulating film are sequentially formed, the transistor opening is formed in a linear shape, and the inside thereof is formed. An active region is formed on the gate insulating film. Therefore, a vertical thin film transistor in which both sides of the channel region are sandwiched by the gate electrodes as described above can be easily formed, the subthreshold characteristic is improved, and a high-performance and highly integrated semiconductor device can be easily manufactured. Further, since the transistor opening is formed in a linear shape, it can be formed with a finer width than the size of the opening determined by one diameter, and a thin film transistor in which the channel region can be sufficiently depleted is easily formed. Can be formed.

[0050]

【Example】

Example 1. An embodiment of the present invention will be described below with reference to the drawings. Note that the description of the same parts as those of the conventional technique will be appropriately omitted. 1 is a sectional view showing the structure of a MIS transistor according to Embodiment 1 of the present invention. In the figure,
1 is the same as the conventional one, for example, a semiconductor substrate made of p-type Si single crystal or the like (hereinafter referred to as a substrate), 13 is an insulating film for element isolation, and 14 is an n ⁺ -type impurity as a diffusion layer formed on the substrate 13. A diffusion layer, 15 is an interlayer insulating film formed on the substrate 1, and 16 is an opening for a transistor provided in the interlayer insulating film 15 and reaching the n ⁺ -type impurity diffusion layer 14. Reference numeral 17 denotes an active region formed in the opening 16 for a transistor, in which three layers of a channel region and a source / drain region sandwiching the channel region from above and below are laminated, and 18 denotes this active region 17
In the figure, 19a and 19b are n ⁺ type epi layers as n ⁺ type semiconductor layers which become the source / drain regions, and p ⁺ type epi layers as the p type semiconductor layer which becomes the channel region.

Reference numeral 20 is a gate electrode opening provided in the center of the transistor opening 16 and penetrating the three layers of the active region 17 to reach the n ⁺ -type impurity diffusion layer 14, and 21 is an n ^+.
A conductive film for taking out the electrode of the epitaxial layer 19b, which is a wiring film formed over the n ⁺ type epitaxial layer 19b and the interlayer insulating film 15, and 22 is a wiring film 2 from the inner wall of the gate electrode opening 20.
A gate insulating film formed over the surface 1 and a gate electrode 23 formed so as to be embedded in the gate electrode opening 20 through the gate insulating film 22.

A method of manufacturing the MIS type transistor configured as described above will be described below with reference to FIGS. First, the element isolation insulating film 13 made of, for example, a Si oxide film is formed on the substrate 1 by, for example, the LOCOS method. The element isolation insulating film 13 may be formed by photolithography and etching techniques after forming a Si oxide film by the CVD method. Next, arsenic ions, for example, are implanted from above the substrate 1 by an ion implantation method, and then thermally diffused, and n
^{The +} type impurity diffusion layer 14 is formed, for example, with an arsenic concentration of 10 ¹⁹ to 10 10.
It forms to ²³ / cm ³ . The n ⁺ type impurity diffusion layer 14 serves as an electrode extraction layer of the n ⁺ type epi layer 19a which is one of the source / drain regions (FIG. 2). Next, an interlayer insulating film 15 made of, for example, a Si oxide film is formed on the entire surface of the substrate 1 by CVD.
By a method or the like, the film is formed to have a film thickness of, for example, about 900 nm (FIG. 3).

Next, a transistor opening 16 is formed in the interlayer insulating film 15 by photolithography and etching with a diameter of, for example, about 0.9 μm to expose the surface of the underlying n ⁺ -type impurity diffusion layer 14. (Fig. 4). Next, an n ⁺ type epi layer 19a is formed in the transistor opening 16 from the substrate 1 side by the selective epitaxial Si growth method, for example, with an arsenic concentration of 10 ¹⁷ to 10 ²⁰ / cm ³ and a film thickness of about 200 nm. The p-type epi layer 18 is, for example, boron concentration 1
At a film thickness of about 500 nm at 0 ¹⁶ to 10 ¹⁷ / cm ³ , and an n ⁺ type epi layer 19 b thereon, for example, an arsenic concentration of 10 ¹⁷
It is formed to a thickness of about 200 nm at about 10 ²⁰ / cm ³ and the transistor opening 16 is embedded (FIG. 5).

Next, a conductive film made of, for example, a polycrystalline Si film or a metal silicide film of titanium, tantalum, tungsten, etc. is formed on the entire surface by, for example, the CVD method, and then patterned by photolithography and etching techniques to form a transistor. A wiring film 21 is formed over the n ⁺ type epi layer 19b of the opening 16 and the interlayer insulating film 15 (FIG. 6). Next, a gate electrode opening 20 is formed in the central portion of the transistor opening 16, and the wiring film 21 and the three epi layers 18, 19a, b below the wiring film 21 are penetrated by photolithography and etching techniques. About 0.6
The surface of the underlying n ⁺ -type impurity diffusion layer 14 is exposed by opening with a diameter of μm (FIG. 7).

Next, a gate insulating film 22 made of a Si oxide film is formed by thermal oxidation on the inner wall of the gate electrode opening 20 and the surface of the wiring film 21 to a thickness of 10 to 20 nm (FIG. 8). Next, a conductive film made of, for example, a polycrystalline silicon film, a metal silicide film, or a laminated film thereof is formed on the entire surface by a sputtering method or a CVD method so as to be embedded in the gate electrode opening 20, and then photolithography and etching are performed. The gate electrode 23 is patterned by the technique.
Are formed (see FIG. 1). After this, a predetermined process is performed and M
The IS type transistor is completed.

In the above-described first embodiment, the gate electrode 23 and the active region 17 composed of three laminated layers surrounding the gate electrode 23 are formed in the transistor opening 16 having a diameter of, for example, about 0.9 μm. is there. Therefore, the area occupied by the transistor is extremely small, and high integration can be achieved. Also,
In this transistor, the active region 17 is formed in a cylindrical shape, the gate electrode 23 is formed inside the active region 17, and the interlayer insulating film 1 is formed outside.
5 is provided. That is, in the channel region 18 which is the second layer from the top of the active region 17, the gate electrode 23 is formed inside and the interlayer insulating film 15 is formed outside, and the same effect as that of the SOI type transistor, that is, the subthreshold is obtained. This has the effect of improving the characteristics. As described above, according to the first embodiment, a high-performance and highly integrated MIS transistor having improved subthreshold characteristics can be obtained.

In the first embodiment, the interlayer insulating film 15 is also used.
Then, an opening 16 for a transistor is formed in the interlayer insulating film 15, an active region 17 is epitaxially grown therein, and then an opening 20 for a gate electrode is formed therein, and a gate insulating film 22 and The gate electrode 23 is formed. Therefore, it is possible to easily form a structure in which the active region 17 is formed in a cylindrical shape, the gate electrode 23 is arranged inside, and the interlayer insulating film 15 is arranged outside, so that the subthreshold characteristic is improved and the performance is high and the degree of integration is high. A semiconductor device can be easily manufactured.

Further, in the first embodiment, since the substrate 1 is connected to the n ⁺ type epi layer 19a provided with the n ⁺ type impurity diffusion layer 14, the n ⁺ type epi layer 1 which is the bottom layer of the active region is connected.
The electrode of 9a can be taken out easily. The n ⁺ -type impurity diffusion layer 14 can also be used as a wiring as it is.

In the first embodiment, after forming the active region 17 in the transistor opening 16, the wiring film 21 is continuously formed, and then the wiring film 21 and the active region 17 are continuously penetrated. After forming the gate electrode opening 20, the gate insulating film 22 and the gate electrode 23 are formed. Therefore, the wiring film 21 connected to the n ⁺ type epi layer 19b
Can be easily formed, and the electrode of the n ⁺ type epi layer 19b can be reliably taken out. In addition, the gate insulating film 22 can be formed on the surface of the wiring film 21 at the same time, and the gate electrode 23 and the wiring film 21 formed thereafter can be easily and surely insulated.

In the first embodiment described above, the case of the n-channel type transistor is shown, but the same can be applied to the p-channel type transistor. Alternatively, the gate insulating film 22 may be a Si oxynitride film that is nitrided by heat treatment in a nitriding atmosphere during formation.

Further, the three epi layers 18, 19a, b constituting the active region 17 may be made of a compound of Si and Ge. Since the compound of Si and Ge has a high hole mobility, the speed can be increased especially in a p-channel transistor. In this case, three epi layers 18,
It suffices that the p-type epi layer 18 serving as the channel region of 19a and 19b is a compound of Si and Ge. Further, in order to obtain a good quality gate insulating film 22, the gate insulating film 22 is formed by the CVD method. Is desirable. Further, as the active region 17, a polycrystalline Si film formed by a CVD method or the like can be used, but an epi layer 18 formed by selective epitaxial growth,
Higher performance transistors can be obtained by using 19a and 19b. In addition, when the epi layers 18, 19a and b are used, the substrate 1
Even when a diffusion layer formed by ion implantation or the like is stacked, the active region 17 of high quality can be stably formed without complicated conditions.

In the first embodiment, after the transistor opening 16 is formed in the interlayer insulating film 15, for example, n-type arsenic or phosphorus ions are implanted from the substrate 1 by ion implantation at an implantation energy of several tens KeV. Quantity 10 ¹⁴ to 10 ¹⁶
You may add the process of injecting in / cm < ² >. This allows
Even when the transistor opening 16 is opened through the element isolation insulating film 13 due to misalignment of photolithography, the transistor opening 16 is opened.
Since the n ⁺ -type impurity diffusion layer 14 is formed on the lower substrate 1, generation of a leak current between the transistor and the substrate 1 is prevented, and element isolation can be reliably performed.

Example 2. Next, the structure of the MIS type transistor according to the second embodiment of the present invention will be described with reference to FIG. As shown in the figure, an insulating film 24 is formed on the wiring film 21 connected to the n + ^type epi layer 19b.

A method of manufacturing the MIS type transistor thus configured will be described below with reference to FIG. First, in the same manner as in Example 1, the element isolation insulating films 13, n were formed on the substrate 1.
^{After the +} type impurity diffusion layer 14 and the interlayer insulating film 15 are sequentially formed, the transistor opening 16 is opened, and the three epitaxial layers 18, 19a are formed in the transistor opening 16.
b is formed (see FIGS. 2 to 5). Next, CVD is performed on the entire surface.
The conductive film, which is made of, for example, a polycrystalline Si film or a metal silicide film, and becomes the wiring film 21, is formed by about 15
The insulating film 24 made of, for example, a Si oxide film is formed to a thickness of about 150 nm over the entire surface of the insulating film 24. After that, the pattern of the insulating film 24 and the wiring film 21 thereunder is formed by photolithography and etching techniques (FIG. 10A).

Thereafter, as in the first embodiment, the gate electrode opening 20 is formed (FIG. 10B), and the gate insulating film 2 is formed.
2 (FIG. 10C), the gate electrode 23 is formed so as to be embedded in the gate electrode opening 20 (FIG. 9C).
reference). After that, predetermined processing is performed to complete the MIS type transistor.

In the second embodiment, the same effect as in the first embodiment is obtained, and since the insulating film 24 which is sufficiently thicker than the gate insulating film 22 is formed on the wiring film 21, the wiring film 21 and the gate are formed. At the intersection with the electrode 13,
The parasitic capacitance can be reduced, and the speed of the device can be increased.

Example 3. Next, the structure of the MIS type transistor according to the third embodiment of the present invention will be described with reference to FIG. In the figure, 1 and 13 to 23 are the same as those in the first embodiment, 25 is a recess provided in the interlayer insulating film 15, the wiring film 21 is embedded in this recess 25, and further, a part of this recess 25 region is formed. A transistor opening 16 is formed so as to penetrate the lower interlayer insulating film 15.

A method of manufacturing the MIS type transistor having the above structure will be described below with reference to FIGS. First, in the same manner as in Example 1, the element isolation insulating film 13 and the n ⁺ -type impurity diffusion layer 14 are formed on the substrate 1 (see FIG. 2). Next, an interlayer insulating film 15 made of, for example, a Si oxide film is formed on the entire surface of the substrate 1 by the CVD method or the like. At this time, the interlayer insulating film 15 is formed so that its film thickness becomes thicker than that of the first embodiment (about 900 nm) by the film thickness of the wiring film 21 (for example, about 150 nm) formed in a later step (for example, about 150 nm). (Fig. 12).

Next, a recess 25 is formed in the interlayer insulating film 15 by photolithography and etching techniques (FIG. 13). Next, an opening 16 for a transistor is formed in a portion of the recess 25 of the interlayer insulating film 15 by photolithography and etching to have a diameter of, for example, about 0.9 μm, and the underlying n ⁺ -type impurity diffusion layer 14 is formed. The surface of is exposed (FIG. 14A). A plan view of the step shown in FIG. 14A is shown in FIG. Next, in the same manner as in Example 1, three epitaxial layers 1 in the opening 16 for the transistor are formed.
8, 19a, b are formed, and then a conductive film 21a made of, for example, a polycrystalline Si film or a metal silicide film is formed on the entire surface by a CVD method so as to be embedded in the recess 25 (FIG. 1).
5).

Next, the unnecessary conductive film 21a is removed by a resist etch-back method or a polishing method to flatten the entire surface to form the wiring film 21 embedded only in the recess 25 (FIG. 16). Next, in the same manner as in Example 1, the gate electrode opening 20 is formed (FIG. 17), and the gate insulating film 22 is formed.
After forming (FIG. 18), the gate electrode 23 is formed so as to be embedded in the gate electrode opening 20 (see FIG. 11). After that, predetermined processing is performed to complete the MIS type transistor.

In the third embodiment, as in the first embodiment,
The n ⁺ type epi layer 1 serving as one of the source / drain regions with improved subthreshold characteristics and integration degree
Since the wiring film 21 connected to 9b is formed by being embedded in the recess 25 provided in the interlayer insulating film 15, there is no step around the gate electrode opening 20 and the patterning of the gate electrode 23 is easy. You can do it. Further, since such a wiring film 21 is formed by forming a conductive film on the entire surface and then leaving it only in the recess 25 to planarize the entire surface, it can be easily formed.

Further, in the selective epitaxial growth for forming the active region 17, the selectivity may be broken and an island-shaped Si film which is a grain or a group thereof may be formed on the interlayer insulating film 15. In the process of forming 21
When the conductive film 21a other than the inside is removed and planarized, the granular or island-shaped Si film can also be removed. Therefore, the wiring film 21 and the like are prevented from being unnecessarily short-circuited by the Si film, and the reliability is improved.

Example 4. The insulating film 24 may be formed on the wiring film 21 of the MIS type transistor shown in the third embodiment as in the second embodiment. FIG. 19 is a sectional view showing the structure of the MIS type transistor according to Embodiment 4 of the present invention. As shown in the figure, the insulating film 24 is formed on the wiring film 21.
Is formed and embedded in the recess 25 together with the wiring film 21.

A method of manufacturing the MIS type transistor thus configured will be described below with reference to FIG. First, in the same manner as in Example 3, the element isolation insulating film 13 and n ^{+ were} formed on the substrate 1.
After the type impurity diffusion layer 14 and the interlayer insulating film 15 are sequentially formed, a recess 25 is formed in the interlayer insulating film 15, and an opening 16 for a transistor is opened to form three epitaxial layers 18, 19a, b. To form. Further, the conductive film 2 is formed on the entire surface.
After forming 1a so as to be embedded in the recess 25, the conductive film 21a is left only in the recess 25 and the others are removed to planarize the entire surface (see FIGS. 12 to 16).

Next, the conductive film 21a is etched and receded using the interlayer insulating film 15 as a mask to form the wiring film 21 (FIG. 20A). Next, an insulating film 24 made of, for example, a Si oxide film is formed on the entire surface by the CVD method (FIG. 2).
0 (b)). Next, the unnecessary insulating film 24 is removed by a resist etch-back method or a polishing method to planarize the entire surface and leave the insulating film 24 only in the recess 25 (FIG. 20).
(C)). Next, in the same manner as in Example 3, the gate electrode opening 20 is formed (FIG. 20D), and the gate insulating film 2 is formed.
After forming 2, the gate electrode 23 is formed so as to be embedded in the gate electrode opening 20 (see FIG. 19). After that, predetermined processing is performed to complete the MIS type transistor.

In the fourth embodiment, the wiring film 21 having the insulating film 24 formed thereon can be easily embedded in the recess 25 together with the insulating film 24.
Both effects of the above and the third embodiment are exhibited.

Example 5. Next, a method of forming a silicide layer on the n ⁺ type impurity diffusion layer 14 formed on the substrate 1 will be described below with reference to FIG. Examples 1 to 4 above
Similarly, after forming the element isolation insulating film 13 and the n ⁺ -type impurity diffusion layer 14 on the substrate 1 (see FIG. 2), the whole surface is made of, for example, titanium, cobalt or the like, and reacts with Si to have a high melting point (1000 ° C.). Above) Metal film 26 forming a silicide film
a is formed by a sputtering method or a CVD method (FIG. 21).
(A)). Next, the substrate 1 is heat-treated to react the metal film 26a formed on the Si layer with the underlying Si, and then unreacted with, for example, an acid-based etching solution containing hydrogen peroxide solution as a main component. Of the metal silicide layer 26a on the n ⁺ -type impurity diffusion layer 14 by etching away the metal film 26a of
Are formed (FIG. 21B).

Next, the interlayer insulating film 15 is formed in the same manner as in the first to fourth embodiments, and the transistor opening 16 is formed. At this time, the transistor opening 16 also penetrates the metal silicide layer 26, and the underlying n ⁺ -type impurity diffusion layer 14 is formed.
Is formed so as to expose. This metal silicide layer 26
Is removed by selective epitaxial growth in the transistor opening 16 in a later step.
It is for allowing b to grow. When CoSi ₂ or NiSi ₂ is used for the metal silicide layer 26, it can be epitaxially grown on the metal silicide layer 26, but the Si substrate surface (n ⁺ type impurity diffusion layer 14)
Of the epi layers 18, 19a,
b is of good quality with no crystal defects. In this step, the case where the recess 25 is provided in Embodiments 3 and 4 is shown, but the same is true when the recess 25 is not provided (FIG. 21C). Then, the MIS type transistor is completed in the same manner as in the first to fourth embodiments.

In the fifth embodiment, the n ⁺ type impurity diffusion layer 1 is used.
Since the metal silicide layer 26 is formed on the electrode 4, the resistance of the electrode extraction layer of the n ⁺ type epi layer 19a can be reduced. In particular,
When the n ⁺ -type impurity diffusion layer 14 is used as a wiring, the resistance of the wiring can be reduced, which is effective.

In the fifth embodiment, the metal film 2 is formed on the entire surface.
After forming 6a, the metal silicide layer 26 is formed.
For example, a metal film of tungsten or the like may be selectively formed on the Si substrate surface (n + ^-type impurity diffusion layer 14) by the selective CVD method, and then the metal silicide layer 26 may be transformed by heat treatment. Alternatively, the metal silicide layer 26 may be directly and selectively formed by the selective CVD method.

Example 6. Although the gate insulating film 22 is formed by the thermal oxidation method in the above embodiments, it may be formed by the CVD method, which will be described below with reference to FIG. For example, in the same manner as in Example 4, the step shown in FIG. 20 is completed to form the gate electrode opening 20, and then the gate insulating film 22 is formed on the entire surface by the CVD method. The gate insulating film 22 is, for example, a Si oxide film, but may be a film having a high dielectric constant such as a Si nitride film or a tantalum oxide film, or a multilayer film thereof (FIG. 22A). Next, the gate electrode 23 is formed similarly to the fourth embodiment (FIG. 22B), and then a predetermined process is performed to complete the MIS type transistor. Although the fourth embodiment is used here, the gate insulating film 2 is similarly formed by the CVD method in the other embodiments.
2 can be formed.

Example 7. Next, the structure of the MIS type transistor according to Embodiment 7 of the present invention will be described with reference to FIG. In the figure, 1, 13 to 23, and 25 are the same as those in the first to sixth embodiments. As shown in the figure, the transistor opening 16 is formed in the interlayer insulating film 15 so as to penetrate therethrough.
Is provided in the opening 16 for the transistor, and the active region 17 composed of the three-layer epi layers 18, 19a, and b is buried to a height lower than that of the interlayer insulating film 15. Interlayer insulating film 1 so as to surround
5 is provided with a concave portion 25 so that the wiring film 21a embedded in the concave portion 25 is in contact with the side surface of the n ⁺ type epi layer 19b. In addition, a gate electrode opening 20 is formed in the center of the active region 17 in a self-aligning manner. The gate electrode opening 20 is formed from two layers of the n ⁺ type epilayers 19b and p from the top of the active region.
It penetrates through the epitaxial layer 18 and is opened so as not to reach the n ⁺ -type impurity diffusion layer 14.

A method of manufacturing the MIS type transistor thus configured will be described below with reference to FIGS. First, in the same manner as in Example 1, after forming the element isolation insulating film 13, the n ⁺ -type impurity diffusion layer 14 and the interlayer insulating film 15 on the substrate 1, the transistor opening 16 is formed in the interlayer insulating film 15. It is formed by photolithography and etching techniques to expose the surface of the underlying n ⁺ -type impurity diffusion layer 14 (FIG. 24). Next, the n ⁺ type epi layer 19a, the p type epi layer 18 and the n ⁺ type epi layer 19b are formed from the substrate 1 side in the transistor opening 16 by the selective epitaxial Si growth method. At this time, the three epi layers 18, 19
The heights of a and b, that is, the height of the surface of the n ⁺ -type epi layer 19b are formed to be, for example, 100 to 200 nm lower than that of the interlayer insulating film 15 (FIG. 25).

Next, a Si nitride film is formed on the entire surface by the CVD method to have a film thickness of, for example, about 150 nm, and the entire surface is etched back to form the interlayer insulating film 1 on the inner wall of the transistor opening 16.
A nitride film sidewall 27 as a sidewall of the Si nitride film is formed on the exposed portion of 5 (FIG. 26). next,
Using the interlayer insulating film 15 and the nitride film sidewall 27 as a mask, the n ⁺ type epi layer 19a is formed in the central portion of the transistor opening 16 so as to penetrate the two layers from above the active region 17.
Opening 20 for the gate electrode is formed (see FIG. 2).
7).

Next, a Si nitride film is formed on the entire surface so as to fill the inside of the gate electrode opening 20, and then S on the interlayer insulating film 15 is formed by a resist etch back method or a polishing method.
The i-nitride film is removed and planarized to form a nitride film burying layer 28 as a Si nitride film burying layer (FIG. 28).
Next, a resist pattern 2 is formed by photolithography.
9 is formed, and the resist pattern 29 and the Si nitride film (nitride film sidewall 2 in the transistor opening 16) are formed.
7 and the nitride film burying layer 28) as a mask, the interlayer insulating film 15 is removed by etching, and a recess 25 is formed so as to surround the periphery of the upper layer of the transistor opening 16.
As a result, the uppermost n ⁺ type epi layer 19 of the active region 17 is formed.
The side surface of the upper layer portion of b is exposed (FIG. 29).

Then, after removing the resist pattern 29 by ashing or the like, a conductive film 21a made of, for example, a polycrystalline Si film or a metal silicide film is formed on the entire surface so as to fill the recess 25 (FIG. 30). Then, the unnecessary conductive film 21a is removed by a resist etch-back method or a polishing method to flatten the entire surface to form the wiring film 21 embedded only in the recess 25 (FIG. 31).

Next, the nitride film burying layer 28 and the nitride film sidewall 27 are selectively removed by wet etching using hot phosphoric acid, and then the gate insulating film 22 is formed by a thermal oxidation method (FIG. 32). . Next, Example 1
Similarly, the gate electrode 23 is formed so as to fill the gate electrode opening 20 (see FIG. 23), and then predetermined processing is performed to complete the MIS transistor.

The seventh embodiment has the same effects as those of the third embodiment, and the gate electrode opening 20 is formed.
The self-alignment is performed by using the nitride film side wall 27 formed on the inner wall of the transistor opening 16. Therefore, there is no variation in transistor shape due to mask misalignment or the like. Therefore, variations in performance are prevented and a highly reliable MIS transistor can be obtained, and such a MIS transistor can be easily manufactured.

In the seventh embodiment, the gate electrode opening 20 is formed so as to penetrate the two layers from above the active region 17 and reach the n ⁺ type epi layer 19a. Although the gate electrode opening 20 is opened to reach the substrate 1 (n ⁺ -type impurity diffusion layer 14) in the above-described first to sixth embodiments, it does not penetrate through the two layers from above the active region 17. Is sufficient and both are equally applicable.

Example 8. A case where the insulating film 24 is formed on the wiring film 21 of the MIS transistor shown in the seventh embodiment and is embedded in the recess 25 together with the wiring film 21 in the same manner as in the fourth embodiment will be described below with reference to FIG. Shown in.
First, in the same manner as in Example 7, the steps shown in FIGS. Next, the interlayer insulating film 15 and the Si nitride film (the nitride film sidewall 27 and the nitride film burying layer 28)
Using the as a mask, the conductive film 21a is etched and receded to form the wiring film 21 (FIG. 33A).

Next, an insulating film 24 made of, for example, a Si oxide film is formed on the entire surface by a CVD method, and the insulating film 24 is removed by a resist etch back method or a polishing method to planarize the entire surface, so that only the recess 25 is formed. The insulating film remains (Fig. 3
3 (b)). Next, in the same manner as in Example 7 described above, after removing the nitride film sidewall 27 and the nitride film burying layer 28, the gate insulating film 22 is formed (FIG. 33C),
After that, the same processing as that of the above-described seventh embodiment is performed to complete the MIS type transistor.

The eighth embodiment has the same effects as those of the seventh embodiment, and the insulating film 2 is the same as the fourth embodiment.
4 can be easily embedded in the recess 25 on the wiring film 21, the parasitic capacitance at the intersection of the wiring film 21 and the gate electrode 23 can be reduced, and the speed of the device can be increased.

Example 9. Next, a method of manufacturing a MIS type transistor according to Embodiment 9 of the present invention will be described below with reference to FIGS. First, similarly to the third embodiment, the element isolation insulating film 13, the n ⁺ -type impurity diffusion layer 14 and the interlayer insulating film 15 are formed on the substrate 1, and the recess 25 is formed in the interlayer insulating film 15 (FIG. 12). , See FIG. 13). Next, a Si nitride film is formed on the entire surface by a CVD method so as to be embedded in the recess 25, and then the Si nitride film is removed by a resist etch back method or a polishing method to planarize the entire surface to form a Si nitride film embedded layer. A nitride film burying layer 30 is formed (FIG. 34).

Next, a transistor opening 16 is formed in a portion of the recess 25 region by photolithography and etching techniques, and a nitride film burying layer 30 and an interlayer insulating film 15 are formed.
To expose the surface of the n ⁺ -type impurity diffusion layer 14 (FIG. 35). Next, a Si nitride film is formed on the entire surface by a CVD method so as to fill the inside of the transistor opening 16, and anisotropic etching is performed. The nitride film sidewall 31 is formed to have a width of 150 nm, for example (FIG. 36).

Next, a Si oxide film is formed on the entire surface by the CVD method so as to fill the inside of the opening 16 for the transistor, then flattened by the resist etch back method or the polishing method, and the upper layer portion of the nitride film side wall 31. The entire surface is etched until the narrow portion is removed to make the width of the nitride film side wall 31 in the transistor opening 16 constant, and the oxide film burying layer as a burying layer of the Si oxide film is formed therein. 32 is formed (FIG. 37). Next, the nitride film burying layer 30 and the nitride film sidewall 31 are selectively removed by wet etching using hot phosphoric acid (FIG. 38).

Next, the n ⁺ type epi layer 19a, the p type epi layer 18 and the n ⁺ type epi layer 19b are introduced into the transistor opening 16 from the substrate side by the selective epitaxial Si growth method.
To form an active region 17 under the recess 25 around the oxide film burying layer 32. Then, a conductive film made of polycrystalline Si or a metal silicide film is formed on the entire surface by CVD.
Is formed so as to fill the inside of the recess 25 by a method, the conductive film is removed by a resist etch back method or a polishing method to planarize the entire surface, and the wiring film 21 is formed in the recess 25 so as to surround the oxide film filling layer 32. Are formed (FIG. 39).

Next, a resist pattern 33 is formed by the photolithography technique, and the resist pattern 33 is formed.
The oxide film burying layer 32 is removed by etching using the mask as a mask to form the gate electrode opening 20. At this time,
The opening of the resist pattern 33 is formed in the oxide film burying layer 32.
It suffices if it surrounds the formation region of the wiring film 21 and is within the formation region of the wiring film 21 (FIG. 40). Next, after removing the resist pattern 33 by ashing or the like, the gate insulating film 22 and the gate electrode 23 are formed in the same manner as in the third embodiment (see FIG. 11), and then a predetermined process is performed to perform the above process. A MIS type transistor similar to that of the third embodiment is completed.

In the ninth embodiment, the nitride film sidewall 31 is formed on the side wall inside the transistor opening 16 to form the opening in a self-aligned manner. This opening is formed by burying the oxide film burying layer 32 therein, forming the active region 17 around the oxide film burying layer 32, then removing the oxide film burying layer 32, and opening again to become the gate electrode opening 20. . When removing the oxide film burying layer 32, a resist pattern 33 formed by a photolithography technique is used.
Since the mask alignment margin is large, for example, about 0.2 μm, it can be sufficiently aligned. Therefore, the gate electrode opening 20 becomes a self-aligned region in the transistor opening 16, and a highly reliable MIS transistor without variations in shape and performance is formed as in the case of the seventh embodiment. can get.

Example 10. Next, Example 10 of the present invention
The structure of the MIS type transistor according to the above will be described with reference to FIG. In the figure, 1, 15, 20 to 23, and 2
Reference numeral 5 is the same as in Embodiments 1 to 9 above, reference numeral 34 is a substrate semiconductor layer formed so as to surround the periphery of the gate electrode opening 20, and includes a channel region and a source / drain region sandwiching the channel region from above and below. The active region of the transistor in which the layers are laminated, and 35 is one of the source / drain regions n ⁺
Type diffusion layer, 36 is a p type diffusion layer serving as a channel region, 37
Is an n ⁺ type diffusion layer which is the other of the source / drain regions, 3
Reference numeral 8 is an oxide film formed in a thin width between the active region 34 and the interlayer insulating film 15 around it.

A method of manufacturing the MIS type transistor having such a structure will be described below with reference to FIGS. 42 to 52. First, the gate electrode opening 20 is formed on the substrate 1 by the photolithography and etching techniques, and then a Si nitride film is formed on the entire surface by the CVD method so as to fill the inside of the gate electrode opening 20. Alternatively, the unnecessary Si nitride film is removed by a polishing method to be planarized, and a nitride film burying layer 39 as a burying layer of the Si nitride film is formed only in the gate electrode opening 20 (FIG. 42).
Next, the entire surface of the substrate 1 is etched back so that the upper portion of the nitride film burying layer 39 is projected by, for example, about 200 nm (FIG. 4).
3).

Next, a Si oxide film is formed on the entire surface by the CVD method, and then the entire surface is etched back to form the nitride film burying layer 3
A first oxide film sidewall 40 is formed on the side surface of the protruding portion 9 of, for example, a width of 100 to 200 nm (FIG. 44). Next, the substrate 1 is etched to a thickness of, for example, about 600 nm by using the first oxide film sidewall 40 and the nitride film burying layer 39 as a mask. As a result, the oxide film burying layer 3
First oxide film side wall 40 so as to surround the periphery of
A substrate semiconductor layer 34a is formed underneath (FIG. 45). Next, a Si oxide film is formed on the entire surface by the CVD method and then etched back to form a second oxide film sidewall 38a around the first oxide film sidewall 40 and the underlying substrate semiconductor layer 34a. (FIG. 46).

Next, the substrate 1 is etched to a thickness of, for example, about 200 nm using the first and second oxide film sidewalls 40 and 38a and the nitride film burying layer 39 as a mask to form sidewalls around the substrate. The substrate semiconductor layer 34a including the lower layer portion which is not formed is formed (FIG. 47). Next, the resist pattern 41 is formed by photolithography.
Then, using the resist pattern 41 as a mask, n-type impurity ions such as phosphorus are implanted from above the substrate 1 at an implantation energy of several tens to several hundreds KeV and an implantation dose of 10 ¹⁵ to 10 ^16.
/ Cm is injected from obliquely with ^2, for example, 45 ° angle of inclination (Figure 48). Next, after removing the resist pattern 41 by ashing or the like, the substrate 1 is subjected to heat treatment, for example, 9
This is performed at 00 ° C. for about 1 hour to form the n ⁺ type diffusion layer 35 from the lower layer portion of the substrate semiconductor layer 34a to the substrate 1 around it (FIG. 49).

Next, after forming an interlayer insulating film 15 made of a Si oxide film on the entire surface, the unnecessary interlayer insulating film 15 is removed by a resist etch back method or a polishing method to planarize it.
Further, the nitride film burying layer 39 and the first and second oxide film sidewalls 40 and 38a are removed and planarized until the surface of the substrate semiconductor layer 34a is exposed. This makes the first
Oxide film sidewalls 40 are completely removed, and the second oxide film sidewalls 38a are removed only in the upper layer to become the oxide film 38. Next, p-type impurity ions such as boron are implanted from above the substrate 1 at an implantation energy of several tens KeV.
100 KeV, injection amount; injection at 10 ¹³ to 10 ¹⁴ / cm ² ,
Further, for example, an n-type impurity ion such as phosphorus is implanted at an energy of 100 KeV to several hundred KeV and an implantation dose of 10 ¹⁵ to 10 ^16.
/ Cm ² and then heat-treating the substrate 1 to, for example, 90
Apply at 0 ° C for about 20 minutes. Thereby, the substrate semiconductor layer 34a
A p-type diffusion layer 36 is formed on the n ⁺ -type diffusion layer 35, and an n ⁺ -type diffusion layer 37 is further formed thereon to form the active region 34 (FIG. 50).

Next, by photolithography and etching techniques, the interlayer insulating film 15 is removed to form the recess 25 so as to surround the periphery of the upper layer portion of the active region 34. As a result, the upper surface of the n ⁺ type diffusion layer 37, which is the uppermost layer of the active region 34, is exposed (FIG. 51). Next, the wiring film 21 is embedded in the recess 25 as in the case of the seventh embodiment (FIG. 5).
2). Next, after the nitride film burying layer 39 is selectively removed by wet etching using hot phosphoric acid to open the gate electrode opening 20, the gate insulating film 22 and the gate electrode 23 are formed as in the third embodiment. Are formed (see FIG. 41), and then predetermined processing is performed to complete the MIS type transistor.

In the tenth embodiment, as in the first embodiment, a high performance and highly integrated MIS transistor having improved subthreshold characteristics can be obtained. Further, as in the third embodiment, since the wiring film 21 is embedded in the recess 25, the flatness is improved and the gate electrode 23 is easily formed. Furthermore, in Example 10 described above, the substrate semiconductor layer 3
The active region 34 is formed by forming three layers of diffusion layers 35, 36, 37 which will become the source / drain regions and the channel region by ion implantation in 4a. Therefore, the crystallinity is better than that of the active region 17 formed of the epi layer, and the performance of the transistor is improved. Further, in the case of the active region 17 formed of the epi layer, if the Si oxide film remains on the surface of the substrate 1, epitaxial growth is impossible and formation becomes difficult. it can.

Example 11. Next, a vertical thin film transistor in which both sides of the channel region are sandwiched by gate electrodes can be formed by applying the ones shown in the first to tenth embodiments, which will be described below. By the way, a dual-gate transistor in which both sides of a channel region are sandwiched by two gate electrodes, a top gate and a bottom gate, is known as the Japan Society of Applied Physics 19
Spring 1990 P. 640A. O. As described in Adan et al., The depletion of the channel region can be efficiently performed by applying the voltage simultaneously to the top gate and the bottom gate, and the subthreshold characteristic can be improved. That is, a transistor in which one gate electrode is formed so as to sandwich both sides of the channel region has the same effect. In addition, the thin film transistor is referred to by the Society of Applied Physics 1988 Autumn P. 656 Yamaguchi et al.
By setting the thickness to 1 μm or less, the entire channel region can be depleted. That is, by forming the gate electrode so as to sandwich both sides of the channel region, the thickness is doubled to 0.
Even if the thickness is 2 μm or less, the channel region can be sufficiently depleted,
Subthreshold characteristics are improved.

FIG. 53 shows an M according to the eleventh embodiment of the present invention.
The structure of the IS transistor is shown in FIG.
Is a sectional view, and FIG. 53 (b) is a plan view of a main pattern. In the figure, reference numerals 1, 13 and 14 are the same as those in the first embodiment, 42 is a first interlayer insulating film, 43 is a gate electrode formed on the first interlayer insulating film 42, and 44 is a gate electrode 43. Is a second interlayer insulating film formed on the first interlayer insulating film 42. Reference numeral 45 is a transistor opening provided in the gate electrode 43 formation region in a U shape penetrating the second interlayer insulating film 44, the gate electrode 43, and the first interlayer insulating film 42, and 46 is a transistor opening. The gate insulating film 47 formed on the inner wall of the portion 45 is formed as a thin film in the vertical direction by stacking three layers of a channel region and a source / drain region sandwiching the channel region in the vertical direction in the transistor opening 45. The active region 48 is a p-type epi layer serving as a channel region in the active region 47, 49a and b are n ⁺ type epi layers serving as source / drain regions, and 50 is connected to the n ⁺ type epi layer 49b. It is a wiring film.

A method of manufacturing the MIS type transistor thus configured will be described below with reference to FIGS. 54 to 58.
First, similarly to the first embodiment, the element isolation insulating film 13 and the n ⁺ -type impurity diffusion layer 14 are formed on the substrate 1. After that, a first interlayer insulating film 42 made of a Si oxide film is formed on the entire surface by a CVD method, and a polycrystalline S film is further formed on the entire surface.
A conductive film made of an i film or a metal silicide film is formed by the CVD method, and the conductive film is patterned by photolithography and etching techniques to form the gate electrode 43. At this time, the gate electrode 43 is thickly formed in the portion which will be the transistor formation region (FIG. 54A). A plan view of the step shown in FIG. 54 (a) is shown in FIG. 53 (b).

Next, a second interlayer insulating film 44 made of a Si oxide film is formed on the entire surface by the CVD method (FIG. 55). Next, the U-shaped transistor opening 4 is formed in the region where the gate electrode 43 is formed by photolithography and etching techniques.
5 is opened through the second interlayer insulating film 44, the gate electrode 43, and the first interlayer insulating film 42 to expose the surface of the n ⁺ -type impurity diffusion layer 14. At this time, the width of the transistor opening 45 is formed to be 0.2 μm or less (FIG. 56).

Next, an insulating film made of a Si oxide film or a Si nitride film or a laminated film thereof is formed on the entire surface by a CVD method so as to fill the transistor opening 45, and is etched by anisotropic etching to form a transistor. A side wall is left on the inner wall of the opening 45 for forming a gate insulating film 46 (FIG. 57). Next, as in the first embodiment, the n ⁺ type epi layer 49a which becomes one of the source / drain regions and the p type which becomes the channel region are formed from the substrate 1 side in the opening 45 for the transistor by the selective epitaxial Si growth method. An epi layer 48 and an n ⁺ type epi layer 49b to be the other of the source / drain regions are formed (FIG. 58).

Next, a conductive film made of a polycrystalline Si film or a metal silicide film is formed on the entire surface and patterned by photolithography and etching techniques to form the wiring film 5.
0 is formed (see FIG. 53). Then, predetermined processing is performed to complete the MIS type transistor.

In the eleventh embodiment, a U-shaped transistor opening 45 having a width of 0.2 μm or less is provided in the gate electrode 43 forming region, and the active region 47 is formed in a vertical thin film shape therein. As a result, a vertical thin film transistor having a thickness of 0.2 μm or less sandwiching both sides of the channel region between the gate electrodes is formed. In the conventional vertical transistor as shown in FIG. 62, the width of the channel region is about 0.8 to 1.0 μm, which is equivalent to that of the contact hole, so it is difficult to sufficiently deplete the channel region during transistor operation. However, in the eleventh embodiment, since the p-type epi layer 48 serving as the channel region is formed with a width of 0.2 μm or less, it can be sufficiently depleted, the subthreshold characteristic of the transistor can be improved, and the vertical transistor can be formed. Therefore, the degree of integration is also improved. In this way, the subthreshold characteristic is improved, and a high-performance and highly integrated MIS transistor can be obtained. Also, the transistor opening 4
Since 5 is formed in a U shape, the area of the p-type epi layer 48 serving as a channel region is large, and the resistance is low during the operation of the transistor, so that the drain current can be increased and the performance of the transistor is improved.

The gate insulating film 46 shown in FIG. 57 may be formed by a thermal oxidation method as shown in FIG. Also, the transistor opening 45 may be formed in a linear shape, as shown in FIG. FIG. 60A is a cross-sectional view showing the structure of the MIS type transistor, and FIG. 60B is a plan view of the main pattern. As described above, since the transistor opening 45 is formed in a linear shape such as a U-shape or a linear shape, the transistor opening 45 can be formed with a finer width than an opening determined by one diameter. Therefore, it becomes easy to manufacture a vertical thin film transistor in which both sides of the channel region are sandwiched by the gate electrodes.

[0114]

As described above, according to the present invention, the active region including the source / channel / drain is vertically stacked in the transistor opening provided in the interlayer insulating film,
Further, since the gate electrode opening is provided in the active region and the gate electrode is formed therein, the subthreshold characteristic is improved, and a high performance and highly integrated semiconductor device can be obtained.

Further, according to the present invention, since the diffusion layer is provided on the semiconductor substrate and is connected to the lowermost layer of the active region, it is easy to take out the electrode of the lowermost layer of the active region. Further, this diffusion layer can be used as it is for wiring, which facilitates manufacturing of a semiconductor device. Further, when a silicide layer is formed on the surface of the diffusion layer, the resistance can be reduced, and particularly when the diffusion layer is used as a wiring, a wiring having a low resistance can be obtained.

Further, according to the present invention, since the active region is composed of the epitaxial layer, a good quality semiconductor layer is stably laminated to form the active region, and a highly reliable semiconductor device can be obtained. Further, if the channel region is composed of an epitaxial layer made of a compound of Si and Ge, the p-channel transistor can be made faster.

Further, according to the present invention, after the interlayer insulating film is formed, the opening for transistor is provided, the active region is formed therein by the selective epitaxial growth, and then the opening for gate electrode is formed and the gate electrode is formed therein. To form.
Therefore, the subthreshold characteristic is improved, and a high-performance and highly integrated semiconductor device can be easily manufactured.

Further, according to the present invention, a wiring film is formed over the active region and over the interlayer insulating film, and a gate electrode opening is formed which continuously penetrates the wiring film and the two layers over the active region. Since the gate insulating film is formed and the gate insulating film is also formed on the surface of the wiring film, the wiring film can be surely connected and formed in the uppermost layer of the active region, and the gate electrode and the wiring film can be surely insulated.
Furthermore, since the gate electrode opening is formed after forming the wiring film and then the gate insulating film is formed, the semiconductor device having the above effect can be easily manufactured.

Further, according to the present invention, since the wiring film connected to the uppermost layer of the active region is formed in the concave portion provided in the interlayer insulating film, there is no step due to the wiring film on the surface of the interlayer insulating film, and when the gate electrode is formed. Patterning is facilitated and reliability is improved. Further, since such a wiring film is formed by forming a conductive film on the entire surface and then leaving the film only in the recesses to planarize the entire surface, a semiconductor device having the above effect can be easily manufactured. Furthermore, even if the selectivity of the selective epitaxial growth is broken during the formation of the active region and Si particles are formed on the interlayer insulating film, the Si particles can be removed during the planarization of the entire surface in the wiring film forming step. Therefore, the wiring film and the like can be prevented from being unnecessarily short-circuited by the Si particles on the interlayer insulating film, and the reliability is improved.

Further, according to the present invention, a conductive film to be a wiring film is formed in the concave portion of the interlayer insulating film and then made to recede by etching, and then an insulating film is formed on the entire surface thereof, and then only in the concave portion. The remaining surface is flattened. As a result, it is possible to easily manufacture a semiconductor device in which there is no step on the surface of the interlayer insulating film, the gate electrode can be easily formed, and the parasitic capacitance is reduced at the portion where the wiring film and the gate electrode intersect to increase the speed.

Further, according to the present invention, since the gate electrode opening is formed in the active region in the transistor opening in a self-aligned manner, a highly reliable semiconductor device having a stable shape and performance can be obtained. Further, the active region is formed lower than the surface of the interlayer insulating film, the side wall of the Si nitride film is formed thereon, and the side wall of the Si nitride film is used as a mask to form the gate electrode opening. ,
The gate electrode opening can be easily formed in a self-aligned manner, and a semiconductor device having the above effects can be easily manufactured. Furthermore, after forming such an opening for a gate electrode, a conductive film to be a wiring film is formed in the recess provided in the interlayer insulating film, and the conductive film is made to recede by etching, and the insulating film is formed thereon. To form. This makes it possible to easily manufacture a semiconductor device having the above-described effect and reducing the parasitic capacitance in the portion where the wiring film and the gate electrode intersect and increasing the speed.

Further, according to the present invention, the opening is formed in the opening for the transistor in a self-aligned manner, and then the buried layer of the Si oxide film buried in the opening is removed by using the resist mask, An opening for the gate electrode is formed. Since the pattern of this resist mask has a very large mask alignment margin at the time of its formation, the opening for the gate electrode has the same value as that formed in the opening for the transistor in a self-aligned manner. A highly reliable semiconductor device with stable performance can be obtained.

Further, according to the present invention, since the wiring film connected to the uppermost layer of the active region is provided with the insulating film which is sufficiently thicker than the gate insulating film in the upper layer, the wiring film and the gate electrode intersect each other. The parasitic capacitance can be reduced in the part
The speed of the device can be increased.

Further, according to the present invention, since the active region is composed of the diffusion layer composed of the substrate semiconductor layer, the active region having good crystallinity can be surely obtained, and the performance of the transistor is improved.

Further, according to the present invention, the gate electrode opening is formed in the semiconductor substrate, the Si nitride film burying layer is embedded therein, and the semiconductor is self-aligned around the Si nitride film burying layer. The substrate semiconductor layer is formed by performing etching twice on the substrate. After forming a diffusion layer to be one of the source / drain regions by ion implantation in the lower part of the substrate semiconductor layer and the surrounding semiconductor substrate, an interlayer insulating film is formed around the substrate semiconductor layer,
Diffusion layers that become the other of the channel region and the source / drain regions are formed by ion implantation. Therefore, the degree of integration is high, the subthreshold characteristic is improved,
Moreover, a high-performance semiconductor device having good crystallinity can be manufactured.

Further, according to the present invention, a gate electrode is formed between the first interlayer insulating film and the second interlayer insulating film formed thereon, and the second interlayer insulating film is formed in the gate electrode forming region. Since an opening for a transistor which penetrates the gate electrode and the first interlayer insulating film is provided and an active region is formed in a thin film in the vertical direction through the gate insulating film, both sides of the channel region are formed as gate electrodes. A sandwiched vertical thin film transistor can be obtained. Therefore, a semiconductor device with improved subthreshold characteristics, high performance, and high integration can be obtained.

Further, since the semiconductor substrate is provided with the diffusion layer and is connected to the lowermost layer of the active region, it is easy to take out the electrode of the lowermost layer of the active region which is one of the source / drain regions in the vertical thin film transistor as described above. Becomes Further, this diffusion layer can be used as it is as a wiring, and the semiconductor device can be easily manufactured.

Furthermore, since the transistor opening is formed with a fine width having an upper limit value of 0.2 μm, the active region has a width of 0.2 μm or less, the channel region can be sufficiently depleted, and the subthreshold characteristic is further improved. improves.

Further, according to the present invention, after the first interlayer insulating film, the gate electrode, and the second interlayer insulating film are sequentially formed, the transistor opening is linearly formed, and the gate insulating film is formed therein. To form an active region. Like this
Since the transistor opening is formed in a linear shape, it can be formed to have a fine width, and an active region is formed therein to obtain a vertical thin film transistor in which both sides of the channel region are sandwiched by gate electrodes. Therefore, the subthreshold characteristic is improved, and a high-performance and highly integrated semiconductor device can be easily manufactured.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 6 is a sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a cross-sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a sectional view showing a step of the method of manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 9 is a sectional view showing a structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a sectional view showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a sectional view showing a structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 13 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

14A and 14B are a sectional view and a plan view showing one step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

FIG. 15 is a sectional view showing a step of a method of manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 16 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the third embodiment of the present invention.

FIG. 17 is a sectional view showing a step of a method of manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 18 is a sectional view showing a step of a method of manufacturing a semiconductor device according to the third embodiment of the present invention.

FIG. 19 is a sectional view showing a structure of a semiconductor device according to a fourth embodiment of the present invention.

FIG. 20 is a sectional view showing the method for manufacturing the semiconductor device according to the fourth embodiment of the present invention.

FIG. 21 is a cross-sectional view showing a structure and a manufacturing method of a semiconductor device according to a fifth embodiment of the present invention.

FIG. 22 is a sectional view showing the method for manufacturing the semiconductor device according to the sixth embodiment of the present invention.

FIG. 23 is a sectional view showing a structure of a semiconductor device according to a seventh embodiment of the present invention.

FIG. 24 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the seventh embodiment of the present invention.

FIG. 25 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the seventh embodiment of the present invention.

FIG. 26 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the seventh embodiment of the present invention.

FIG. 27 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the seventh embodiment of the present invention.

FIG. 28 is a sectional view showing a step of a method of manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 29 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the seventh embodiment of the present invention.

FIG. 30 is a sectional view showing a step of a method of manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 31 is a sectional view showing a step of a method of manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 32 is a sectional view showing a step of a method of manufacturing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 33 is a cross-sectional view showing the structure of the semiconductor device and the manufacturing method according to Embodiment 8 of the present invention.

FIG. 34 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the ninth embodiment of the present invention.

FIG. 35 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the ninth embodiment of the present invention.

FIG. 36 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the ninth embodiment of the present invention.

FIG. 37 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the ninth embodiment of the present invention.

FIG. 38 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the ninth embodiment of the present invention.

FIG. 39 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the ninth embodiment of the present invention.

FIG. 40 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the ninth embodiment of the present invention.

FIG. 41 is a sectional view showing the structure of the semiconductor device according to Example 10 of the invention.

FIG. 42 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention.

FIG. 43 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention.

FIG. 44 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention.

FIG. 45 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the tenth embodiment of the invention.

FIG. 46 is a cross-sectional view showing a step in the method of manufacturing the semiconductor device according to the tenth embodiment of the present invention.

FIG. 47 is a sectional view showing a step of a method of manufacturing a semiconductor device according to the tenth embodiment of the present invention.

FIG. 48 is a sectional view showing a step of a method of manufacturing the semiconductor device according to the tenth embodiment of the present invention.

FIG. 49 is a sectional view showing a step of a method of manufacturing a semiconductor device according to the tenth embodiment of the present invention.

FIG. 50 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the tenth embodiment of the present invention.

FIG. 51 is a cross-sectional view showing a step in the semiconductor device manufacturing method according to the tenth embodiment of the present invention.

FIG. 52 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the tenth embodiment of the invention.

53A and 53B are a sectional view and a plan view showing the structure of a semiconductor device according to an eleventh embodiment of the present invention.

54A and 54B are a sectional view and a plan view showing one step of a method of manufacturing a semiconductor device according to an eleventh embodiment of the present invention.

FIG. 55 is a cross-sectional view showing a step in the semiconductor device manufacturing method according to the eleventh embodiment of the present invention.

FIG. 56 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the eleventh embodiment of the present invention.

FIG. 57 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the eleventh embodiment of the present invention.

FIG. 58 is a cross-sectional view showing a step in the semiconductor device manufacturing method of the eleventh embodiment of the present invention.

FIG. 59 is a cross sectional view showing a step of a method of manufacturing a semiconductor device according to another example of Example 11 of the present invention.

FIG. 60 is a sectional view and a plan view showing the structure of a semiconductor device according to another example of Example 11 of the present invention.

FIG. 61 is a cross-sectional view showing the structure of a conventional semiconductor device.

FIG. 62 is a cross-sectional view showing the structure of a conventional semiconductor device according to another example.

[Explanation of symbols]

1 semiconductor substrate, 14 n ⁺ type impurity diffusion layer as diffusion layer, 15 interlayer insulating film, 16 transistor opening, 17 active region, 18 p-type epi layer as semiconductor layer to become channel region, 19a, b source N ⁺ type epi layer as a semiconductor layer to be a drain region, 20 gate electrode opening, 21 wiring film, 21a conductive film, 22
Gate insulating film, 23 gate electrode, 24 insulating film, 2
5 recess, 26 metal silicide layer, 27, 31 Si
Nitride film sidewalls as nitride film sidewalls, 28,30 Si nitride film burying layers as nitride film burying layers, 32 Si oxide film burying layers as oxide film burying layers, 33 resist patterns, 34 active regions, 34a substrate semiconductor layer, 35, 37 source
N ⁺ type diffusion layer to be a drain region, 36 p type diffusion layer to be a channel region, 38 oxide film, 38a second oxide film sidewall, 39 nitride film burying layer as a burying layer of Si nitride film, 40 first Oxide side wall, 42 first interlayer insulating film, 43 gate electrode, 4
4 second interlayer insulating film, 45 transistor opening,
46 gate insulating film, 47 active region, 48 p-type epi layer serving as channel region, 49a, b n ⁺ -type epi layer serving as source / drain region.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication H01L 21/8242 29/43 H01L 29/62 G 29/78 301 X

Claims (22)

[Claims] 1. An interlayer insulating film and a transistor opening formed on a semiconductor substrate so as to penetrate through the interlayer insulating film to reach the underlying semiconductor substrate and have a side surface thereof surrounded by the interlayer insulating film. A semiconductor layer of a first conductivity type which becomes a channel region on the semiconductor substrate in the opening for a transistor and a semiconductor layer of a second conductivity type which becomes a source / drain region so as to sandwich the channel region from above and below. An active region formed by stacking layers, a gate electrode opening formed in the central portion of the transistor opening so as to penetrate two layers from at least the active region, and in the gate electrode opening. A semiconductor device having a gate electrode formed through a gate insulating film. 2. A semiconductor substrate is provided with a diffusion layer of the second conductivity type, an opening for a transistor is formed in the diffusion layer forming region so as to reach the diffusion layer, and the bottom layer of the active region is diffused. The semiconductor device according to claim 1, wherein the semiconductor device is connected to the layer. 3. A surface of a diffusion layer provided on a semiconductor substrate,
The semiconductor device according to claim 2, wherein a metal silicide layer is formed in a region other than a region in contact with the active region. 4. The semiconductor device according to claim 1, wherein the active region comprises an epitaxial layer. 5. The semiconductor device according to claim 4, wherein the semiconductor layer which becomes at least the channel region of the active region is an epitaxial layer made of a compound of Si and Ge. 6. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a transistor opening in the interlayer insulating film, and a step of forming an active region in the transistor opening by a selective epitaxial growth method. Forming a gate electrode opening so as to penetrate two layers from above the active region, and forming a gate insulating film on the inner wall of the gate electrode opening, and then embedding the gate electrode opening in the gate electrode opening. 6. The method for manufacturing a semiconductor device according to claim 4, further comprising the step of forming a gate electrode. 7. A wiring film connected to the uppermost layer of the active region is provided from above the active region to above the interlayer insulating film, and the wiring film and at least two layers above the active region are continuously penetrated. 6. The semiconductor device according to claim 4, wherein the gate electrode opening is formed in the same manner, and a gate insulating film is further formed on the inner wall of the gate electrode opening and the surface of the wiring film. 8. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a transistor opening in the interlayer insulating film, and a step of forming an active region in the transistor opening by a selective epitaxial growth method, A step of forming a wiring film over the active region and the interlayer insulating film; a step of forming a gate electrode opening so as to penetrate the wiring film and the two layers from above the active region; The method of manufacturing a semiconductor device according to claim 7, further comprising the step of forming a gate electrode after forming the gate insulating film. 9. An interlayer insulating film is provided with a recess having a predetermined depth,
An opening for a transistor that penetrates the interlayer insulating film is formed in a part of the recessed region, and a wiring film connected to the uppermost layer of the active region formed in the opening for the transistor is provided in the recessed portion. A gate electrode opening is formed so as to continuously penetrate the film and at least two layers from above the active region, and a gate insulating film is formed on the inner wall of the gate electrode opening and the wiring film surface. The semiconductor device according to claim 4, wherein the semiconductor device is a semiconductor device. 10. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a recess in the interlayer insulating film, and a step of forming a transistor opening penetrating the interlayer insulating film in a part of the recess area. And a step of forming an active region in the opening for the transistor by a selective epitaxial growth method, and then forming a conductive film to be a wiring film on the entire surface so as to fill the inside of the concave portion, and then, forming the conductive film only in the concave portion. A step of leaving it to flatten the entire surface, a step of forming a gate electrode opening so as to penetrate the wiring film made of the conductive film and two layers from above the active region, and then forming a gate insulating film 10. The method of manufacturing a semiconductor device according to claim 9, further comprising the step of: 11. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a concave portion in the interlayer insulating film, and a step of forming a transistor opening penetrating the interlayer insulating film in a part of the concave area. And a step of forming an active region in the opening for the transistor by a selective epitaxial growth method, and then forming a conductive film to be a wiring film on the entire surface so as to fill the inside of the concave portion, and then, forming the conductive film only in the concave portion. A step of leaving and flattening the entire surface, and a step of further receding the conductive film by etching, then forming an insulating film on the entire surface, and leaving the insulating film only in the recesses to flatten the entire surface. Then, a step of forming a gate electrode opening so as to penetrate the wiring film formed of the insulating film and the conductive film and the two layers from above the active region, and then forming the gate insulating film. 10. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of: 12. An active region is formed in the transistor opening so that its surface is lower than the surface of the interlayer insulating film by a predetermined amount, and the interlayer is formed so as to surround the periphery of the upper layer of the transistor opening. A recess is provided in the insulating film at a depth that does not reach the second layer from above the active region, and a wiring film is provided in the recess to connect to the side surface of the uppermost layer of the active region, and further in the opening for the transistor. 5. A gate electrode opening is formed in the active region in a self-aligning manner, and a gate insulating film is formed on the inner wall of the gate electrode opening, the surface of the active region and the surface of the wiring film. Or the semiconductor device according to 5. 13. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a transistor opening in the interlayer insulating film, and an active region in the transistor opening by a selective epitaxial growth method. A step of forming the silicon nitride film so that its height is lower than the surface of the interlayer insulating film by a predetermined amount, and a step of forming a sidewall of a Si nitride film on the exposed portion of the interlayer insulating film in the inner wall of the transistor opening; A step of etching the active region in a self-aligned manner using the sidewall of the nitride film and the interlayer insulating film as a mask to form a gate electrode opening;
A step of filling the gate electrode opening with a burying layer of a Si nitride film; a step of forming a concave portion in the interlayer insulating film using the sidewall and filling layer of the Si nitride film and a resist pattern as a mask; After forming a conductive film to be a wiring film on the entire surface so that
A step of flattening the entire surface by leaving the conductive film only in the recess, a step of removing the sidewalls and the buried layer of the Si nitride film, and a gate insulating film, and then a gate electrode. 13. The method for manufacturing a semiconductor device according to claim 12, further comprising: 14. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a transistor opening in the interlayer insulating film, and an active region in the transistor opening by a selective epitaxial growth method on the surface thereof. Forming a height lower than the surface of the interlayer insulating film by a predetermined amount, and then forming a sidewall of a Si nitride film on the exposed portion of the interlayer insulating film on the inner wall of the opening for transistor, A step of etching the active region in a self-aligning manner by using the sidewall of the Si nitride film and the interlayer insulating film as a mask to form a gate electrode opening, and filling the gate electrode opening with a Si nitride film. A step of burying with a layer, and using the sidewall of the Si nitride film and the burying layer and the resist pattern as a mask to form the interlayer insulating film. A step of forming a concave portion, a step of forming a conductive film to be a wiring film on the entire surface so as to fill the concave portion, flattening the entire surface by leaving the conductive film only in the concave portion, and then the conductive layer After further retreating the film by etching, an insulating film is formed on the entire surface, and the insulating film is left only in the concave portion to planarize the entire surface, and thereafter, the side wall of the Si nitride film and the buried layer are formed. 13. The method for manufacturing a semiconductor device according to claim 12, further comprising a step of removing the gate insulating film and a step of forming a gate electrode after forming a gate insulating film. 15. A step of forming an interlayer insulating film on a semiconductor substrate, a step of forming a concave portion in the interlayer insulating film, a step of filling the concave portion with an embedded layer of a Si nitride film, and a step of forming the concave region. A step of forming a transistor opening penetrating the buried layer of the Si nitride film and the interlayer insulating film, and forming a sidewall of the Si nitride film on the side wall in the transistor opening, and then forming the transistor After forming a Si oxide film on the entire surface so as to fill the opening for use, the entire surface is removed until the upper portion of the sidewall of the Si nitride film is removed and the width of the sidewall of the Si nitride film becomes constant. Flattening and forming a buried layer of the Si oxide film, then removing the buried layer and sidewalls of the Si nitride film, and then the recess A step of forming an active region around the buried layer of the Si oxide film by a selective epitaxial growth method in the opening for the transistor below, and then a conductive film to be a wiring film is formed on the entire surface so as to fill the recess. Then, a step of flattening the entire surface by leaving the conductive film only around the buried layer of the Si oxide film in the recess, and then removing the buried layer of the Si oxide film by using a resist mask, 10. The method for manufacturing a semiconductor device according to claim 9, further comprising: a step of forming an opening for use; and a step of forming a gate insulating film and then forming a gate electrode. 16. The wiring film connected to the uppermost layer of the active region is provided with an insulating film sufficiently thicker than the gate insulating film on the upper layer thereof. Semiconductor device. 17. The semiconductor device according to claim 1, wherein the active region is formed of a diffusion layer formed of a substrate semiconductor layer. 18. A step of forming an opening for a gate electrode in a semiconductor substrate, and a step of filling a buried layer of a Si nitride film in the opening for a gate electrode, and then etching the semiconductor substrate to fill the Si nitride film. A step of projecting an upper layer portion of the layer, and a step of forming a first Si oxide film sidewall on a side surface of the projecting portion of the buried layer of the Si nitride film,
A step of etching the semiconductor substrate using the first Si oxide film sidewall and the buried layer of the Si nitride film as a mask to form a substrate semiconductor layer so as to surround the periphery of the buried layer of the Si nitride film; A step of forming a second Si oxide film sidewall around the first Si oxide film sidewall and the substrate semiconductor layer thereunder, and the first and second Si oxide film sidewalls and the S
The semiconductor substrate is again etched by using the i-nitride film burying layer as a mask to form a substrate semiconductor layer including a lower layer portion around which the sidewall is not formed so as to surround the burying layer of the Si nitride film. And a step of forming an impurity diffusion layer as the lowermost layer of the active region in the lower layer portion of the substrate semiconductor layer and the surrounding semiconductor substrate by ion implantation, and then forming an interlayer insulating film on the entire surface. After that, a step of flattening the entire surface until the surface of the substrate semiconductor layer is exposed, and a step of forming impurity diffusion layers, which are two layers from above the active region, in the substrate semiconductor layer by an ion implantation method, and then, A recess is formed in the interlayer insulating film so as to surround the upper periphery of the substrate semiconductor layer,
A step of forming the active region to a depth that does not reach the second layer, a step of burying a wiring film in the recess, and a step of removing the burying layer of the Si nitride film to open the gate electrode opening. 18. The method of manufacturing a semiconductor device according to claim 17, further comprising the step of forming a gate electrode after forming the gate insulating film. 19. A first interlayer insulating film on a semiconductor substrate,
A gate electrode formed in a predetermined region on the first interlayer insulating film, a second interlayer insulating film formed on the first interlayer insulating film so as to cover the gate electrode, and the gate electrode forming region. And a linear transistor opening formed so as to penetrate the second interlayer insulating film, the gate electrode, and the first interlayer insulating film to reach the underlying semiconductor substrate, and the transistor. A gate insulating film formed on the inner wall of the opening for use, and a first conductivity type epitaxial layer to be a channel region on the semiconductor substrate in the opening for the transistor in which the gate insulating film is formed A semiconductor device comprising: an active region formed in a vertical thin film shape by stacking three layers of a second conductivity type epitaxial layer to be a source / drain region so as to be sandwiched therebetween. 20. A semiconductor substrate is provided with a diffusion layer of the second conductivity type, an opening for a transistor is formed in the diffusion layer forming region so as to reach the diffusion layer, and the lowermost layer of the active region is the diffusion layer. 20. The semiconductor device according to claim 19, which is connected. 21. The upper limit of the opening for a transistor is set to 0.
21. The semiconductor device according to claim 19, wherein the semiconductor device is formed with a fine width of 2 μm. 22. A step of forming a first interlayer insulating film on a semiconductor substrate, and after forming a gate electrode on the first interlayer insulating film, covering the gate electrode and forming a second interlayer insulating film over the entire surface. A step of forming a film, and a step of forming a linear transistor opening in the gate electrode formation region so as to penetrate the second interlayer insulating film, the gate electrode and the first interlayer insulating film. Then, after forming the gate insulating film,
22. A method of manufacturing a semiconductor device according to claim 19, further comprising the step of forming an active region in the transistor opening.