JPH0851265A - Printed circuit board - Google Patents
Printed circuit boardInfo
- Publication number
- JPH0851265A JPH0851265A JP6184649A JP18464994A JPH0851265A JP H0851265 A JPH0851265 A JP H0851265A JP 6184649 A JP6184649 A JP 6184649A JP 18464994 A JP18464994 A JP 18464994A JP H0851265 A JPH0851265 A JP H0851265A
- Authority
- JP
- Japan
- Prior art keywords
- component
- preamplifier
- conductor pattern
- hole
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Structure Of Printed Boards (AREA)
Abstract
(57)【要約】
【目的】 テレビジョンカメラのプリアンプの入力回路
を撮像管ホルダ内に実装するために好適な手段を提供す
ることを目的とする。
【構成】 プリアンプの入力回路を構成するにあたり、
そのプリント回路基板上に部品の外被ケースの形状・寸
法に合わせた貫通穴を設け、上記貫通穴の周囲に上記部
品の端子を接着するための導体パターンを設け、上記部
品の外被ケースを上記貫通穴に挿入し、その端子を上記
導体パターンに接着する。さらに、上記基板上に設けら
れた第1の導体パターンに加え、上記基板の裏面に第2
の導体パターンを設け、上記第1の部品に加え、第2の
部品の外被ケースを上記基板の裏面より上記貫通穴に挿
入し、その端子を上記第2の導体パターンに接着する。
(57) [Abstract] [Purpose] It is an object to provide a suitable means for mounting an input circuit of a preamplifier of a television camera in an image pickup tube holder. [Configuration] In configuring the input circuit of the preamplifier,
A through hole is formed on the printed circuit board in accordance with the shape and dimensions of the case of the component, and a conductor pattern for bonding the terminals of the component is provided around the through hole, and the case of the component is covered. It is inserted into the through hole and the terminal is bonded to the conductor pattern. Further, in addition to the first conductor pattern provided on the substrate, a second conductor pattern is formed on the back surface of the substrate.
In addition to the first component, the casing of the second component is inserted into the through hole from the back surface of the substrate, and the terminal is bonded to the second conductor pattern.
Description
【0001】[0001]
【産業上の利用分野】本発明はテレビジョンカメラのプ
リアンプのプリント回路基板の構造に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a printed circuit board of a preamplifier of a television camera.
【0002】[0002]
【従来の技術】撮像管方式のテレビジョンカメラでは、
撮像管を光学的に精度良くカメラきょう体内に保持・固
定する機構として、図2に示すような撮像管ホルダが用
いられている。図3に撮像管ホルダの詳細な構造を示
す。図3に示すように、撮像管9のターゲットピン12
の近傍には、光導電ターゲット10で生じた信号をター
ゲットピン12を通して外部へ取り出すためのプリアン
プの入力回路13が実装される。キャップ15の内側に
あるこの部分は、撮像管9のフェースプレート11とプ
リズム16との距離が数mmと短く、また、撮像管ホルダ
8の径も図2に示すように3本の撮像管ホルダ相互の位
置関係から大きくとれない等の理由で、極めて狭くなっ
ている。あえて、この部分にプリアンプの入力回路を配
置する理由は以下による。2. Description of the Related Art In a television camera of an image pickup tube system,
An image pickup tube holder as shown in FIG. 2 is used as a mechanism for optically holding and fixing the image pickup tube in the camera housing. FIG. 3 shows a detailed structure of the image pickup tube holder. As shown in FIG. 3, the target pin 12 of the image pickup tube 9 is
An input circuit 13 of a preamplifier for taking out a signal generated in the photoconductive target 10 to the outside through the target pin 12 is mounted near the. In this portion inside the cap 15, the distance between the face plate 11 of the image pickup tube 9 and the prism 16 is as short as several mm, and the diameter of the image pickup tube holder 8 is three as shown in FIG. It is extremely narrow due to the fact that it cannot be set large due to the mutual positional relationship. The reason for arranging the input circuit of the preamplifier in this part is as follows.
【0003】すなわち、撮像管方式のテレビジョンカメ
ラの信号のS/Nは、撮像管の出力信号検出用のプリア
ンプのS/Nでほぼ決定付けられる。図4はそのプリア
ンプの概略を示したものである。図4に示すように、プ
リアンプ入力端子18には、FET1のゲート入力容量
Ca、撮像管9の光導電ターゲット10の出力容量C
s、さらに、入力端子18とターゲトピン12との間の
結線上に生じた浮遊容量C’とが存在する。ここでC=
Ca+Cs+C’とすると、このCとプリアンプのS/
Nとの間には概ね、 S/N ∝ I/C ……………………………………(1) の関係がある。したがって、カメラの信号のS/Nを向
上させるためには、上記式(1)のCの値を極力小さく
する必要がある。とりわけ、上記浮遊容量C’の低減は
重要である。浮遊容量C’を低減するには、図4におい
て、プリアンプ入力端子18とターゲットピン12との
間の結線を極力短くしなければならない。このため、テ
レビジョンカメラにおいては、図4に示したプリアンプ
17の入力回路13を、図3に示すようにターゲットピ
ン12との距離が最短になる位置に装着する必要があ
る。That is, the S / N of the signal of the image pickup tube type television camera is almost determined by the S / N of the preamplifier for detecting the output signal of the image pickup tube. FIG. 4 shows an outline of the preamplifier. As shown in FIG. 4, the preamplifier input terminal 18 has a gate input capacitance Ca of the FET 1 and an output capacitance C of the photoconductive target 10 of the image pickup tube 9.
s, and there is a stray capacitance C ′ generated on the connection between the input terminal 18 and the target pin 12. Where C =
If Ca + Cs + C ', this C and S / of the preamplifier
The relationship with N is generally S / N ∝ I / C …………………………………… (1). Therefore, in order to improve the S / N of the signal of the camera, it is necessary to make the value of C in the above formula (1) as small as possible. Above all, it is important to reduce the stray capacitance C ′. In order to reduce the stray capacitance C ′, the connection between the preamplifier input terminal 18 and the target pin 12 in FIG. 4 must be made as short as possible. Therefore, in the television camera, it is necessary to mount the input circuit 13 of the preamplifier 17 shown in FIG. 4 at a position where the distance from the target pin 12 is the shortest, as shown in FIG.
【0004】[0004]
【発明が解決しようとする課題】ところで、撮像管には
光導電ターゲットに数100Vの高電圧をかけて使用す
るものがあるが、その場合、プリアンプの入力回路とし
ては図4の13’で示すように、同図の入力回路13に
加え、バイアス抵抗Rbと結合用コンデンサCcが必要
となる。また、入力回路13’に示すように、FET1
を複数個(通常は2個程度)並列に接続してS/N等の
プリアンプの特性改善を図る場合もある。このように使
用する部品点数が増えるのにともない、プリアンプの入
力回路13を図3に示した撮像管ホルダ8の先端部の狭
いスペースに実装することが困難となってきた。本発明
は上記の問題を除去し、プリアンプの入力回路を撮像管
ホルダ内に実装するために好適な手段を提供することを
目的とする。By the way, there is an image pickup tube in which a photoconductive target is applied with a high voltage of several hundreds of volts. In that case, the input circuit of the preamplifier is shown by 13 'in FIG. As described above, the bias resistor Rb and the coupling capacitor Cc are required in addition to the input circuit 13 shown in FIG. In addition, as shown in the input circuit 13 ', FET1
In some cases, a plurality of (normally about two) are connected in parallel to improve the characteristics of the preamplifier such as S / N. As the number of parts used increases, it has become difficult to mount the input circuit 13 of the preamplifier in the narrow space at the tip of the image pickup tube holder 8 shown in FIG. It is an object of the present invention to eliminate the above problems and provide a suitable means for mounting the input circuit of the preamplifier in the image pickup tube holder.
【0005】[0005]
【課題を解決するための手段および作用】本発明は上記
目的を達成するために、プリアンプの入力回路を構成す
るプリント回路基板上に、FETの外被ケースの形状に
合わせた貫通穴を設け、上記FETの端子を接着するた
めの導体パターンを上記基板の表裏両面各々の上記貫通
穴の周囲に設けたことを特徴とし、第1のFETを上記
基板の表の面より上記貫通穴に挿入し、その端子を上記
基板の表の面に設けた第1の導体パターンに接着した上
で、第2のFETを同じく上記貫通穴に上記基板の裏面
より挿入し、その端子を上記基板の裏面に設けた第2の
導体パターンに接着するようにしたものである。これに
より、基板上にFET2個を1個分のスペースで搭載で
き、さらに、搭載したFETを含む全体の厚みを薄くで
き、よってプリアンプの入力回路の基板を小さくできる
ため、撮像管ホルダへの実装が容易になる。In order to achieve the above object, the present invention provides a through hole corresponding to the shape of the outer case of an FET on a printed circuit board which constitutes an input circuit of a preamplifier. A conductive pattern for bonding terminals of the FET is provided around the through holes on both front and back surfaces of the substrate, and the first FET is inserted into the through hole from the front surface of the substrate. , The terminal is bonded to the first conductor pattern provided on the front surface of the substrate, and then the second FET is also inserted into the through hole from the back surface of the substrate, and the terminal is mounted on the back surface of the substrate. It is adapted to be adhered to the provided second conductor pattern. As a result, two FETs can be mounted on the board in a space for one FET, and the total thickness including the mounted FETs can be reduced, so that the board of the input circuit of the preamplifier can be made small, and thus mounting on the pickup tube holder Will be easier.
【0006】[0006]
【実施例】以下、本発明について実施例を用いて説明す
る。図4に示したプリアンプ入力回路13’のようにF
ETを2個実装する場合、従来は基板上に横に並べて取
り付けていたために基板の面積が大きくなり、撮像管ホ
ルダ内に実装するのが困難であった。(図5にプリアン
プに用いられるFETの一例を示す。) そこで、本発明においては、図6に示すように、基板2
上にFETのモールド(端子を除く胴の部分)の形状に
合わせた取付穴4を設け、さらに、FETの端子接続用
の銅パターン3を基板2の表裏両面に設け、図1に示す
ように、FET1を基板2の表裏両面よりモールドを取
付穴4に埋め込むように実装し、ハンダ5により各端子
を銅パターン3に接続する。以上により、FET2個を
1個分の面積で実装できる。しかも、FET2個を上記
取付穴を用いずに単純に基板の表裏両面に1個ずつ実装
した場合と比較して部品の高さを含めた全体の厚みを薄
くすることができる。EXAMPLES The present invention will be described below with reference to examples. F as in the preamplifier input circuit 13 'shown in FIG.
In the case of mounting two ETs, conventionally, they were mounted side by side on the board, and thus the area of the board was large and it was difficult to mount them in the image pickup tube holder. (FIG. 5 shows an example of the FET used in the preamplifier.) Therefore, in the present invention, as shown in FIG.
A mounting hole 4 matching the shape of the FET mold (the portion of the body excluding the terminals) is provided on the top, and further copper patterns 3 for connecting the terminals of the FET are provided on both front and back surfaces of the substrate 2, as shown in FIG. The FET 1 is mounted on both sides of the substrate 2 such that the mold is embedded in the mounting hole 4, and each terminal is connected to the copper pattern 3 by the solder 5. As described above, two FETs can be mounted in an area for one FET. Moreover, the total thickness including the height of the parts can be reduced as compared with the case where two FETs are simply mounted one on each of the front and back surfaces of the substrate without using the mounting holes.
【0007】[0007]
【発明の効果】本発明によれば、撮像管方式のテレビジ
ョンカメラにおいて、プリアンプの入力回路基板を小型
にできるため、同基板を実装スペースの極めて限られた
撮像管ホルダ内に容易に実装できるようになる。これに
より、図4に示したプリアンプ入力回路13を撮像管9
のターゲットピン12に近接して配置できるために、入
力端子18とターゲットピン12との結線を短くでき、
この結線上に生じる浮遊容量C’を低減できる。また、
図1のようにFET2個を上下に重ねて実装することに
より、従来のように同一面上に並べて実装した場合に比
較して実装面積が1/2以下となり、部品実装にともな
う(部品と他導体間の)浮遊容量も低減できる。以上の
結果、前述の式(1)の関係からプリアンプのS/Nを
向上させることができ、テレビジョンカメラの基本性能
向上に大きく寄与できる。According to the present invention, in the image pickup tube type television camera, the input circuit board of the preamplifier can be downsized, so that the board can be easily mounted in the image pickup tube holder having a very limited mounting space. Like As a result, the preamplifier input circuit 13 shown in FIG.
Since it can be arranged close to the target pin 12 of, the connection between the input terminal 18 and the target pin 12 can be shortened,
The stray capacitance C ′ generated on this connection can be reduced. Also,
By mounting two FETs vertically on top of each other as shown in FIG. 1, the mounting area becomes 1/2 or less as compared with the case where the FETs are mounted side by side on the same surface as in the conventional case. Stray capacitance (between conductors) can also be reduced. As a result, the S / N ratio of the preamplifier can be improved from the relation of the above-mentioned formula (1), and it can greatly contribute to the improvement of the basic performance of the television camera.
【図1】本発明によるプリント回路基板の部品実装概念
図。FIG. 1 is a conceptual diagram of component mounting on a printed circuit board according to the present invention.
【図2】カメラきょう体内の撮像管ホルダの実装状態を
示す構造図。FIG. 2 is a structural diagram showing a mounting state of an image pickup tube holder in a camera housing.
【図3】撮像管ホルダの一例を示す構造図。FIG. 3 is a structural diagram showing an example of an image pickup tube holder.
【図4】プリアンプの概略を示す概念図。FIG. 4 is a conceptual diagram showing an outline of a preamplifier.
【図5】FETの形状を示す概略図。FIG. 5 is a schematic view showing the shape of an FET.
【図6】本発明によるプリント回路基板の一実施例を示
す概略図。FIG. 6 is a schematic view showing an embodiment of a printed circuit board according to the present invention.
1 FET 2 プリント回路基板 3 銅パターン 4 取付穴 5 ハンダ 6 カメラきょう体 8 撮像管ホルダ 9 撮像管 12 ターゲットピン 13、13’ プリアンプ入力回路 1 FET 2 Printed Circuit Board 3 Copper Pattern 4 Mounting Hole 5 Solder 6 Camera Body 8 Camera Tube Holder 9 Camera Tube 12 Target Pin 13, 13 'Preamplifier Input Circuit
Claims (2)
において、基板上に部品の外被ケースの形状・寸法に合
わせた貫通穴を設け、該貫通穴の周囲に上記部品の端子
を接着するための導体パターンを設け、上記部品の外被
ケースを上記貫通穴に挿入し、その端子を上記導体パタ
ーンに接着したことを特徴とするプリント回路基板。1. In a printed circuit board on which an electronic component is mounted, a through hole is provided on the substrate in accordance with the shape and size of a casing of the component, and the terminals of the component are bonded around the through hole. The printed circuit board is characterized in that the conductor pattern is provided, the case of the component is inserted into the through hole, and the terminal is adhered to the conductor pattern.
1の導体パターンに加え、上記基板の裏面に第2の導体
パターンを設け、上記第1の部品に加え、第2の部品の
外被ケースを上記基板の裏面より上記貫通穴に挿入し、
その端子を上記第2の導体パターンに接着したことを特
徴とする請求項1記載のプリント回路基板。2. In addition to the first conductor pattern provided on the printed circuit board, a second conductor pattern is provided on the back surface of the board, and in addition to the first component, a jacket of the second component is provided. Insert the case into the through hole from the back side of the board,
The printed circuit board according to claim 1, wherein the terminal is bonded to the second conductor pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6184649A JPH0851265A (en) | 1994-08-05 | 1994-08-05 | Printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6184649A JPH0851265A (en) | 1994-08-05 | 1994-08-05 | Printed circuit board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0851265A true JPH0851265A (en) | 1996-02-20 |
Family
ID=16156934
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6184649A Pending JPH0851265A (en) | 1994-08-05 | 1994-08-05 | Printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0851265A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19725424C2 (en) * | 1996-06-19 | 2001-11-15 | Lg Semicon Co Ltd | Printed circuit board with components mounted in the surface |
-
1994
- 1994-08-05 JP JP6184649A patent/JPH0851265A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE19725424C2 (en) * | 1996-06-19 | 2001-11-15 | Lg Semicon Co Ltd | Printed circuit board with components mounted in the surface |
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