JPH0851584A - LCD drive circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In a liquid crystal display device in which a counter electrode voltage is inverted and driven together with the polarity of a video signal, the quality of the liquid crystal can be maintained and a memory needs to be used even when an interlaced signal is displayed. And to provide a liquid crystal drive circuit that does not increase the circuit scale. [Structure] After inputting mutually inverted video signals to a first horizontal drive circuit 51 and a second horizontal drive circuit 52 and writing a signal for one scanning line to the first and second sample hold circuits, In the horizontal blanking period, first, a signal is transferred from one horizontal drive circuit 51 (or 52) to the liquid crystal element, and then the counter electrode voltage Vcom is inverted, and then the other horizontal drive circuit 52 (or 51) transfers it to the liquid crystal element. Transfer the signal. As a result, when pseudo interlaced display is performed by simultaneous writing of two lines, it is possible to perform display using polarity inversion for each horizontal pixel, and it is possible to maintain the image quality of the liquid crystal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal drive circuit for displaying an interlaced video signal in a pseudo interlaced display mode by simultaneously writing two lines.

[0002]

2. Description of the Related Art Liquid crystal display devices use various AC driving methods for the purpose of maintaining the quality of liquid crystals. In general,
In the liquid crystal display device, an AC drive that inverts the polarity of a video signal for each field is used.

FIG. 5 shows an example of a conventional liquid crystal drive circuit. The video signal supplied to the input terminal 1 is input to the non-inverting amplifier 2 and the inverting amplifier 3. The inverting amplifier 3 outputs a voltage whose polarity is opposite to that of the output of the non-inverting amplifier 2 with respect to the voltage Vcom of the counter electrode 8. The outputs of the non-inverting amplifier 2 and the inverting amplifier 3 are supplied to the respective input terminals a of the two switches 41 and 42 that constitute the switch 4 for switching the polarity. The switches 41 and 42 are switched in association with each other for each field, and the switch 41 inputs the signal from the non-inverting amplifier 2 to the input end a and the signal from the inverting amplifier 3 to the input end b to select the selected signal. To the first horizontal drive circuit 51, the switch 42 inputs the signal from the inverting amplifier 3 to the input end a and the signal from the non-inverting amplifier 2 to the input end b, and outputs the selected signal to the second Horizontal drive circuit 52
Supply to. If the switch 41 is the terminal a, the switch 42
Is also switched to the terminal a, and if the switch 41 is the terminal b, the switch 42 is also switched to the terminal b. Each switch 4
From the output terminals c of 1, 42, the video signals (Video) in which the polarities are inverted and the polarities are switched in each field.
Is output. Therefore, the signal supplied to the first horizontal drive circuit 51 and the signal supplied to the second horizontal drive circuit 52 are inverted, and the respective signals are inverted for each field.

The liquid crystal display device 5 selects a liquid crystal panel 56, first and second horizontal drive circuits 51 and 52 for driving a horizontal direction to write a video signal in the liquid crystal panel 56, and a vertical write line. It is composed of first and second vertical drive circuits 53 and 54. The first horizontal drive circuit 51 and the second horizontal drive circuit 52 alternately supply sampling video signals to a plurality of vertical lines of the liquid crystal panel 56, and the first vertical drive circuit 53 and the second vertical drive circuit 53. The vertical drive circuit 54 alternately supplies a scanning pulse to a plurality of horizontal lines alternately arranged in the vertical direction of the liquid crystal panel 56 to activate a horizontal line to be written (on state). In the liquid crystal panel 56, a constant voltage Vcom is supplied from the terminal 8 to the counter electrode of the liquid crystal.

The horizontal drive circuits 51, 52 and the vertical drive circuits 53, 54 have various timing signals (sampling clock CK1, horizontal synchronizing pulse CK2, sampling start signal STH, scanning start signal STV, Transfer signals OE1 and OE2) are supplied. The timing generating circuit 7 is supplied with horizontal and vertical synchronizing signals from the terminal 6. This sync signal is separated from the input video signal.

In the above structure, the liquid crystal panel 56 is
The operation is performed with respect to the absolute value of the difference between the counter electrode voltage Vcom and the driving voltage, and the outputs of the non-inverting amplifier 2 and the inverting amplifier 3 become the counter electrode voltage Vcom as shown in FIGS. 6 (a) and 6 (b). It has a symmetrical waveform. In FIG. 6, (a) is a positive video signal (Vi
deo), (b) are negative video signals (Video) input to the horizontal drive circuit 52, (c) is the type of input video signal period (video period and horizontal blanking period HBLK), (d)
Is a transfer signal OE1 of the horizontal drive circuits 51 and 52, (e) is a sampling start signal STH of the horizontal drive circuit 51, (f) is a sampling clock CK1 of the horizontal drive circuit 51, (g)
Is a sampling start signal STH of the horizontal drive circuit 52,
(h) is the sampling clock CK1 of the horizontal drive circuit 52
Is.

FIG. 7 shows a structural example of the liquid crystal display device 5. Here, the liquid crystal panel 56 has a case of horizontal 8 pixels and vertical 6 pixels, and the same portions as those in FIG. 5 are represented by the same numbers. Note that reference numerals 561 to 563 represent one liquid crystal pixel, 561 is a liquid crystal element, 562 is the capacitance of the liquid crystal layer,
63 is a thin film transistor (TFT). The first horizontal drive circuit 51 and the second horizontal drive circuit 52 are provided with vertical lines X1 and X2 for writing video signals as shown in FIG.
, X3, X4, X5, X6, X7, X8 are alternately driven (alternately driven for each pixel), the drive polarity of the first horizontal drive circuit 51 and the second When the drive polarity of the horizontal drive circuit 52 of
The polarity is inverted for each horizontal pixel and for each field, and display unevenness (flicker) caused by the inversion of the polarity becomes a fine vertical line, which is inconspicuous.

Here, the liquid crystal display device 5 will be described in detail. The horizontal drive circuit 51 includes a shift register 515 corresponding to the number of pixels to be driven in the horizontal direction, a sample hold circuit 516 that samples and holds an input video signal by this output, and a buffer driver 517 that can supply this video output to liquid crystal. It is composed by. The shift register 515 has a terminal 51 as shown in FIG.
The sampling start signal STH inputted from 2 is shifted, and the sampling clock CK1 inputted to the terminal 511 is inputted with a clock having a half frequency of the dot clock as shown in FIG. 6 (f). There is. Therefore, the output of the shift register 515 is the output of the horizontal drive circuit 51.
Shows the horizontal position of every two pixels to be displayed in the video signal currently input.

The sample and hold circuit 516 is constructed as shown in FIG. In FIG. 8, a sample hold circuit 516 includes a terminal 5161 to which a sampling timing signal from the shift register 515 is applied, a switch 5162 for sampling a video signal input from the terminal 513, and a hold for holding the sampling signal. It is composed of an element 5163. The video signal input from the terminal 513 is input to the terminal 5161 to the shift register 5
It is written in the hold element 5163 through the switch 5162 to which the signal from 15 is supplied. Since the output of the shift register 515 is input to the terminal 5161, signals for one scanning line are sequentially written in each hold element 5163.

Returning to FIG. 7, the sample hold circuit 51.
When a signal for one scanning line is input to 6, the buffer driver 51 is input during the horizontal blanking period as shown in FIG. 6 (d).
The transfer signal OE1 is input to the transfer signal input terminal 514 of No. 7 and the video signal is transferred from the buffer driver 517 to the liquid crystal panel 56. Although the first horizontal drive circuit 51 has been described above, the second horizontal drive circuit 52 also has a sampling start signal ST as shown in FIGS. 6 (g) and 6 (h).
H, the phase of the sampling clock CK1 is different from that of the first horizontal drive circuit 51 (see FIGS. 6 (e) and 6 (f)), and the operation is exactly the same as that of the first horizontal drive circuit 51.

The vertical drive circuits 53 and 54 are shift registers 534 and 5 corresponding to the number of pixels to be driven in the vertical direction.
44 and buffer driver circuits 535 and 545. The shift registers 534 and 544 are
Scan start signal STV input from terminals 542 and 532.
Are shifted, and the clock terminals 531 and 541 have
A clock CK2 having a frequency half that of the horizontal synchronizing signal is input. Therefore, the shift registers 534, 54
The output of 4 indicates the vertical position for every two lines of the video signal currently input, and the signals output from the horizontal drive circuits 51 and 52 are of the horizontal line selected by the vertical drive circuits 53 and 54. It is transferred to the liquid crystal element 561.

By the way, in the above configuration, when a non-interlaced signal is input to the input terminal 1, 1
In the vertical scanning period, writing is performed one horizontal line at a time over all the horizontal lines of the liquid crystal panel 56, and one of the first and second vertical drive circuits 53 and 54 is alternately driven. In the configuration example of FIG. 7, the first vertical drive circuit 53 on the left side is used for driving odd lines, and the second vertical drive circuit 54 on the right side is used for driving even lines. The drive control of the vertical drive circuit 53 or 54 is performed by the transfer signal OE2 supplied to the output control terminals 533 and 543 of the vertical drive circuits 53 and 54.

On the other hand, when an interlace signal is input to the input terminal 1, a control method called pseudo interlaced display by simultaneous writing of two lines is used. This is the first vertical drive circuit 53 and the second vertical drive circuit 5
4 is used simultaneously, and the same video data is simultaneously transferred from the buffer drivers 517 and 527 of the horizontal drive circuits 51 and 52 to two adjacent horizontal lines.
In this case, the clock C applied to the vertical drive circuits 53 and 54
K2 is a horizontal synchronizing signal. Since the simultaneous writing of two lines is performed for each vertical scanning, that is, for each field, the liquid crystal panel 56 is driven by a full line for each field. At this time, a pseudo interlaced display can be performed by rearranging a combination of two lines simultaneously written in the first field and the second field. For example, in the first field, the second N-1 line and the second N line (N is a positive integer) of the liquid crystal panel 56 are simultaneously written, and in the second field, the second N line and the second N + 1 line of the liquid crystal panel 56 are written. Write at the same time. As described above, in the pseudo interlaced display, two lines are simultaneously driven in full line, and simultaneously written lines are shifted by one line for each field, so that the resolution in the vertical direction can be improved.

By the way, when a polymer dispersion type liquid crystal is used for the liquid crystal panel, it is necessary to set a large driving voltage with respect to the counter electrode voltage. Therefore, in FIG.
As shown in (a) and (b), the drive reference voltage Vc of the positive polarity video signal
(P) is set low and the drive reference voltage Vc of the positive polarity video signal is set.
(P) and the drive reference voltage Vc (N) of the negative video signal are made different so that a large drive voltage can be obtained even with a low power supply voltage. By doing so, it is possible to obtain a drive voltage about twice as high as that of the case of FIGS. 6 (a) and 6 (b) with the same power supply voltage. However, the drive reference voltage is the counter electrode voltage Vco
Since the counter electrode is common to all liquid crystal pixels, it is not possible to write a positive video signal and a negative video signal to each liquid crystal element at the same time. Therefore, in the conventional method of fixing Vcom, the polarities of the video signals supplied to the first horizontal driving circuit 51 and the second horizontal driving circuit 52 are inverted for each field, and the polarities are changed for each pixel in the horizontal direction. It was not possible to reverse and write on the liquid crystal element.

Therefore, as shown in FIG. 10, a method of inverting the polarity of the video signal for each scanning line is used. Even if this method is used, when a non-interlaced signal is input, the drive polarities of all the pixels are inverted for each field and the drive polarities are inverted for each scanning line. Flicker) becomes a fine horizontal line, which makes it inconspicuous. However, the interlaced signal is input,
When a pseudo interlaced display is performed by simultaneous writing of two lines, the drive polarities of all pixels are inverted for each field, and the drive polarities are inverted for every two adjacent scanning lines, and the combination of the two scanning lines is for each field. Therefore, a pixel whose drive polarity is not inverted is formed every time the field changes. Therefore, when an interlaced signal is supplied as an input, it is necessary to use a memory for converting the interlaced signal into a non-interlaced signal and inputting it, which causes a problem that the circuit scale becomes large.

[0016]

As described above, in the conventional liquid crystal drive circuit, when the method of inverting the polarity of the video signal for each field and inverting the polarity of the video signal for each scanning line is used, When an interlaced signal is input and a pseudo interlaced display is performed by simultaneous writing of two lines, pixels in which the drive polarity is not inverted are formed in each field. Therefore, a memory is required for converting the interlaced signal into the non-interlaced signal, which causes a problem that the circuit scale becomes large.

Therefore, according to the present invention, in the liquid crystal display device in which the counter electrode voltage is inverted and driven together with the polarity of the video signal, even when the interlaced signal is displayed, the drive polarities of all pixels can be inverted for each field, and the liquid crystal It is an object of the present invention to provide a liquid crystal drive circuit that can maintain the quality of the liquid crystal display device, does not require the use of a memory, and does not increase the circuit scale.

[0018]

A liquid crystal drive circuit according to the present invention comprises a liquid crystal panel in which a plurality of liquid crystal elements are arranged in a matrix in horizontal and vertical directions, and an interlaced video signal is input and sampled. The first and second horizontal drive circuits are alternately supplied to the liquid crystal elements arranged in the horizontal direction of the liquid crystal panel, the polarities of the video signals input to the first horizontal drive circuit, and the second horizontal drive circuit. Means for inverting the polarity of the input video signal for each field; first and second vertical drive circuits for supplying scanning pulses to the liquid crystal elements alternately arranged in the vertical direction of the liquid crystal panel for scanning. A means for supplying a voltage to the counter electrode of the liquid crystal panel and the first and second vertical drive circuits are controlled to scan one line information over two lines in the first field,
In the second field, the combination of two lines to be displayed is rearranged for scanning, and two lines are simultaneously scanned to drive the liquid crystal panel in a pseudo-interlace mode and control the first and second horizontal drive circuits to perform a horizontal blanking period. After the video data is transferred from the first horizontal drive circuit to the liquid crystal element, the voltage level of the counter electrode is changed to transfer the video data from the second horizontal drive circuit to the liquid crystal element. And a timing control means.

[0019]

With the above-described structure, even in the liquid crystal display device in which the counter electrode voltage Vcom is inverted together with the video signal polarity and AC drive is performed, when performing pseudo interlaced display by simultaneous writing of two lines, every pixel in the horizontal direction. Since the polarity can be inverted, the drive polarity of all pixels can be inverted for each field, and the quality of the liquid crystal can be maintained. When displaying the interlaced signal, the circuit scale is not increased without using the memory.

[0020]

EXAMPLES Examples will be described with reference to the drawings. FIG. 1 is a block diagram showing a liquid crystal drive circuit according to an embodiment of the present invention.

In FIG. 1, the same parts as those in FIG. The video signal supplied to the input terminal 1 is input to the non-inverting amplifier 2 and the inverting amplifier 3. The respective outputs of the non-inverting amplifier 2 and the inverting amplifier 3 are supplied to two input terminals a of a switch 4 for switching the polarity of each field. The switch 4 includes a switch 41 for inputting a signal from the non-inverting amplifier 2 to an input end a and a signal from the inverting amplifier 3 to an input end b, and a switch 41 for inputting a signal from the inverting amplifier 3 to an input end a. and a switch 42 for inputting a signal from the non-inverting amplifier 2 to b. Both switches 41, 42 are switched in association with each other in each field. If switch 41 is terminal a, switch 42 is also connected to terminal a, and if switch 41 is terminal b, switch 4
2 is also connected to terminal b. From the output terminals c of the switches 41 and 42, video signals (Video) whose polarities are mutually inverted and whose polarities are switched for each field are output.

The outputs of the switches 41 and 42 are supplied to the first and second horizontal drive circuits 51 and 52 in the liquid crystal display device 5. Therefore, the signal supplied to the first horizontal drive circuit 51 and the signal supplied to the second horizontal drive circuit 52 are such that the polarities thereof are inverted and the polarities of the signals are switched for each field.

The liquid crystal display device 5 selects a liquid crystal panel 56, first and second horizontal drive circuits 51 and 52 for driving a horizontal direction to write a video signal in the liquid crystal panel 56, and a vertical write line. It is composed of first and second vertical drive circuits 53 and 54. The first horizontal drive circuit 51 and the second horizontal drive circuit 52 are provided in the liquid crystal panel 5
The sampling video signals are alternately supplied to the six vertical lines, and the first vertical drive circuit 53 and the second vertical drive circuit 54 are alternately arranged in the vertical direction of the liquid crystal panel 56. The scanning pulse is alternately supplied to the horizontal line of (1) to activate the horizontal line to be written (ON state).

The counter electrode voltage Vcom is supplied to the counter electrode of the liquid crystal panel 56 from the timing generation circuit 7A.

In this embodiment, when the horizontal drive circuits 51 and 52 transfer the positive video signal to the liquid crystal panel 56,
The level of the counter electrode voltage Vcom supplied to the counter electrode of the liquid crystal panel 56 is changed when the horizontal drive circuits 51 and 52 transfer the negative video signal to the liquid crystal panel 56.
That is, the timing generation circuit 7A sets the low reference voltage level Vc (P) to the common electrode voltage Vcom when the positive video signal is transferred.
, And a high reference voltage level Vc (N) can be output as the counter electrode voltage Vcom when the negative video signal is transferred.

Horizontal and vertical synchronizing signals are supplied from the terminal 6 to the timing generating circuit 7A.
In addition to generating the counter electrode voltage Vcom at a timing based on the timing of the synchronizing signal, various timing signals (sampling clock CK1, horizontal synchronizing pulse CK2, sampling start signal STH, scanning start signal STV, transfer signal OE1, OE2) is generated. Terminal 6
The horizontal and vertical synchronizing signals supplied to are separated from the input video signal.

The horizontal drive circuits 51, 52 and the vertical drive circuits 53, 54 are supplied to the timing generator circuit 7A with various timing signals (sampling clocks CK1,
Horizontal sync pulse CK2, sampling start signal STH,
The scanning start signal STV and the transfer signals OE1 and OE2) are supplied. Horizontal and vertical synchronizing signals are supplied from the terminal 6 to the timing generating circuit 7A.

Next, the operation of FIG. 1 will be described with reference to FIGS. 2 and 3. It is assumed that an interlace signal is input to the video signal input terminal 1. First, a case where the switches 41 and 42 are switched to the terminal a side in the first field will be described with reference to FIG.

The input video signal is input to the non-inverting amplifier 2 and the inverting amplifier 3 and inverted by the switch 4 which switches for each field to the first horizontal drive circuit 51 and the second horizontal drive circuit 52. Signal is input.
The output of non-inverting amplifier 2 and the output of inverting amplifier 3 are shown in Fig. 2 (a).
, A signal as shown in FIG. In this embodiment, as shown in FIG. 2C, the level of the common electrode voltage Vcom for the positive video signal and the level of the common electrode voltage Vcom for the negative video signal are changed. The output of the non-inverting amplifier 2 and the output of the inverting amplifier 3 become signals as shown in FIGS. 2 (a) and 2 (b). 2 (c) (and FIGS. 2 (a), (b)) where Vc (P) is a positive video signal drive reference signal, and Vc (N)
Is a reference signal for driving the negative video signal. The timing generation circuit 7A supplies various timing signals to the liquid crystal display device 5 on the basis of the synchronization signal input from the terminal 6, and the sampling signal and the clock signal CK1 supplied to the first and second horizontal drive circuits 51 and 52. The start signal STH and the timing signals supplied to the first and second vertical drive circuits 53 and 54 are the same as those in the conventional example (the timing signals to the horizontal drive circuits 51 and 52 are shown in FIGS. 6D to 6H). Same as),
Pseudo interlaced display is performed by writing 2 lines simultaneously.

2C to 2F show timing signals supplied to the liquid crystal display device 5 in this embodiment. The structure of the liquid crystal display 5 is the same as that of FIG. Now the first
2A is input to the horizontal drive circuit 51 of FIG. 2A, and the second horizontal drive circuit 52 is input to the second horizontal drive circuit 52 of FIG.
A negative video signal as shown in is input. At this time, the positive video signal is written in the first sample hold circuit 516 and the negative video signal is written in the second sample hold circuit 526 of the liquid crystal display device 5 shown in FIG.

Since the liquid crystal element 561 is driven with the counter electrode voltage Vcom as a reference, when the positive electrode video signal is written in the liquid crystal element 561, the counter electrode voltage Vcom is set to the positive electrode signal drive reference voltage Vc (P) and the negative electrode video signal is set. Is written, the counter electrode voltage Vcom is set to the negative signal drive reference voltage Vc.
Must be set to (N). Writing the video signal to the liquid crystal element 561 is performed by the transfer signal O to the horizontal drive circuits 51 and 52.
This is when E1 is input. Therefore, the counter electrode voltage V
com may be the reference voltage corresponding to the polarity of the video signal only when the transfer signal OE1 is input. In addition, the liquid crystal element 56 from the first and second horizontal drive circuits 51 and 52.
The timing of transfer to 1 is not necessarily the same, and it is possible to transfer independently whenever signals for one scanning line are written in the sample hold circuits 516 and 526.

Therefore, first, the drive reference voltage Vcom corresponding to the polarity of the video signal written in the first sample hall degree circuit 516 is applied to the counter electrode, and then the first and second sample hold circuits 516. After all the signals for one scanning line are written in 526, the signals are transferred from the first sample hold circuit 516 to the liquid crystal element 561.
Further, the counter electrode voltage Vcom is changed to a voltage level corresponding to the polarity of the signal written in the second sample hold circuit 526, and the second sample hold circuit 526 is changed.
By transferring a signal to the liquid crystal element 561, the polarity can be inverted for each horizontal pixel.

First and second sample and hold circuits 51
A period in which the video signal for one scanning line is written in 6,526 is a horizontal blanking period indicated by HBLK in FIG. In this embodiment, since the video signal is transferred from the first sample and hold circuit 516 in which the positive video signal is first written, the counter electrode voltage V as shown in FIG.
com is set to the positive video signal drive reference voltage Vc (P) during the video period before entering the horizontal blanking period HBLK.
In the horizontal blanking period HBLK, as shown in FIG. 2E, the transfer signal OE1 is first input to the first horizontal drive circuit 51, and the video signal is transferred from the first sample hold circuit 516 to the liquid crystal element 561. Next, as shown in FIG. 2C, the counter electrode voltage Vcom is set to the negative video signal drive reference voltage Vc.
Set to (N). Further, as shown in FIG. 2F, the transfer signal OE1 is input to the second horizontal drive circuit 52, and the video signal is transferred from the second sample hold circuit 526 to the liquid crystal element 561. The counter electrode voltage Vcom is set to the positive video signal drive reference voltage Vc (P) again during the next video period as shown in FIG. 2 (c). By repeating the above operation,
It is possible to perform display using polarity inversion for each horizontal pixel.

Next, the case where the switches 41 and 42 are switched to the terminal b side in the second field will be described with reference to FIG.

The input video signal is input to the non-inverting amplifier 2 and the inverting amplifier 3 and the output of the non-inverting amplifier 2 and the output of the inverting amplifier 3 at this time are respectively changed by the switch 4 which switches for each field. The signals are as shown in a) and Fig. 3 (b).

FIGS. 3C to 3F show timing signals supplied to the liquid crystal display device 5 at this time. As shown in FIG. 3C, the counter electrode voltage Vcom is reversed as compared with the case of FIG. 2C as the polarities of the video signals are switched. First
3 (a) is input to the horizontal driving circuit 51 of FIG. 3 (b), and the second horizontal driving circuit 52 is input to the second horizontal driving circuit 52 of FIG. 3 (b).
Since the negative polarity video signal as shown in FIG. 7 is input, at this time, the negative polarity video signal is input to the first sample hold circuit 516 and the second sample hold circuit 526 of the liquid crystal display device 5 shown in FIG. The positive image signal is written.

In the second field just described, the video signal is first transferred to the liquid crystal element from the first sample hold circuit 516 in which the negative video signal is written.

As shown in FIG. 3 (c), the counter electrode voltage Vcom
Is set to the negative video signal drive reference voltage Vc (N) during the video period before entering the horizontal blanking period HBLK. In the horizontal blanking period HBLK, first, the transfer signal OE1 is input to the first horizontal drive circuit 51, and the negative video signal is transferred from the first sample hold circuit 516 to the liquid crystal element 561. Next, as shown in FIG. 3C, the counter electrode voltage Vcom is set to the positive video signal drive reference voltage Vc (P) during the horizontal blanking period. Then, the transfer signal OE1 is input to the second horizontal drive circuit 52, and the positive video signal is transferred from the second sample hold circuit 526 to the liquid crystal element 561. The counter electrode voltage Vcom is set to the negative video signal drive reference voltage Vc (N) again during the next video period as shown in FIG. 3 (c). By repeating the above operation, it is possible to perform display using polarity inversion for each horizontal pixel also in the second field.

In the operation examples of FIGS. 2 and 3, the counter electrode voltage Vcom is changed during the video period, and the transfer order of the horizontal drive circuits 51 and 52 for transferring during the horizontal blanking period HBLK is fixed. Horizontal drive circuit 5 for each scanning line
It is also possible to change the transfer order of 1, 52 so that the common electrode voltage Vcom does not change during the video period.

FIG. 4 shows another operation example of the circuit of FIG.
However, FIG. 4 is an operation explanatory diagram when the switch 4 is switched to the terminal a side. As shown in FIG. 4, as shown in FIG. 4 (a), the positive video signal input to the horizontal drive circuit 51 is used.
When a negative video signal is input to the horizontal drive circuit 52, the counter electrode voltage Vc during the video period as shown in FIG.
The counter electrode voltage Vcom is changed during the horizontal blanking period HBLK without changing om, as shown in FIGS. 4 (e) and 4 (f).
Transfer the positive and negative video signals as shown in
If the transfer order is changed for each scanning line, it is possible to perform display using polarity reversal for each horizontal pixel similarly to the operation of FIG.

As described above, the first horizontal drive circuit (driver on the upper side in the figure) 51 for driving the odd-numbered pixels of the liquid crystal panel 56 and the second horizontal drive circuit 51 for driving the even-numbered pixels.
The horizontal drive circuit (lower driver in the figure) 52 is supplied with video signals whose polarities are inverted to each other, and during the horizontal blanking period HBLK, first one of the horizontal drive circuits starts the liquid crystal panel 5.
The signal is transferred to 6 and the potential of the counter electrode is changed, and then the signal is transferred from the other horizontal drive circuit to the liquid crystal panel 56. As a result, even when the pseudo interlaced display is performed by writing two lines at the same time, the polarity is inverted for each horizontal pixel every time the field is changed, and therefore, there is a line in which the polarity is not inverted even if the field is changed as in the conventional case. The quality of the liquid crystal can be maintained without such a problem.

[0042]

EFFECTS OF THE INVENTION By using the liquid crystal driving circuit as described above, even if the driving method of changing the counter electrode voltage is used, the pseudo-interlaced display is performed by simultaneously writing two lines while inverting the driving polarity for each horizontal pixel. Therefore, it is possible to provide a low-cost liquid crystal drive circuit that can maintain the quality of the liquid crystal and does not need to use a memory and does not increase the circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing a liquid crystal drive circuit according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating the operation of the circuit of FIG.

FIG. 3 is a diagram for explaining the circuit operation of FIG.

FIG. 4 is a diagram showing another operation example in the circuit of FIG.

FIG. 5 is a block diagram showing a conventional liquid crystal drive circuit.

FIG. 6 is a diagram showing the operation of the circuit of FIG. 5;

7 is a diagram showing a configuration example of the liquid crystal display device in FIG.

FIG. 8 is a diagram showing a configuration example of a sample hold circuit in FIG.

FIG. 9 is a diagram showing voltage waveforms when the driving reference voltage of the positive polarity video signal and the driving reference voltage of the negative polarity video signal are different.

FIG. 10 is a diagram for explaining the operation of the liquid crystal drive circuit when displaying a non-interlaced signal.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Video signal input terminal 2 ... Non-inverting amplifier 3 ... Inversion amplifier 4 ... Polarity switching switch 5 ... Liquid crystal display device 6 ... Synchronous signal input terminal 7A ... Timing generation circuit (timing control means) 51 ... First horizontal drive circuit 52 ... 2nd horizontal drive circuit 53 ... 1st vertical drive circuit 54 ... 2nd vertical drive circuit 56 ... Liquid crystal panel 515, 525, 534, 544 ... Shift register 516, 526 ... Sample hold circuit 517, 527, 535 , 545 ... Buffer driver 561 ... Liquid crystal element

Claims (3)

[Claims] 1. A liquid crystal panel in which a plurality of liquid crystal elements are arranged in a matrix in the horizontal and vertical directions, and an interlaced video signal is input and sampled, and the liquid crystal elements are arranged in the horizontal direction of the liquid crystal panel. First and second horizontal drive circuits alternately supplied, and the polarity of the video signal input to the first horizontal drive circuit and the polarity of the video signal input to the second horizontal drive circuit are inverted for each field. And a liquid crystal element alternately arranged in the vertical direction of the liquid crystal panel,
First and second vertical drive circuits for supplying a scan pulse to perform scanning, a means for supplying a voltage to a counter electrode of the liquid crystal panel, a first and a second vertical drive circuits for controlling the first and second vertical drive circuits, In the field, 1 line information is scanned over 2 lines, and in the 2nd field, the combination of 2 lines to be displayed is rearranged for scanning, and 2 lines are simultaneously scanned, and the liquid crystal panel is pseudo-interlaced to drive the first and second lines. The horizontal drive circuit is controlled so that the video data is transferred from the first horizontal drive circuit to the liquid crystal element during the horizontal blanking period, and then the voltage level of the counter electrode is changed to the second horizontal drive circuit. A liquid crystal drive circuit, comprising: timing control means for controlling to transfer video data to the liquid crystal element. 2. The timing control means sets the voltage level of the voltage supply means to the first voltage level during the video period before the horizontal blanking period, and during the horizontal blanking period. In the first
After the video data is transferred from the horizontal drive circuit to the liquid crystal element, the voltage level of the counter electrode is set to the second voltage level, and the video data is transferred from the second horizontal drive circuit to the liquid crystal element. 2. The liquid crystal drive circuit according to claim 1, wherein the liquid crystal drive circuit is controlled so that the video data transfer order from the first and second horizontal drive circuits in the horizontal blanking period is constant regardless of the horizontal scanning period. 3. The timing control means sets the voltage level of the voltage supply means to a first voltage level during a first horizontal blanking period, and during a second horizontal blanking period. By setting the voltage level to the second voltage level, the video data is transferred to the liquid crystal element from the first or second horizontal drive circuit at the first voltage level during the horizontal blanking period, and then the counter electrode is set. Is set to a second voltage level, and the second or first voltage level is set to the second voltage level.
The horizontal drive circuit controls the video data to be transferred to the liquid crystal element, and the video data transfer order from the first and second horizontal drive circuits in the horizontal blanking period is 1
The liquid crystal drive circuit according to claim 1, wherein the liquid crystal drive circuit is changed every horizontal scanning period.