JPH0851585A - Image display device - Google Patents

Abstract

PURPOSE:To obtain a high luminance image by providing a video signal time axis expansion device and a horizontal synchronizing signal expansion device so as to attain emission of electron beam to a fluorescent body even for a vertical blanking period. CONSTITUTION:A horizontal synchronizing signal expansion circuit 210 provides an output of a horizontal synchronizing signal LH expanded with respect to a video signal subject to time base expansion. Furthermore, a video signal time base expansion circuit 240 reproduces the video signal for a vertical valid pattern period by applying time base expansion to the video signal for the entire vertical period including the vertical blanking period. All control signals corresponding to line cathode drive pulses K1, K2 K44 and vertical deflection signals DV, DV' or the like are expanded over the entire vertical period including the vertical blanking period. Thus, each picture element in a scanning line is displayed according to the video signal and the video signal for a valid pattern subject to time base expansion for all the vertical period including the vertical blanking period is displayed even during the vertical blanking period according to a timing signal of a corresponding expansion period, then the electron beam emission time is kept long in each picture element unit and the image with high luminance is obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device in video equipment.

[0002]

2. Description of the Related Art Heretofore, a cathode ray tube has been mainly used as a color television image display element. However, a cathode ray tube has a very long depth compared to a screen, and it is not possible to manufacture a thin television receiver. It was possible.
Therefore, EL display elements, plasma display elements, liquid crystal display elements, and the like have been developed as flat panel display elements, but they are all insufficient in terms of performance such as brightness, contrast, and color reproducibility. Therefore, for the purpose of displaying a high-quality image similar to that of a cathode ray tube on a flat device using an electron beam, the screen on the screen is divided into matrix-shaped sections without any gaps, and an electron beam is generated for each section. 2. Description of the Related Art There is an image display apparatus that deflects and scans a phosphor to emit light to form a color television image as a whole.

An example of the above-mentioned conventional image display device will be described below with reference to the drawings. FIG. 8 is an exploded perspective view of a display element of a conventional image display device.

In FIG. 8, 1 is a back electrode, 2 is a line cathode as an electron beam source, 3 is an extraction electrode, 4 is a signal electrode,
Reference numerals 5 and 6 are focusing electrodes, 7 is a horizontal deflection electrode, and 8 is a vertical deflection electrode.
It is housed in the flat glass plate 10 and the inside of the container is evacuated.

The four corners of the back electrode 1 are chamfered because the bases (not shown) of the supporting frame for the various electrodes and the line cathode 2 are placed.

The line cathodes 2 are stretched in the horizontal direction so as to generate an electron flow that is uniformly distributed in the horizontal direction, and a plurality of such line cathodes 2 are provided in the vertical direction at appropriate intervals. There is. These line cathodes 2 have a structure in which, for example, a surface of a tungsten wire is coated with an oxide cathode material.

The back electrode 1 is formed by coating a conductor on the back glass plate 10 and is provided in parallel with the line cathode 2. The extraction electrode 3 is opposed to the back electrode 1 through the line cathode 2, and the through-holes 1 are provided at appropriate intervals in the horizontal direction.
It consists of a conductive plate having one row on a horizontal line facing each line cathode. The through hole 11 is circular in the embodiment, but may be elliptical or rectangular, or may be slit-shaped.

The signal electrode 4 is composed of a row of vertically elongated conductive plates 12 arranged in a plurality at a position facing each of the through-holes 11 in the extraction electrode 3 with a predetermined interval,
Each conductive plate has a similar through hole 13 at a position facing the through hole 11 of the extraction electrode 3. Through hole 1
The shape of 3 may be an ellipse or a rectangle, or may be an elongated slit in the vertical direction.

The focusing electrode 5 is made of a conductive plate having through holes 14 at positions facing the through holes 13 of the signal electrode 4, respectively. The shape of the through hole 14 may be a circle, an ellipse, or a slit shape. The focusing electrode 6 has a slit hole 15 which is vertically connected at a position facing the through hole 14 of the focusing electrode 5. The shape of the slit hole 15 may be a round hole, an ellipse, or a rectangular shape.

The horizontal deflection electrode 8 is composed of conductive plates 16 and 17 which are connected to each other at two comb-shaped ends which are meshed with each other at an appropriate interval on the same plane.
The space 18 formed between 7 and 7 is opposed to the through slit hole 15 of the focusing electrode 6. As shown in FIG. 8, the vertical deflection electrode 8 has a structure in which conductive plates 19 and 20 connected at the ends thereof, that is, two comb-shaped conductive plates 19 and 20 are in the same plane and are meshed with each other at an appropriate interval. Consists of.

The screen 21 is formed by applying a phosphor 22 which emits light by irradiation of an electron beam to the inner surface of the glass container 9 and adding a metal back layer (not shown) on the phosphor 22.

Further, the extraction electrode 3, the signal electrode 4, and the
Focusing electrodes 5 and 6, horizontal deflection electrode 7, vertical deflection electrode 8
Are bonded together with an insulating adhesive (not shown here) to form an integral electrode block 24.

The operation of the image display device configured as described above will be briefly described. First, the wire cathode 2 is heated by passing a heater current in order to facilitate electron emission. Appropriate voltage is applied to the back electrode 1, the line cathode 2, and the extraction electrode 3 in a heated state to emit a sheet-shaped electron beam from the surface of the line cathode 2. The sheet-shaped electron beam is divided into a plurality of pieces by the through hole 11 of the extraction electrode 3 and becomes a large number of electron beam streams 23.

The passing amount of the electron beam stream 23 is individually adjusted by the signal electrode 4 in accordance with the image signal applied to the signal electrode 4. Next, the electron beam that has passed through the signal electrode 4 passes through the through holes 14, 1 of the focusing electrodes 5, 6.
After being focused and shaped by the electrostatic lens effect of No. 5, the horizontal deflection is performed horizontally and vertically by the potential difference given to the adjacent conductive plates 16 and 17 of the horizontal deflection electrode 7 and the adjacent conductive plates 19 and 20 of the vertical deflection electrode 8. Biased. Further, a high voltage (for example, 10 KV) is applied to the metal back layer of the screen 21, and the electron beam is accelerated to high energy and collides with the metal back, causing the phosphor to emit light.

Next, a main part of a drive circuit for displaying a television image on this display element will be described with reference to FIG. FIG. 9 is a block diagram of a main part of a drive circuit of a conventional image display device.

First, the electron beam stream 23 is directed to the screen 21.
A drive portion for irradiating the surface with the light to make the raster emit light will be described.

The power supply circuit 122 is a circuit for applying a predetermined voltage to each electrode of the display element.
A DC voltage is applied to each of the extraction electrode 3, the focusing electrode 5, and the screen 21.

A composite video signal of a television signal is applied to the input terminal 123, and a vertical sync signal V and a horizontal sync signal H are separated and extracted by a sync separation circuit 124. The vertical deflection circuit 140 includes the comb-shaped conductive plates 19 and 20 of the vertical deflection electrode 8.
The vertical deflection signals DV and DV 'are output to the. The horizontal deflection circuit 141 outputs horizontal deflection signals DH and DH ′ to the comb-shaped conductive plates 16 and 17 of the horizontal deflection electrode 7.

On the other hand, the line cathode control circuit 126 includes the line cathode 2
Drive pulses K1, K2, ... K44 are generated. Figure 10
FIG. 4 is an operation waveform diagram of a main part of the drive circuit when the number of line cathodes is 44, the number of horizontal deflection stages is 6, and the number of vertical deflection stages per each line cathode is 5.

As shown in FIG. 10, the DV and DV 'signals change stepwise in opposite directions for each horizontal synchronizing signal H,
The electron beam flow 23 is vertically deflected in five steps by the difference voltage. The staircase waveforms of DV and DV 'alternately rise and fall are shown by the comb-shaped conductive plates 19 and 20 of the vertical deflection electrode 8.
Is every 5 horizontal scanning periods, the top and bottom of the electron beam flow alternate with each other. Further, regarding the DH and DH 'signals, the electron beam is deflected in the horizontal direction in six steps by the difference voltage during one horizontal scanning line period.

Further, the line cathode control pulse is K1, shown in FIG.
As in K2, ..., K44, the potential is low only for 5 horizontal scanning periods (hereinafter, referred to as 5H period) within the entire vertical period for each line cathode line, and the electrons are emitted during this low potential period. During the other period, a high potential is applied so that the electron emission is not performed, and a current is applied to the wire cathode to heat it so that the electron emission may be facilitated during the low potential period. . In this way, during the effective vertical scanning period, electrons are emitted from the upper to lower line cathodes in order for every 5 horizontal scanning periods.

As a result of the above, the electron beam is emitted for 5H periods in sequence from the one above the 44 line cathodes, and each electron beam corresponds to one line from the top to the bottom in 44 sections in the vertical direction. The vertical deflection is sequentially performed, and raster lines are sequentially drawn on the screen 22 from the first line at the upper end to the 220 line at the lower end.

Further, in each raster, each electron beam divided into a plurality of pieces in the horizontal direction is deflected in six steps in the horizontal direction, and these six steps are divided into R and R for two pixels in each section on the screen 22. Corresponding to each of the G and B phosphors, they are sequentially irradiated.

Hereinafter, for convenience of explanation, this one pixel is referred to as R1,
G1, B1 and the other are R2, G2, B2. The electron beams for each horizontal section are R1, G1, B1, R
By modulating with the video signal of 2, G2, B2,
Color television images can be displayed.

Next, the electron beam modulation control portion will be described. First, the television signal input terminal 123
Is added to the color demodulation circuit 130, and R, G, B primary color signals (hereinafter referred to as RGB video signals) are output. The output RGB video signal is A / D
It is digitally converted by the converter 300. Further, the sync separation circuit 124 extracts the horizontal sync signal H and the vertical sync signal V from the television signal.

Next, the digitally converted RGB video signal is added to the sample hold circuit group 131. Each sample and hold circuit group 131 has R1, G1, and B, respectively.
It has six sample-hold circuits for 1, R2, G2 and B2. These sample and hold outputs are added to the holding memory set 132, respectively.

The reference clock oscillator 133 is composed of a PLL circuit or the like, and generates a reference clock SCK having a constant phase with respect to the horizontal synchronizing signal H. The reference clock SCK is applied to the timing pulse generating circuit 134, and here, various timing pulses are generated based on the horizontal synchronizing signal H and the vertical synchronizing signal V.

In the leading sample and hold circuit 131,
The sampling of the video signal is started based on the sampling start pulse t1 corresponding to the first pixel in the effective horizontal scanning line period. The sampling start pulse t1 is sequentially transmitted to the next sample and hold circuit by a shift register or the like, and sampling is performed respectively. As a result, the video signals of R1, G1, B1, R2, G2 and B2 for the two pixels in each section are individually held in each sample and hold circuit group 131.

The held video signal is transferred to the memory group 132 all at once by the transfer pulse t2 after the sample and hold for one line is completed. This retained R1,
The signals of G1, B1, R2, G2 and B2 are switch circuits 1
35 added. Each switch circuit 135 is controlled by a signal switching pulse t3 obtained by dividing each horizontal period from the timing pulse generating circuit 134 into six, and each video signal of R1, G1, B1, R2, G2, B2 from the memory set 132. Is time-divided for each 1/6 horizontal scanning line period and sequentially output to the pulse width modulation (PWM) circuit 137.

In the pulse width modulation (PWM) circuit 137,
A signal electrode control signal V pulse-width modulated according to the magnitude of each of the video signals R1, G1, B1, R2, G2, B2.
12 is output. Further, the signal electrode control signals are individually applied to the conductive plates 12 of the signal electrodes 4 of the display element. The horizontal deflection and the switching of the switch circuit 135 are completely synchronized with each other, and as a result, each pixel in the scanning line is luminescently displayed according to the video signal. In this example, this control is sequentially performed for the 5 × 44 220 lines from the upper line, and the television image is displayed.

[0031]

However, according to the above configuration, the line cathode control pulses K1 and K2 shown in FIG.
As shown in K44, the electron beam is not emitted from any of the line cathodes during the vertical blanking period. That is, the electron beam irradiation for image display is performed only in the vertical effective screen period. Since the brightness of the image is proportional to the irradiation time of the electron beam, the above method is disadvantageous in considering higher brightness of the image.

In view of the above problems, it is an object of the present invention to provide an image display device of high brightness by irradiating an electron beam for image display during the entire vertical period including the vertical blanking period. To do.

[0033]

In order to achieve the above object, the image display device of the present invention reproduces a video signal of a vertical effective screen period by time-axis expansion for all vertical periods including a vertical blanking period. A video signal time base expansion device and a horizontal synchronization signal expansion device for generating a horizontal synchronization signal having an expanded period corresponding to the expanded video signal are provided.

[0034]

The video signal of the effective screen which is time-axis expanded in the entire vertical period including the vertical blanking period is included in the vertical blanking period according to the horizontal synchronizing signal, the reference clock and the timing signal of the corresponding extended period. Will be displayed. As a result, the electron beam irradiation time for each pixel can be lengthened, and the brightness of the image can be increased.

[0035]

【Example】

(Embodiment 1) An image display device according to an embodiment of the present invention will be described below with reference to the drawings. Figure 1
FIG. 1 is a block diagram of a main part of an image display device in one embodiment of the present invention. In FIG. 1, the same parts as those of the conventional example are designated by the same reference numerals and the description thereof will be omitted.

In FIG. 1, reference numeral 233 is a reference clock oscillator, and here, a reference clock "RCK" corresponding to a time-axis expanded video signal and a reference clock "SCK" corresponding to an unexpanded video signal similar to the conventional example. Is oscillated and output.
Reference numeral 210 denotes a horizontal synchronizing signal expansion circuit, which outputs an expanded horizontal synchronizing signal "LH" corresponding to the time axis expanded video signal.

A video signal time axis expansion circuit 240 expands the video signal in the vertical effective screen period in the entire vertical period including the vertical blanking period and reproduces it.

The video signal time base expansion circuit according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 3 is a block diagram of a main part of the video signal time base expansion circuit according to the first embodiment of the present invention.

In FIG. 3, reference numeral 201 denotes a digital video signal input section to which digital RGB video signals are input. 20
Reference numerals 4a and 204b are memories, each of which has a storage capacity of a video signal corresponding to an effective screen. Numerals 203a and 203b are changeover switches for switching input / output video signals to / from the memories 204a and 204b, respectively. 205a and 205b are changeover switches, which change over signals of address lines to the memories 204a and 204b, respectively.

A read address counter 206 is reset by the vertical synchronizing signal V and outputs a read address of the memory. A write address counter 207 is reset by the vertical synchronizing signal V and outputs a write (write) address to the memory. Reference numeral 208 denotes a D-type flip-flop which is toggled by the vertical synchronizing signal V. A video signal output unit 202 outputs a video signal expanded in the time domain.

The operation of the video signal time base expansion circuit according to the first embodiment of the present invention configured as described above will be described below with reference to FIG. FIG. 4 is an operation waveform diagram of a main part of the video signal time base expansion circuit shown in FIG. Here, for the sake of simplicity, the number of video dots (sampling number) in the vertical effective screen period is 12, the number of dots (sampling number) in the vertical blanking period is 4, and the number of dots (sampling number) in all vertical periods is 16. The operation will be described.

The D-type flip-flop 208 outputs a toggle signal in which H / L is switched every time the vertical synchronizing signal V is input, as shown in the figure.

The write address counter 207 is reset by the vertical synchronizing signal V, counts at each rising edge of the clock pulse "SCK" synchronized with the dots of the input video signal, and outputs 1 to 16 as shown in FIG. To do.

The read address counter 206 is reset by the vertical synchronizing signal V, and performs a counting operation at each rising edge of the clock pulse "RCK" synchronized with the dots of the output video signal, that is, the video signal expanded in the time axis as shown in FIG. Then, 1 to 12 are counted and output.

The respective terminals of the memories 204a and 204b are alternately switched between the read state and the write state for each vertical synchronizing signal V by the output of the D-type flip-flop 208, and when one is in the read state, one is in the write state. Controlled to be.

Taking the memory 204a as an example, when the R / W input terminal of the memory 204a is in the read state, the address input to the memory 204a becomes the read address counter 206, and the data line is controlled by the output terminal 202. It

As a result, as shown in FIG. 4, the video signal data from d1 'to d12' in the vertical effective screen period written in the previous video field is read from the memory 204a. This read timing is as shown in FIG.
The expansion is performed in the entire vertical period in synchronization with the rising of "K".

On the other hand, the memory 204b is in the write state at this time, and the writing operation of the video signal in the effective screen period is performed at the rising timing of "SCK".

In this way, by using the memory having a capacity corresponding to two vertical effective screens, writing / reading is alternately performed for each vertical synchronizing signal "V", and the read cycle is extended with respect to the write cycle. Axial extension is realized.

The operation of the image display device of the present invention will be further described below with reference to FIG. In FIG. 1, reference numeral 134 denotes a timing pulse generation circuit similar to that of the conventional example, but since "RCK" and "LH" corresponding to the expanded video signal are used as the reference pulse here, the timing pulse output is All correspond to the video signal expanded in the time axis.

Further, since the horizontal deflection circuit 141, the vertical deflection circuit 140, and the line cathode drive circuit 126 use "LH" corresponding to the expanded video signal as the horizontal synchronizing signal,
Various control circuits such as deflection signals also correspond to the time-axis expanded video signal.

As a result of the above, the expanded video signal is input to the circuit in the subsequent stage in the same manner as in the conventional example, and the operation is performed in the latter stage in correspondence with all the video signals expanded in the time axis.

The operation will be described below with reference to FIG. FIG. 2 shows an operation waveform diagram of a main part of the image display device in the first embodiment of the present invention shown in FIG.
Here, the same operation as that of the conventional example is omitted, and only the operation unit different from that of the conventional example will be described.

Line cathode drive pulses "K1", "K2" ...
All the control signals corresponding to "K44", "DV", "DV '", etc. were operating within the vertical effective screen period in the conventional example, but here, as shown in FIG. It operates by being stretched over the entire vertical period including it.

For example, the electron emission operation of the line cathode drive pulse "K44" is performed during the vertical blanking period here in contrast to the last 5 horizontal synchronizing periods of the vertical effective screen in the conventional example.

As described above, according to the present embodiment, all the control operations are performed in perfect synchronization with the video signal expanded in all vertical periods including the vertical retrace period, so that scanning is performed as in the conventional example. Each pixel in the line is luminescently displayed according to the video signal. Further, here, the video signal of the effective screen which is time-axis expanded in the entire vertical period including the vertical blanking period is displayed during the vertical blanking period in accordance with the timing signal of the corresponding extended period. Since the electron beam irradiation time for each pixel can be extended, the brightness of the image can be increased.

(Second Embodiment) A second embodiment of the present invention will be described below with reference to the drawings. FIG. 5 is a block diagram of a second embodiment of the video signal time base expansion circuit of FIG.

The difference from the video signal time base expansion circuit of the first embodiment is that the expansion operation, which requires two field memories, is performed by one field memory here.

In FIG. 5, reference numeral 201 denotes a digital video signal input section to which digital RGB video signals are input. 20
Reference numerals 3 and 205 denote change-over switches for switching the input / output video signal to / from the memory 204 and the address. A memory 204 stores a video signal.

A read address counter 206 is reset by the vertical synchronizing signal "V" and outputs a read (read) address of the memory. A write address counter 207 is reset by the vertical synchronizing signal "V" and outputs a write (write) address to the memory.

A timing generator 213 generates various timing signals from the vertical synchronizing signal V and "SCK". 212 is a D-type flip-flop. 210 is a shift register, which sequentially outputs the input data from “Q1” to “Q3”.

Reference numeral 211 denotes a shift register having a load function, which sequentially outputs the data loaded from "D1" to "D3". A video signal output unit 202 outputs a video signal expanded in the time domain.

The operation of the video signal time base expansion circuit according to the second embodiment of the present invention configured as described above will be described below with reference to FIG. FIG. 6 shows an operation waveform diagram of a main part of the video signal time base expansion circuit in the second embodiment shown in FIG. Again, for simplicity, the number of video dots (sampling number) in the vertical effective screen period is 1
The operation will be described assuming that the number of samplings in the vertical blanking period is 4, and the number of samplings in the entire vertical period is 16.

The "WAC" output from the timing generation circuit 213
"K" is a burst clock only for the vertical effective screen period as shown in FIG. With this "WACK", the write address counter 207 counts 1 to 12 during the vertical valid screen period. Since "WACK" is connected to the read / write control terminal of the memory, the changeover switch 203, and the changeover switch 205, the memory 204 performs the write operation in the first half of one clock cycle and the read operation in the second half.
The changeover switch 203 and the changeover switch 205 in FIG. 5 show the write operation. In this way, the output of the write address counter is connected to the address line during the write, and the input video signal is connected to the data line, and during the read, respectively. It works in reverse.

The timing generator circuit 213 outputs "RAC
“K” is a non-continuous clock every 3 clocks as shown in FIG. 6, and the read address counter 206 counts 1 to 12 in the entire vertical period by this “RACK”.

The output of the D-type flip-flop 212 is "R
CK ”is delayed by one clock and output to the shift register 210. The shift register 210 reads (reads) data from the memory 204 at this clock timing and sequentially outputs the data to "Q1", "Q2", and "Q3". In the shift register 211 with the load function, every time the shift register 210 reads 3 dots, “L
The data "Q1", "Q2", and "Q3" of the shift register 210 are loaded at the "P" timing, and are sequentially output at the timing of the reference clock "RCK" corresponding to the time axis expanded video signal.

As a result, as shown in FIG. 6, the video signal data from "d1 '" to "d12'" in the vertical effective screen period written from the shift register with load function 211 is "RCK" as shown in FIG. Synchronized with the rising edge of, the data is expanded in all vertical periods and continuously output.

As described above, during the vertical effective period, the video signal 4
A video signal for 3 dots is sequentially read while writing dots for the memory, and only the reading is sequentially performed without writing to the memory during the vertical blanking period, so that the memory having the capacity for the vertical effective scanning line period is obtained. With one, it is possible to realize time-axis expansion of the video signal.

(Embodiment 3) A third embodiment of the present invention will be described below with reference to the drawings. FIG. 7 shows an operation waveform diagram of a main part of the video signal time base expansion circuit in the third embodiment of the present invention. Again, for simplicity, the number of video dots (sampling number) in the vertical effective screen period is 1
The operation will be described assuming that the number of samplings in the vertical blanking period is 4, and the number of samplings in the entire vertical period is 16.

The difference from the second embodiment is that the read address counter 206 and the write address counter 207 are the second one.
In this embodiment, the number is counted from 1 to 12, but in this example, the number is counted from 1 to 3 because it is ternary.

During the vertical effective period, the video signal for 3 dots is sequentially read out while writing 4 dots for the video signal to the memory. Therefore, the next video signal is stored in the read memory address for 3 dots. It becomes possible to write data.

As described above, when the total video signal sampling number in the vertical effective screen period is M, the read / write address control to the memory is performed by the counter of the decimal number less than the sampling number M in the vertical effective screen period. By using the memory so as to make one round, the time axis extension can be performed with a memory capacity corresponding to less than the total number M of video signal samplings in the vertical effective screen period.

The memory capacity required at this time can be set to a minimum for the video signal data read in the vertical blanking period.

As described above, the first embodiment, the second embodiment, the third embodiment
The operation explanation of the video signal time base expansion circuit example
For the sake of simplicity, the operation has been described assuming that the number of video dots (sampling number) in the vertical effective screen period is 12, the number of samplings in the vertical blanking period is 4, and the number of samplings in all vertical periods is 16. If the ratio of the effective screen period and the vertical blanking period is about 8: 2, the vertical effective period is about 1
3.3 ms, the vertical blanking period is about 3.4 ms.

On the other hand, for example, assuming that the sampling frequency of the RGB video signal is 9 MHz and the quantization is performed at 8 bits, when considering the memory capacity, the total data amount of the RGB video signal in the effective screen period of one field. Is about 3M
It can also be a bit.

Therefore, the memory capacity required to expand the time axis in the first embodiment by about 6 Mbit is about 3 Mbit in the second embodiment and 10% of the minimum memory capacity in the third embodiment. This can be realized with a memory capacity of about 300 kbit.

[0077]

As described above, according to the present invention, the video signal in the vertical effective screen period is time-expanded in all the vertical scanning periods including the vertical blanking period, so that all the vertical blanking periods are included. In the vertical period, it is possible to irradiate an electron beam for image display, and it is possible to provide an image display device of high brightness at low cost.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an image display device according to an embodiment of the present invention.

FIG. 2 is an operation waveform diagram of a main part of the image display device according to the first embodiment of the present invention.

FIG. 3 is a block diagram of a main part of a video signal time base expansion circuit according to the first embodiment of the present invention.

FIG. 4 is an operation waveform diagram of a main part of the video signal time base expansion circuit according to the first embodiment of the present invention.

FIG. 5 is a block diagram of a main part of a video signal time base expansion circuit according to a second embodiment of the present invention.

FIG. 6 is an operation waveform diagram of a main part of a video signal time base expansion circuit according to a second embodiment of the present invention.

FIG. 7 is an operation waveform diagram of a main part of a video signal time base expansion circuit according to a third embodiment of the present invention.

FIG. 8 is an exploded perspective view of a main part of a display element of a conventional image display device.

FIG. 9 is a block diagram of a main part of a drive circuit of a conventional image display device.

FIG. 10 is an operation waveform diagram of a main part of a drive circuit of a conventional image display device.

[Explanation of symbols]

 122 power supply circuit 123 input terminal 124 sync separation circuit 126 line cathode control circuit 130 color demodulation circuit 131 sample hold circuit 132 memory 134 timing pulse generation circuit 135 switch circuit 137 pulse width modulation (PWM) circuit 140 vertical deflection circuit 141 horizontal deflection circuit 210 Horizontal sync expansion circuit 233 Reference clock oscillator 240 Video signal time axis expansion device 300 A / D converter 201 Digital video signal input unit 202 Video signal output unit 203, 203a, 203b Changeover switch 204, 204a, 204b Memory 205, 205a, 205b Changeover switch 206 Read address counter 207 Write address counter 208 D type flip-flop 210 Shift register 211 Shift register with load function 212 D type Flip-flop 213 timing generator circuit

Claims (3)

[Claims] 1. A front glass container internally coated with a phosphor and a rear glass plate that closes a rear opening of the front glass container are arranged opposite to each other, and a conductor is coated on an inner surface of the rear glass plate. By configuring a back electrode, in the space portion sandwiched between the front glass container and the back glass plate, the back electrode, a plurality of line cathodes, an extraction electrode composed of a single or a plurality of conductive plates, The control circuit includes an electrode block in which signal electrodes, a single or a plurality of focusing electrodes, horizontal deflection electrodes and vertical deflection electrodes are superposed in front and back, and a control circuit for driving each of the above electrodes by a television signal. Has a video signal time axis decompressor and a horizontal sync signal decompressor for time-decompressing and reproducing the video signal in the vertical effective screen period in all vertical periods including the vertical blanking period. Line period An image display device characterized in that it is also performed. 2. A video signal time axis expansion device, wherein, when the total number of video signal samplings in the vertical effective screen period is M, in the vertical effective screen period, during the writing period of the video signal for n samples to the memory, The video signal for (n-α) samples is read from the memory, and the video signal for (n-α) samples read and temporarily held is n /
(N-α) times of continuous reading, and during the vertical blanking period, writing to the memory is not performed, and the unread α × n / M sample video signals in the memory are The image display device according to claim 1, wherein the time axis expansion is performed by reading out in the same manner as the vertical effective screen period, with a memory capacity corresponding to the number of all video signal samplings in the vertical effective screen period. 3. A video signal time base expansion device, when the total video signal sampling number in the vertical effective screen period is M, the read / write address control to the memory is a decimal number less than the sampling number M in the vertical effective screen period. 3. The time axis expansion is performed with the memory capacity less than the total number of video signal samplings in the vertical effective screen period by using the counter in the vertical synchronization cycle and using the memory while making a round in the memory. Image display device.