JPH085404A - Position detection device - Google Patents

Abstract

(57) [Summary] (Correction) [Purpose] The phase change amount θ is output by the A / B phase conversion circuit,
A plurality of reference clock frequency groups are automatically selected in accordance with the counting capability of a counter or the like connected to the output side of the A / B phase conversion circuit to avoid the trouble of setting the reference clock frequency and to reduce the number of pins. A position detection device suitable for a small number of ICs is obtained. A difference circuit 31 for taking a difference between a current phase change amount θ _n obtained from a position detection device and a previous phase change amount θ _n-1
The output data D ₇ to D ₀ of supplies to the A / B phase converter circuit 20 and a selector 33, a plurality of the reference clock frequency group f ₀ supplied to the selector 33, f _0/2, f _0/4 ‥‥
Any one of the reference clock frequencies of the data D _{7 to} D
₀ according to ₀ , supplies to the clock terminal CK of the A / B phase conversion circuit 20, and is connected to the output side of the A / B phase conversion circuit 20. Then, A-phase and B-phase signals whose phases are different by 90 degrees are obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a position detecting device which detects a position by a sampling method.

[0002]

2. Description of the Related Art Conventionally, various types of position detecting devices for detecting a tool moving position of a machine tool or the like have been proposed, for example, magnetic type, optical type, capacitance type and the like are known. There is. FIG. 5 shows the principle configuration of a phase modulation type magnetic scale device. In FIG. 5, reference numeral 1 is a magnetic scale, and a constant wavelength λ (for example, 20
A rectangular wave signal or a sine wave signal of 0 μm) is recorded, and is attached to, for example, a movable table on which a workpiece of a machine tool is clamped.

2 and 3 are attached to a fixed part of a machine tool so as to be in contact with the magnetic scale 1 on the moving table (n ± 1).
/ 4) First and second magnetic flux response type magnetic heads (hereinafter referred to as magnetic heads) arranged at intervals of λ (n is an integer).

These magnetic heads 2 and 3 are saturable cores 2.
It is composed of exciting coils 2B and 3B wound around A and 3A and output coils 2C and 3C.

[0005] m times 5 is the angular frequency 2πf ₀ = _{ω 0} of the carrier signal: an oscillator for oscillating (m positive integer), the corners of omega _0/2 by downconverting unit 6 an output signal from the oscillator 5 The signal of the frequency is supplied to the exciting coil 2B of the first magnetic head 2 and is supplied to the exciting coil 3B of the second magnetic head 3 with a phase shift of π / 4 through the phase shifter 7.

From the output coils 2C and 3C of the first and second magnetic heads 2 and 3, the first and second magnetic heads 2 are connected.
A modulation signal of each excitation signal according to the relative change amount x of the magnetic scales 1 and 3 with respect to the magnetic scale 1 is obtained.

The modulation signals e ₁ = E ₁ obtained from the output coils 2C and 3C of the first and second magnetic heads 2 and 3, respectively.
sin 2πx / λ cos ω ₀ t and e ₂ = E ₁ co
s2πx / λ sin ω ₀ t (where E ₁ is a constant and λ is a wavelength) is added by the adder 8 to pass only the second harmonic (generally even harmonics) signal thereof. A phase change signal e = e ₁ having phase change data θ corresponding to the relative change amount x and having an angular frequency ω ₀ twice the angular frequency of the exciting current by being supplied to the filter (BPF) 9.
+ E ₂ = E ₁ sin (ω ₀ t + 2πx / λ) = E ₁ si
n (ω ₀ t + θ) is obtained.

The phase modulation signal e thus obtained is interpolated by the interpolation circuit 1
Supply 0. Since the relationship between the phase change data θ and the relative change amount x is θ = 2πx / λ, the carrier wave signal (sin ω) supplied through the oscillator 5 is inserted in the interpolation circuit 10.
₀ t) (see FIG. 6A), the phase modulation signal e = (si
n ω ₀ t ± θ) (see FIG. 6B) and the phase difference is, for example, 1
The value counted by the ₀ MHz time reference clock f ₀ (see FIG. 6C) is output to the output terminal T ₁ as the phase change amount θ and supplied to the counter, the control device, or the like. Here, as the phase variation θ is the sampling pulse SP carrier signal is output to the output terminal T _1, for example, as such a digital value of 0 to 199.

Further, a position detecting device as shown in FIG. 7 is also known. That is, the sine component (sin θ) and the cosine component (cos
θ) is taken out from the magnetic heads 2 and 3 of the magnetic scale 1, and the respective sin θ and cos θ components are converted into analog-digital converters (A / D) 18A and 18B of the detector 24.
To the frequency divider 21 via the input terminals T ₂ and T ₃ , and the clock CK from the oscillator 23 that oscillates the reference clock frequency f ₀ to the frequency divider 21 to form the sampling pulse SP, It is supplied to the converters 18A and 18B, a calculator 19 described later, a difference circuit 31, and an A / B phase conversion circuit (two-phase conversion circuit) 20.

The digitally converted sine and all-string data from the A / D converters 18A and 18B are sampled by the sampling pulse SP by calculating the value of the triangular function Arctan (sin θ / cos θ) = θ by the calculator 19. The phase change amount θ for each sampling is calculated. The data of the phase change amount θ for each sampling obtained by the computing unit 19 is supplied to the A / B phase conversion circuit 20 through the difference circuit 31 and is
Two-phase signals having different 90-degree phases of phase B and phase B are supplied to a device 22 such as a counter or an NC device via output terminals T ₄ and T ₅ . Here, the A / B phase conversion circuit 2
It is necessary to change the counting capability of the A / B phase conversion circuit 20, that is, the reference clock frequency supplied to the A / B phase conversion circuit 20, by the counting capability (frequency response) of the device 22 on the side receiving the output signal from 0. There is, supplies a clock CK from the oscillator 23 to the frequency divider _{25, f 0 / 2~f 0 /} n (n
Is a positive number), and these reference clock frequencies f _{0 to} f
Switches S ₁ , S ₂ , S ₃ for switching ₀ / n
The predetermined reference clock frequency is supplied to the A / B phase conversion circuit 20 via S _m .

[0011]

In the position detecting device shown in FIG. 7, the magnetic scale 1 and the magnetic heads 2 and 3 are mounted relative to the moving part of the machine tool or the like, and the position detecting conversion circuit is provided. The constituent detector 24 is arranged in the vicinity of the machine tool, but the device 22 is installed at a position apart from the machine tool.

Therefore, the device 22 connected to the side for receiving the A phase and B phase signals of the output data of the A / B phase conversion circuit 20.
Depending on the count capacity, it involves trouble of switching the switch S ₁ to S ₃ of the clock frequency switching of the detector 24 side, such as is further adapted to all devices connected to the output terminal T ₄ and T ₅ side In order to obtain the detector 24, naturally, it is better that the number of the switches S _{1 to} S ₃ is larger, so that the number is increased, the frequency divider 25 is also increased, and the number of pins at the time of IC formation is increased. There was a problem to do.

The present invention has been made in order to solve the above problems, and the purpose thereof is to eliminate the need to provide a plurality of switches for switching the reference clock frequency on the detector 24 side, and to output the output of the detector 24. The reference clock frequency is automatically switched according to the counting capacity of the electronic device such as the counter or the control device connected to the side, and the trouble of frequency setting can be eliminated and the number of pins when integrated into an IC is small. The detector 24, that is, the position detecting circuit is obtained.

[0014]

As shown in FIG. 1, the position detecting device of the present invention has a phase change within one wavelength obtained from the position detecting means which moves relative to the scale. In the position detecting device 30 configured to sample the data, detect the phase change amount θ for each sampling, and output a two-phase signal via the two-phase conversion means 20,
A difference means 31 for counting and outputting the difference between the current phase change amount θ _n and the previous phase change amount θ _n-1 for each sampling;
It comprises a two-phase conversion means 20 to which the output data of the difference means 31 is supplied and a clock frequency selection means 33 for automatically selecting the reference clock frequency of the two-phase conversion means 20.

[0015]

[Action] position detecting device of the present invention is to provide a phase variation theta for each sampling of the output signal from the scale of the detector head to the difference circuit 31, a phase change amount of the current phase variation theta _n and the previous theta _{n -1} Difference data θ _D = θ _n −θ _{n −1} Difference data θ _{D, that} is, the movement difference is output to obtain the movement difference of 1 count or more of the resolution within one sampling, and the response speed is artificially increased. I am letting you. This kind of count data is used for two-phase A
The output data of the difference circuit 31 is supplied to the selector 33 when the A / B phase signal is supplied to the / B phase conversion circuit 20 and the reference clock frequency f ₀ is supplied according to the output data.
Since ~ f ₀ / n is selected and the selected reference clock frequency is automatically supplied to the A / B phase conversion circuit 20, a switch becomes unnecessary when a detector circuit is formed.
It is possible to obtain a circuit having a small number of pins at the time of C conversion, and to obtain a position detection device that does not require a reference clock frequency setting switch.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the position detecting device of the present invention will be described in detail below with reference to FIGS. In the present example, the explanation will be given on the assumption that the phase change amount θ for each sampling is extracted from the magnetic heads 2 and 3 moving relatively to the scale 1 in the conventional configuration as described in FIGS. .

FIG. 1 is a system diagram showing the configuration of an embodiment of the position detecting apparatus of this example. For example, the arithmetic unit 19 shown in FIG.
The phase change amount θ for each sampling from is supplied to the difference circuit 31 as digital data. The sampling pulse SP is supplied to the sampling pulse input terminal T ₁₂ via the frequency divider 21 of FIG.
It is supplied to the / B-phase conversion circuit (two-phase conversion circuit) 20.

In the difference circuit 31, the sampling pulse SP
Captures the phase variation theta for each, holds the phase variation theta _n-1 taken for the current phase variation theta _n at the last sampling pulse SP, the current phase variation theta _n and the previous phase The difference data θ _D from the change amount θ _n-1 is obtained.
That is, θ _D = θ _n −θ _n−1 is output to the A / B phase conversion circuit 20 and the selector 33 as the difference, for example, 8-bit data D ₇ −D ₀ .

Further, since the magnetic heads 2 and 3 having a phase difference of 90 degrees, which are arranged to face the scale 1 as described with reference to FIGS. 5 and 7, are used, the polarity discriminating signal SPL indicating the moving direction of the scale 1 is used. It can be easily found in gate circuits. This polarity discrimination signal SPL is also supplied to the A / B phase conversion circuit 20.

In this example, the difference circuit 31 supplies the higher order 2-bit data D ₇ and D ₆ to the selector 33, but all the 8-bit data D _{7 to} D ₀ from the difference circuit 31.
May be supplied. The selector 33 has an input terminal T
₁₄ through T ₁₇ from the divider 25 (see FIG. 7) via the reference clock frequency f ₀ and the divided clock frequency f _0/2
.About.f ₀ / n is supplied, and one of these frequencies is automatically supplied to the A / B phase conversion circuit 20 as a clock signal CK according to the input data D ₇ and D ₆ .

As a result, the differential data for each sampling SP supplied to the A / B phase conversion circuit 20 is converted into A phase and B phase signals and two-phase signals having 90 ° different phases from the output terminals T ₄ and T _5. Is output and the position data is displayed on the device 22, for example.

1 of the A / B phase conversion circuit 20 described in FIG.
An example will be described with reference to FIG. In FIG. 2, the polarity determination signal SPL is supplied to the input terminal T ₁₈ and is supplied to one input terminal of the first exclusive OR gate circuit EXOR ₁ through the first inverter circuit INV ₁ and the second exclusive circuit. The polarity determination signal SPL supplied to the input terminal T ₁₈ is directly supplied to one input terminal of the OR gate circuit EXOR ₂ .

The other input terminals of the first and second exclusive OR gate circuits EXOR ₁ and EXOR ₂ are supplied with the A and B phase signals output to the output terminals T ₄ and T _{5 from} the third exclusive OR circuit. The output of the exclusive OR gate circuit EXOR ₃ is supplied to the first and second exclusive OR gate circuits EXOR 3.
The outputs of ₁ and EXOR ₂ are supplied to the first input terminals of the first and _second NAND gate circuits NAND ₁ and NAND ₂ , respectively.

Input terminal T₁₉Has a time reference clock CK
This clock frequency is f ₀, F₀/ 2, f₀
/ 4, f₀/ 8, etc. are selected and the second inverter
Road INV₂Via the down counter 34
And the first and second NANDs are supplied to the clock terminal CK.
Gate circuit NAND₁And NAND₂Second input terminal
To input terminal T₁₉The reference clocks CK supplied to
Supplied directly.

Further, the first and second NAND gate circuits N
The borrow output of the down counter 34 is supplied to the third input terminals of AND ₁ and NAND ₂ , respectively.

The input terminal T ₂₀ is supplied with, for example, 8-bit digital data D _{7 to} D ₀ obtained by digitizing the phase change amount θ for each sampling, and is supplied to the preset terminal of the down counter 34.

Further, the sampling pulse SP is supplied to the input terminal T ₂₁ and is supplied to the load terminal of the down counter 34, and the first and second NAND gate circuits NAND ₁ and NAN are supplied through the _third inverter circuit INV _3.
It is supplied to the fourth input terminal of D ₂ .

First and second NAND gate circuits NAND
The outputs of ₁ and NAND ₂ are supplied to the clock terminals of the first and second D-type flip-flop circuits FF ₁ and FF ₂ , respectively. First and second D-type flip-flop circuit F
Negative outputs Q of F ₁ and FF ₂ are returned to the data input terminal D, and two-phase A and B phase signals with 90 ° different phases are output from the respective positive outputs Q to output terminals T ₄ and T ₅ . It is made to do.

In the A / B phase conversion circuit 20 described above, the output of the down counter 34 is at a low level as shown in FIG. 3C from when the count of the down counter 34 becomes zero until the arrival of the next sampling pulse SP. Since the sampling pulse SP as shown in FIG. 3B is inputted to the load terminal of the down counter 34 at the input terminal T ₂₁ by presetting the down counter 34, the sampling pulse SP as shown in FIG. If the phase change amount θ is input and the value of the phase change amount θ is 8 in the decimal number “00001000”, the clock CK input to the input terminal T ₁₉ is reduced by 8 as shown in FIG. 3A. When counting, the down counter 34 becomes zero, so the output of the down counter 34 becomes low level as shown in FIG. 3C.

As a result, the A-phase and B-phase signals shown in FIGS. 3D and 3E are obtained at the output terminals T ₄ and T ₅ by the logic circuit shown in FIG. The A-phase and B-phase signals are supplied to the device 22.
By supplying to the device, it is possible to display the relative position between the scale and the detection head when the device 22 is a counter, and to control the relative position when the device 22 is an NC device.

Next, the selector shown in FIG. 1 will be described. This selector may be a multiplexer for selecting one system clock frequency from among a plurality of clock frequencies f _{0 to} f ₀ / n. For example, a multiplexer circuit such as type SN54ALS151, SN54ALS153 manufactured by Texas Instruments Incorporated is used. Is also good.

The SN54ALS 151 is an 8-channel multiplexer and has select input terminals A, B and C.
One of the input data supplied to the input terminals D1 to D7 is output to the non-inverting output terminal Y by one of the combinations of 3 bits. Therefore, by using an 8-channel multiplexer as the selector 33 in FIG. 1, the upper 3 bits of data D ₇ , D ₆ , D from the difference circuit 31 are applied to the select input terminals A, B, C.
By supplying ₅ , the clock terminal CK of the A / B conversion circuit 20 is selected by selecting one of the clock frequencies f _{0 to} f ₀ / n supplied to the input terminals T _{14 to} T _17.
Can be supplied to.

[0033] FIG. 4 is the reference clock frequency f ₀ and f _0/2
Of two types of input signals, i.e., the two-phase signals having different 90-degree phases output from the A / B-phase conversion circuit 20 when the one type is selected via the selector 33, that is, the A-phase signal and the B-phase signal. It is a wave form diagram which shows the phase relationship with the sampling pulse SP.

That is, FIG. 4A shows the input terminal T of the selector 33.
Reference clock frequency f ₀ supplied to _14, Figure 4B is also a reference clock frequency f _0/2 of the waveform supplied to the input terminal T ₁₅ of the selector 33, FIG. 4D is supplied to the select terminal A of the selector 33 In the case of the waveform of the data D ₇ of the most significant bit, select data of 1 and 0 is used in this case. Figure 4D is a reference clock frequency f ₀ or f _0/2 of the waveform supplied is selected by the selector 33 to the clock terminal CK of the A / B phase converter circuit 20.

According to the selector 33 as described above, when the selection data D ₇ is "1" as in the waveform on the left side of FIG. 4C, the reference clock frequency of the output terminal T _{14 is} as in the waveform on the left side of FIG. 4D. f ₀ is output, and when the select data D ₇ is “0” as in the waveform on the right side of FIG. 4C, the reference clock frequency f _0/2 of the output terminal T ₁₅ is output. An example of the phase relationship between the clock CK and the A-phase and B-phase signals and the sampling pulse SP is shown in FIGS. 4E to 4G. The number of A-phase and B-phase signals is determined by the output data of the difference circuit 31. That is, in this example, the position detecting device is configured to move by one count or more of the resolution within one sampling period T, and the response speed is increased.

Although the reference clock frequency group is selected by using only the higher order data such as the select data D ₇ and D ₆ in the above-mentioned embodiment, the select data D _{7 to} D ₀ from the difference circuit 31 is 8-bit. It is obvious that a larger number of reference clock frequency groups can be selected by constructing the operation logic. Further, in practice, the smaller the count number during sampling, the more the switching operation is required. Therefore, if the reference clock frequency f ₀ is divided by 1 / 2n, the count numbers 1, 2,
An extremely effective position detecting device can be obtained by switching every 4, 8 ... The reference clock frequency is, for example, 1 /
The frequency may be a divided frequency such as 2.5f ₀ .

In the present invention, the case where the magnetic scale is used has been described above, but any of the optical type, the capacitance type, the electromagnetic induction type and the like can be used.

[0038]

Since the position detecting device of the present invention is constructed and operated as described above, even if the reference clock frequency group is increased, the troublesome switching for frequency setting can be avoided and a plurality of switching devices can be used. Since the switch becomes unnecessary and the number of pins when the detector is integrated into an IC can be greatly reduced, a position detection device that is easily integrated into an IC can be obtained.

[Brief description of drawings]

FIG. 1 is a system diagram showing an embodiment of a position detecting device of the present invention.

FIG. 2 is an A / B phase conversion circuit diagram used in the position detection device of the present invention.

FIG. 3 is a waveform diagram for explaining an A / B conversion circuit.

FIG. 4 is a waveform diagram for explaining A- and B-phase signal counts.

FIG. 5 is a configuration diagram of a conventional position detection device.

FIG. 6 is a waveform diagram of FIG.

FIG. 7 is another configuration diagram of a conventional position detection device.

[Explanation of symbols]

 20 A / B phase conversion circuit (two-phase conversion circuit) 30 Position detection device 31 Difference circuit 33 Selector

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[Procedure amendment]

[Submission date] July 4, 1994

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction content]

In the above embodiment, the select data
D₇, D₆Reference clock frequency using only upper data such as
The wave group was selected, but the select data from the difference circuit 31
TA D₇~ D₀If you build an 8-bit operation logic as
It is obvious that many reference clock frequency groups can be selected
Is. Also, the number of counts during sampling is actually small.
Since the switching operation is required to the extent that there is not, the reference clock frequency
f₀Is divided by 1 / 2n, the number of counts 1, 2,
It is an extremely effective position detection if it is switched every 4, 8 ...
A delivery device is obtained. The reference clock frequency is, for example, 1 /
2.5f₀It is also possible to use a divided frequency as in. Also, above
PL instead of the multiplexer described above as a selector
An L (phase locked loop) circuit may be used, for example
For example, Type S manufactured by Applied Micro Circuits
Using a clock synthesizer circuit such as 4503
Is also good. The above S4503 is a video clock synthesizer.
It is an iser and connects with a predetermined clock oscillator.₀~
M_FourLower 5 bit data D from the difference circuit 31 to the terminal
₀~ D_Four(Appropriate bit data may be used if necessary)
Select the required clock frequency by supplying A / B
It can be supplied to the clock terminal CK of the phase conversion circuit 20.
In this case, a finer clock frequency can be selected.
Therefore, the output of the A / B phase conversion circuit 20 is closer to 90 °.
Two-phase signals with different phases can be obtained.

Claims (2)

[Claims] 1. The phase change data within one wavelength obtained from the position detecting means that moves relative to the scale is sampled to detect the phase change amount for each sampling,
In a position detecting device configured to output a two-phase signal via a two-phase conversion means, a difference means for counting and outputting the difference between the current phase change amount and the previous phase change amount for each sampling. And a clock frequency selecting means for automatically selecting the reference clock frequency of the two-phase converting means and the two-phase converting means to which the output data of the difference means is supplied. apparatus. 2. The position detecting device according to claim 1, wherein the output data from said difference means is supplied to said clock frequency selecting means to switch the clock frequency.