JPH0855844A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] To improve the poly-buffered LOCOS method and prevent the deterioration of the device performance and reliability. [Structure] A pad oxide film 2 is formed on a semiconductor substrate 1,
A semiconductor thin film layer 3 is formed thereon, and an oxidation resistant film pattern 5P is formed on the semiconductor thin film layer 3 so as to cover the upper part of the region 4 serving as an active region.
A field oxide film 6 formed by oxidizing a part of the semiconductor thin film layer 3 and the semiconductor substrate 1 is formed in a region not covered by the oxidation resistant film pattern 5P by thermal oxidation using the oxidation resistant film pattern 5P as a mask, The oxidation resistant film pattern 5P is removed to expose the semiconductor thin film layer 3 therebelow, a conductor layer 7 is formed on the semiconductor thin film layer 3 and the field oxide film 6, and the conductor layer 7 and the lower part thereof are formed. The semiconductor thin film layer 3 is patterned to form a gate electrode 8 in which the semiconductor thin film layer 3 and the conductor layer 7 are laminated on the pad oxide film 2 which serves as a gate oxide film and covers the region 4 which serves as the active region. There is a step to do.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device,
In particular, it relates to improvement of a polybuffered LOCOS method used when forming a field oxide film for element isolation by selective oxidation.

In recent years, with the development of the information processing society, further improvement in performance and reliability of computers and communication devices is required. On the other hand, semiconductor devices such as LSIs, which are mounted due to the large scale and multi-functionalization of these devices, have been extremely integrated and highly integrated, and in the semiconductor department, ensuring high performance and high reliability of the above semiconductor devices. Is an important issue.

In the above LSI and the like, in order to improve high density and high integration, it is necessary to reduce the element region area and the element isolation region width, and in order to achieve this, an element isolation insulating film is used. Polybuffered LOCO as a forming technology
A method by selective oxidation of S is provided. However, in the MOS type semiconductor device formed by using the conventional poly-buffered LOCOS, there is a problem that the performance and reliability of the element are deteriorated, and improvement is desired.

[0004]

2. Description of the Related Art In a high density and highly integrated LSI or the like, it is necessary to extremely reduce the area of the element region and the width of the element isolation region as described above, but it has been generally used. According to the selective oxidization means called LOCOS method, bird's beaks are extended and formed at the ends of the oxide film (field oxide film) for element isolation, which prevents the size of the element region and the reduction of the field oxide film width. The problem arises. This is the normal LOCOS method,
Since the pad oxide film for stress relaxation which is interposed between the semiconductor substrate and the oxidation resistant film formed as a mask for selective oxidation on the element formation region thereof has a large thickness, oxygen diffused there causes bird's beak This is because the growth is promoted. Therefore, it is necessary to reduce the film thickness of the pad oxide film in order to reduce the bird's beak and enable higher density and higher integration of the device.

However, when the thickness of the pad oxide film is reduced by the above method, the oxidation resistant film formed on the pad oxide film is patterned by dry etching means into a shape that selectively covers the element formation region. At this time, since a large etching selection ratio cannot be obtained between the oxidation resistant film and the pad oxide film, the pad oxide film around the oxidation resistant film pattern is also removed by etching and the semiconductor substrate surface is damaged. In addition, the stress relaxation effect also decreases as the pad oxide film thickness decreases, causing the problem that the element formation region is damaged by the stress exerted by the oxidation resistant film pattern. Deteriorates.

Then, a method of selective oxidation called polybuffered LOCOS is provided as a method for preventing the above damage. This method provides a polysilicon thin film between the pad oxide film and the oxidation resistant film, which serves as an etching stopper during patterning of the oxidation resistant film and contributes to alleviation of stress between the oxidation resistant film pattern and the semiconductor substrate. The interposition makes it possible to make the pad oxide film extremely thin, thereby achieving reduction of the bird's beak extending laterally along the pad oxide film under the oxidation resistant film pattern.

The conventional poly-buffered LOCOS
A MOS type semiconductor device in which a field oxide film for element isolation is formed by using the method has been manufactured by the method described below with reference to the process sectional view of FIG.

Referring to FIG. 6A, a silicon (Si) substrate 51 having a thickness of 30 is formed by thermal oxidation means.
A pad oxide film 52 having a thickness of about Å is formed, and then a poly-Si buffer layer 53 having a thickness of about 100 Å is formed by the CVD method.
A silicon nitride (Si ₃ N ₄ ) oxide resistant film with a thickness of about 1100Å is formed by the VD method, and then this Si ₃ N ₄ oxide resistant film is subjected to photolithography and dry etching means using, for example, (CF ₄ + CHF ₃ ) gas. By using this, patterning is performed so as to selectively cover the element forming region 54 which will be the active region. In the figure, 55 is Si
₃ N ₄ shows an oxidation resistant film pattern.

[0009] Incidentally, in the etching of the the Si ₃ N ₄ film is patterned, the Si ₃ N ₄ film bottom of the poly Si buffer layer 53 has a selectivity of sufficient etching, will not be etched away.

Referring to FIG. 6B, the Si ₃ N ₄ oxidation resistant film pattern 55 is used as a mask,
Thermal oxidation is performed in a wet oxygen atmosphere to form a field oxide film 56 for separating the elements on the surface of the Si substrate 51 excluding the element formation region 54 covered with the Si ₃ N ₄ oxidation resistant film pattern 55.

Next, referring to FIG. 6 (c), a Si ₃ N ₄ oxidation resistant film pattern is formed by boiled phosphate treatment.
55 removed, poly-Si buffer layer remaining underneath
The edges of 53 and the field oxide film 56 are exposed.

Referring to FIG. 6 (d), the poly-Si buffer layer 53 is removed by wet etching means using a hydrofluoric nitric acid-based solution, and then the pad oxide film 52 thereunder is removed by wet etching means using a hydrofluoric acid-based solution. Then, the surface of the Si substrate 51 in the element formation region 54 is exposed.

Next, as shown in FIG. 6 (d), a thickness is formed on the surface of the element forming region 54 by thermal oxidation means.
After forming a gate oxide film 57 of about 50 Å, then form a poly Si layer having a thickness of about 1500 Å by CVD means on this substrate, after introducing impurities into the poly Si layer to impart conductivity, The gate oxide film is formed on the element formation region 54 by patterning by dry etching using a gas such as chlorine.
It was a method of forming the poly-Si gate electrode 58 via 57.

[0014]

However, in the above-mentioned conventional method, in the step of removing the poly-Si buffer layer 53 and the pad oxide film 52 thereunder described in FIG. In order to cover the variation of the above, wet etching with the above-mentioned fluorinated nitric acid-based solution and hydrofluoric acid-based solution is performed under the condition that a predetermined over-etching is added, and therefore, as shown in FIG. Is also etched and its surface recedes to form a stepped portion 51S with the Si surface exposed at the peripheral portion of the element forming region 54. Then, a Si surface having a plane orientation other than the (100) plane of the upper surface is exposed in the step portion 51S, and the interface level in that portion increases.
Further, as described above, since the surface orientation of the Si surface exposed at the step portion 51S is different from that of the (100) surface, the oxidation rate in thermal oxidation becomes slower at the step surface, as shown in FIG. 6 (e). In addition, the film thickness of the gate oxide film 57 on the step portion 51S becomes extremely thin. 57S indicates a thinned gate oxide film.

Therefore, the conventional poly-buffered LO described above is used.
In a MOS LSI formed using the COS method,
The increase in the interface state of the stepped portion 51S at the periphery of the element forming region 54 and the decrease 57S in the thickness of the gate oxide film 57 cause a problem that the performance and reliability of the element are deteriorated.

Accordingly, the present invention provides an improved polybuffered LOC which does not degrade device performance and reliability.
The purpose is to provide an OS method.

[0017]

Means for Solving the Problems To solve the above problems, a step of forming a pad oxide film on a semiconductor substrate, a step of forming a semiconductor thin film layer on the pad oxide film, and a step of forming the semiconductor substrate on the semiconductor thin film layer A step of selectively forming an oxidation resistant film pattern on an upper part of an active region of the semiconductor thin film, and the semiconductor thin film is selectively formed on a region not covered with the oxidation resistant film pattern by thermal oxidation using the oxidation resistant film pattern as a mask. A step of forming a field oxide film formed by oxidizing a layer and a part of the semiconductor substrate, a step of removing the oxidation resistant film pattern to expose a residual semiconductor thin film layer thereunder, the residual semiconductor thin film layer and the field Forming a conductor layer on the oxide film, patterning the conductor layer and the residual semiconductor thin film layer, and covering the region to be the active region on the pad oxide film functioning as a gate oxide film. A method for manufacturing a semiconductor device according to the present invention, which includes a step of forming a gate electrode composed of a laminated body of a residual semiconductor thin film layer and a conductor layer, or a step of forming a pad oxide film on a semiconductor substrate, the pad oxide film A step of forming a semiconductor thin film layer thereon, a step of forming an oxidation resistant film pattern on the semiconductor thin film layer to selectively cover an upper portion of an active region of the semiconductor substrate, a heat treatment using the oxidation resistant film pattern as a mask. A step of selectively forming a field oxide film formed by oxidizing a part of the semiconductor thin film layer and the semiconductor substrate in a region which is not covered with the oxidation resistant film pattern by oxidation; A step of removing the semiconductor thin film layer to expose the pad oxide film on a region to be the active region; a step of forming a conductor layer on the pad oxide film and the field oxide film; A method of manufacturing a semiconductor device according to the present invention, which comprises a step of forming a gate electrode made of the conductor layer on the pad oxide film that functions as a gate oxide film by covering a region that becomes the active region by turning. A step of forming a silicon oxynitride film for a pad on a substrate, a step of forming a semiconductor thin film layer on the silicon oxynitride film for a pad, and selecting an upper portion of a region to be an active region of the semiconductor substrate on the semiconductor thin film layer A step of forming an oxide-resistant film pattern that covers the surface of the semiconductor thin film, the oxide-resistant film pattern is used as a mask to selectively remove the exposed semiconductor thin film layer and the silicon oxynitride film below it, and cover the oxide-resistant film pattern. The step of exposing the surface of the semiconductor substrate to the uncovered area, thermal oxidation is performed using the oxidation resistant film pattern as a mask, and the semiconductor substrate surface in the area not covered by the oxidation resistant film pattern is exposed. A step of forming a field oxide film, a step of removing the oxidation resistant film pattern and exposing a residual semiconductor thin film layer thereunder,
A step of forming a conductor layer on the residual semiconductor thin film layer and the field oxide film; patterning the conductor layer and the residual semiconductor thin film layer to cover the region to be the active region and to function as a gate insulating film Method for manufacturing a semiconductor device according to the present invention, which comprises a step of forming a gate electrode composed of a laminated body of the residual semiconductor thin film layer and the conductor layer on the silicon oxynitride film for use, or oxidation for a pad on a semiconductor substrate. A step of forming a silicon nitride film, a step of forming a semiconductor thin film layer on the pad silicon oxynitride film, and an oxidation resistant film which selectively covers an upper portion of an active region of the semiconductor substrate on the semiconductor thin film layer. A step of forming a pattern, the semiconductor thin film layer and the silicon oxynitride film are selectively removed by using the oxidation resistant film pattern as a mask, and a region not covered with the oxidation resistant film pattern is formed. A step of exposing the conductor substrate surface, a step of performing thermal oxidation using the oxidation resistant film pattern as a mask to form a field oxide film on the semiconductor substrate surface in a region not covered by the oxidation resistant film pattern, the oxidation resistant film pattern And then removing the residual semiconductor thin film layer thereunder to expose the pad silicon oxynitride film thereunder,
A step of forming a conductor layer on the pad silicon oxynitride film and the field oxide film, patterning the conductor layer, and covering the region to be the active region and functioning as a gate insulating film. This is achieved by the method for manufacturing a semiconductor device according to the present invention, which has a step of forming a gate electrode made of the conductor layer on the film.

[0018]

The main feature of the method of the present invention is the polybuffered L.
When a field oxide film is formed by the OCOS method, a pad oxide film for stress relaxation or a silicon oxynitride film for a pad, which is provided below an oxidation resistant film pattern used as a mask for selective oxidation, is formed into a field oxide film. After that, the pad oxide film or the silicon oxynitride film for the pad is used as it is as a gate insulating film without being removed by an etching means such as wet etching, and is left on the active region as it is.
Forming an IS type semiconductor device.

As described above, since the pad oxide film or the silicon oxynitride film for the pad is not removed by etching, a step portion in which a silicon surface having a plane orientation other than (100) is exposed at the peripheral portion of the area to be the active area. Is not formed, an increase in the interface state at that portion is avoided, and at the same time, the pad oxide film or the silicon oxynitride film for pad is used as it is as the gate insulating film, so that Since the film thickness does not decrease at the peripheral portion, the quality and reliability of the gate are improved.

Furthermore, in order to improve the film quality of the gate oxide film, after forming the gate oxide film or after forming a semiconductor layer (usually a polycrystalline or amorphous silicon layer) to be a gate electrode on the gate oxide film. , Some heat treatment (900 ~
It is desirable to apply 1000 ° C for about 30 minutes). But,
With miniaturization of transistors due to high integration of LSI,
The heat treatment allowed for the formation of these is unavoidably reduced. For example, in the case of a fine transistor with a gate width of 0.5 μm or less, it is 800
There is no heat treatment at or above ℃, and new heat treatment at about 900 ℃ for the purpose of improving the film quality of the gate oxide film is not allowed from the viewpoint of suppressing the diffusion of impurities. However, in the method of the present invention, since the pad oxide film which will later become the gate oxide film is formed before the field oxide film is formed, the conventional heat treatment for forming the field oxide film can be effectively utilized for improving the film quality. It is possible to improve the film quality of the gate oxide film without newly increasing the heat treatment.

That is, in the method of the present invention, since the pad oxide film or the silicon oxynitride film for pads used for the gate insulating film is subjected to sufficient heat treatment at a high temperature of about 1000 ° C. in the selective oxidation (LOCOS) step,
The quality and reliability of the gate insulating film can be improved in an LSI or the like in which a new gate insulating film cannot be formed after the field oxide film is formed and heat treatment at a sufficiently high temperature cannot be performed thereafter.

[0022]

EXAMPLES The present invention will now be described in detail by way of examples with reference to the drawings. 1 and 2 are process cross-sectional views of the first embodiment of the present invention, FIG. 3 is a process cross-sectional view of the second embodiment of the present invention,
FIG. 4 is a process sectional view of the third embodiment of the present invention, and FIG. 5 is a process sectional view of the fourth embodiment of the present invention. The same object is denoted by the same reference numeral throughout the drawings.

First, the invention described in claim 1 will be concretely described with reference to FIG. 1 by a first embodiment. Refer to FIG. 1 (a) When forming a MOS type semiconductor device using the invention of claim 1, for example, a pad oxide film having a thickness of about 30 Å is formed on a p-type silicon (Si) substrate 1 by a conventional thermal oxidation means. A pad SiO ₂ film 2 is formed, and then a polycrystalline Si buffer layer 3 having a thickness of about 100 Å, which is a semiconductor thin film layer, is formed thereon by a CVD method, and then an oxidation resistant film is formed thereon by an ordinary CVD method. A silicon nitride (Si ₃ N ₄ ) film 5 having a thickness of about 1100Å is formed.

Referring to FIG. 1 (b), the Si ₃ N ₄ film 4 is then subjected to reactive ion etching using, for example, [CF ₄ + CHF ₃ ] as an etching gas, using a resist pattern (not shown) formed by an ordinary lithography method as a mask. Si ₃ N which is patterned by the (RIE) process and selectively covers the upper part of the element formation region 4 which is a region which becomes an active region of the Si substrate 1 on the polycrystalline Si buffer layer 3.
_{A four} film pattern 5P is formed. In addition, after the Si ₃ N ₄ film pattern 5P is formed, the polycrystalline Si buffer layer 3 exposed around it is formed.
May be removed.

See FIG. 1 (c).₃N_FourWet using the film pattern 5P as a mask
About 65 minutes at about 1000 ℃ in oxygen, or about 200 minutes at 900 ℃
Selective oxidation (LOCOS oxidation)₃N_FourMembrane pattern 5P
Si surrounding the covered element formation region 4₃N_FourCover with membrane pattern 5P
The surface of the polycrystalline Si buffer layer 3 and the Si substrate 1 in the uncovered region
Selectively oxidize the surface area to provide a thickness for element isolation in that area.
A field oxide film 6 of about 3000 Å is formed. This
When Si₃N _FourPad Si under the film pattern 5P
O₂Since the thickness of the film 2 is extremely thin, around 30Å, the device formation area
The extension of the bird's beak on the area 4 is suppressed to a very small width.
(Features of poly-buffered LOCOS).

Next, referring to FIG. 1 (d), the Si ₃ N ₄ film pattern 5P is removed by a phosphoric acid boil treatment to expose the end portions of the polycrystalline Si buffer layer 3 and the field oxide film 6 remaining thereunder.

Then, referring to FIG. 1 (e), by a normal CVD method, a multi-layer having a thickness of about 3000 Å is formed on the substrate, that is, on the element forming region 4 covered by the poly-Si buffer layer 3 and on the field oxide film 6. The crystalline Si electrode layer 7 is formed, and then, for example, n-type impurities are introduced at a high concentration into the polycrystalline Si electrode layer 7 to impart high conductivity.

Then, referring to FIG. 1 (f), the polycrystalline Si electrode layer 7 is formed by using a resist pattern (not shown) formed by ordinary lithography means as a mask.
And the polycrystalline Si buffer layer 3 thereunder are collectively patterned by RIE processing using a gas such as chlorine, and the pad SiO ₂ film 2 that functions as a gate SiO ₂ film in the element formation region 4 is formed.
A laminated Si gate electrode 8 is formed by laminating the polycrystalline Si buffer layer 3 and the polycrystalline Si electrode layer 7 on top.

As is apparent from the above description, in the method of the present invention, the LOC of the field oxide film 6 is formed.
At the time of OS oxidation, the pad SiO ₂ film 2 formed as a base film for stress relaxation under the Si ₃ N ₄ film of the oxidation resistant mask is used as it is as the gate SiO ₂ film. Then, as in the conventional method, after the formation of the field oxide film is completed, the pad SiO _{2 is}
The film 2 is removed by etching, and the film is oxidized again to form the gate SiO ₂
No new film is formed. Therefore, as in the prior art, the parts other than (100) were exposed at the peripheral edge of the element formation region 4.
The stepped portion of the Si substrate 1 is not formed. for that reason,
The problems of increasing the interface state and thinning of the gate oxide film, which have conventionally occurred in the stepped portion, can be avoided and the quality and reliability of the gate can be improved, and at the same time, the pad used for the gate SiO ₂ film SiO ₂ Since the film 2 is sufficiently subjected to the heat treatment at a high temperature of about 1000 ° C. at the time of LOCOS oxidation, the quality and reliability of the gate SiO ₂ film itself are improved.

Subsequent processes are shown in process sectional views in directions different from those in FIG. See FIG. 2 (a). Then, according to a usual method for manufacturing a MOS type semiconductor device, the exposed pad SiO ₂ is formed by using the laminated Si gate electrode 8 as a mask.
An n-type impurity phosphorus (P) is ion-implanted at a low concentration into the element formation region 4 through the film 2. Reference numeral 9 indicates a low concentration P implantation region.

Next, referring to FIG. 2 (b), Si is formed on the side surface of the gate electrode 8 by a known method.
An O ₂ sidewall 10 is formed, and then the n-type impurity arsenic (As) is ion-implanted at a high concentration using the gate electrode 8 having the SiO ₂ sidewall 10 as a mask. 11 is high concentration As
The implantation area is shown.

Next, as shown in FIG. 2 (c), a short time heat treatment at 900 to 1000 ° C. is performed,
By activating the ion-implanted P and As, n ⁻ type (low concentration) source region 9S, n ⁻ type (low concentration) drain region 9D, n ⁺ type (high concentration) source region 11S and n ⁺ type A (high concentration) drain region 11D is formed.

Then, although not shown, an interlayer insulating film is formed on the substrate as usual, and contact holes for exposing the high-concentration source region, the high-concentration drain region, etc. are formed in the interlayer insulating film, and a normal wiring is formed. By forming technique, for example, an Al alloy wiring that is connected to the source region, the drain region, etc. through the contact hole is formed on the interlayer insulating film, and L
The MOS semiconductor device having the DD structure is completed.

Next, the invention described in claim 2 will be concretely described by the second embodiment with reference to FIG. Refer to FIG. 3 (a). The method of claim 2 is the same as in FIG. 1 (a) in the first embodiment.
~ After forming the field oxide film 6 for element isolation around the area which becomes an active area, that is, the element forming area 4 through the process of FIG. 1 (c), the Si ₃ N ₄ film pattern 5P is removed by boiling phosphate. , The polycrystalline Si buffer layer 3 thereunder is removed by a dry etching means using a chlorine (Cl) -based gas.
As shown in (a), the pad SiO ₂ film 2 is exposed on the element forming region 4. Here, as a means for dry etching with a Cl-based gas, the substrate is immersed in a Cl-based gas for 200
A method of irradiating the surface of the polycrystalline Si buffer layer 3 covering the element formation region 4 of the substrate with ultraviolet light or plasma for generating neutral atoms in the state of heating to ˜700 ° C. This is a desirable method because the selection ratio with respect to the pad SiO ₂ film 2 therebelow can be made large and the film thickness of the pad SiO ₂ film 2 which will later become a gate oxide film does not change.

Next, referring to FIG. 3B, a polycrystalline Si electrode layer 7 having a thickness of about 3000 Å is formed on the pad SiO ₂ film 2 and the field oxide film 6, and then the polycrystalline Si electrode layer 7 is formed with, for example, n. A high concentration of type impurities is introduced to provide high conductivity.

Next, referring to FIG. 3 (c), the polycrystalline Si electrode layer 7 is formed by using a resist pattern (not shown) formed by ordinary lithography means as a mask.
Is patterned by RIE treatment with chlorine-based gas,
A polycrystalline Si gate electrode 7G composed of a polycrystalline Si electrode layer 7 is formed on the pad SiO ₂ film 2 which functions as a gate oxide film in the element formation region 4.

After that, the MOS type semiconductor device is formed through the same steps as those of the first embodiment shown in FIG. Also in this method, since the pad SiO ₂ film 2 is left as it is on the element formation region 4 and used as a gate oxide film, the conventional pad SiO ₂ film is removed to the peripheral portion of the element formation region as in the first embodiment. The stepped portion of the Si substrate that has occurred is not formed, and the same effect as in the first embodiment is produced.

When a thicker gate SiO ₂ film is required for controlling the threshold voltage, the pad SiO ₂ film 2 is exposed as shown in FIG. 3 (a) in the second embodiment. After that, the film thickness of the pad SiO ₂ film 2 may be increased to a predetermined thickness by further performing additional thermal oxidation for a predetermined time in a temperature range of 800 to 1100 ° C. in an oxidizing atmosphere.

If the additional heat treatment is performed in a non-oxidizing gas such as an inert gas, it is possible to further improve the film quality without increasing the film thickness. Next, the invention described in claim 4 will be concretely described by a third embodiment with reference to FIG.

The present invention is applied when a silicon oxynitride (SiON) film is used as the gate insulating film. See FIG. 4 (a). In the method of claim 4, for example, the thickness is first formed on the p-type Si substrate 1.
A SiON film 12 for a pad having a thickness of about 30Å is formed.

The SiON film 12 is formed by the following method, for example.
The above Si substrate in an atmosphere containing ammonia and argon 7
A thermal nitride film is formed on the Si surface by treatment at 00 ° C. for about 10 minutes, and then this Si substrate is treated in oxygen at 900 ° C. for about 30 minutes to transform the thermal nitride film into an oxynitride Si (SiON) film. At this time, the nitrogen content in the SiON film is preferably about 20%.

In addition, after forming the oxide film, heat treatment is performed in, for example, an ammonia atmosphere to nitride the oxide film to form Si.
Direct ON / OFF method, CVD method, or sputtering method
You may perform by the method etc. which form a SiON film.

Then, a polycrystalline Si buffer layer 3 having a thickness of about 100 Å is formed on the SiON film 12 by the same method as in the above embodiment.
Then, a Si ₃ N ₄ film pattern 5P of an anti-oxidation mask is formed on the polycrystalline Si buffer layer 3 by a method similar to that of the above-described embodiment to selectively cover the active region, that is, the upper portion of the element forming region 4. To form.

See FIG. 4 (b).₃N_FourWith the film pattern 5P as a mask, Cl-based gas is used.
Si by RIE process₃N _FourAppears around the membrane pattern 5P
After selectively removing the polycrystalline Si buffer layer 3, the lower part
From the SiON film 12 that prevents selective oxidation_FourSystem gas
Element formation area 4
Around Si₃N_FourSemiconductor substrate not covered with film pattern 5P
Make one plate exposed.

Next, as shown in FIG. 4 (c), the field oxide film 6 is formed around the element formation region 4 to isolate the elements from each other by performing selective oxidation in wet oxygen using the Si ₃ N ₄ film pattern 5P as a mask as in the above embodiment. To form.

Next, referring to FIG. 4 (d), the Si ₃ N ₄ film pattern 5P is removed by boiled phosphoric acid treatment to expose the end portions of the polycrystalline Si buffer layer 3 and the field oxide film 6 remaining thereunder.

Next, referring to FIG. 4 (e), by a normal CVD method, a multi-layer having a thickness of about 3000 Å is formed on the substrate, that is, on the element forming region 4 covered with the poly-Si buffer layer 3 and on the field oxide film 6. The crystalline Si electrode layer 7 is formed, and then, for example, n-type impurities are introduced at a high concentration into the polycrystalline Si electrode layer 7 to impart high conductivity.

Next, referring to FIG. 4 (f), the polycrystalline Si electrode layer 7 is formed by using a resist pattern (not shown) formed by ordinary lithography means as a mask.
And the polycrystalline Si buffer layer 3 thereunder are collectively patterned by RIE treatment using a gas such as chlorine-based gas, and the pad SiON that functions as a gate insulating film in the element formation region 4 is formed.
A laminated Si gate electrode 8 is formed by laminating a polycrystalline Si buffer layer 3 and a polycrystalline Si electrode layer 7 on the film 2.

Then, in the first embodiment, as shown in FIG.
The MOS type semiconductor device using the invention of claim 4 is completed through the normal manufacturing process as described with reference to (c). Next, the invention described in claim 5 will be concretely described by a fourth embodiment with reference to FIG.

Refer to FIG. 5 (a). The method of claim 5 is the same as in FIG. 4 (a) in the third embodiment.
After forming the field oxide film 6 for element isolation around the area to be an active area, that is, the element forming area 4 through the steps (c) to (c), the Si ₃ N ₄ film pattern 5P is removed by boiling phosphate, The lower polycrystalline Si buffer layer 3 is removed by the dry etching method using the Cl-based gas described in the second embodiment, and the pad Si is formed on the element formation region 4 as shown in FIG. 5 (a).
The ON film 12 is exposed.

Next, referring to FIG. 5B, a polycrystalline Si electrode layer 7 having a thickness of about 3000 Å is formed on the pad SiON film 12 and the field oxide film 6 by a CVD method, and then the polycrystalline Si electrode layer 7 is formed. For example, n-type impurities are introduced at a high concentration to provide high conductivity.

Next, as shown in FIG. 5C, the polycrystalline Si electrode layer 7 is formed by using a resist pattern (not shown) formed by ordinary lithography means as a mask.
Is patterned by RIE treatment with chlorine-based gas,
A polycrystalline Si gate electrode 7G made of a polycrystalline Si electrode layer 7 is formed on the pad SiON film 12 which functions as a gate insulating film in the element formation region 4.

Then, in the first embodiment, as shown in FIG.
The MOS type semiconductor device using the invention of claim 5 is completed through the normal manufacturing process as described with reference to (c).

[0054]

As described above, according to the present invention, after the field oxide film is formed by the polybuffered LOCOS method, the pad oxide film or the pad oxynitride for the pad provided under the oxidation resistant mask film pattern is formed. Since the silicon film is used as it is as the gate insulating film, it is not removed by etching. As a result, the stepped portion where the silicon surface having a plane orientation other than (100) is exposed is not formed at the peripheral edge of the element formation area that becomes the active area, and the increase of the interface state at that portion is avoided. It Further, as described above, since the pad oxide film or the pad silicon oxynitride film is used as it is as the gate insulating film, the film thickness of the gate insulating film at the peripheral portion of the active region does not become thin.

The pad oxide film or the silicon oxynitride film for a pad used as the gate insulating film is a gate oxide film or a gate in the selective oxidation (LOCOS) process.
Since the heat treatment at about 900 to 1000 ° C, which is necessary for improving the film quality of the SiON film, has been applied, the film quality can be improved even in VLSIs that cannot be subjected to sufficiently high temperature heat treatment after the field oxide film is formed. And a sufficiently reliable gate insulating film can be obtained.

From the above points, according to the present invention, it is possible to improve the quality and reliability of the gate in a semiconductor device that is extremely highly integrated and highly integrated, and to contribute to the improvement of the performance and reliability of VLSI and the like. large.

[Brief description of drawings]

FIG. 1 is a process sectional view of a first embodiment of the present invention (No. 1)

FIG. 2 is a process sectional view of the first embodiment of the present invention (No. 2)

FIG. 3 is a process sectional view of a second embodiment of the present invention.

FIG. 4 is a process sectional view of a third embodiment of the present invention.

FIG. 5 is a process sectional view of a fourth embodiment of the present invention.

FIG. 6 is a process sectional view of a conventional method.

[Explanation of symbols]

1 p-type Si substrate 2 pad SiO ₂ film 3 polycrystalline Si buffer layer 4 element formation region (active region) 5 Si ₃ N ₄ film 5P Si ₃ N ₄ film pattern 6 field oxide film 7 polycrystalline Si electrode layer 7G Polycrystalline Si gate electrode 8 Laminated Si gate electrode

Claims (7)

[Claims] 1. A step of forming a pad oxide film on a semiconductor substrate, a step of forming a semiconductor thin film layer on the pad oxide film, and selecting an upper portion of a region to be an active region of the semiconductor substrate on the semiconductor thin film layer. A step of forming an oxidation resistant film pattern that covers the semiconductor thin film layer and a part of the semiconductor substrate selectively by thermal oxidation using the oxidation resistant film pattern as a mask in a region not covered by the oxidation resistant film pattern. Forming a field oxide film, removing the oxidation resistant film pattern to expose the residual semiconductor thin film layer thereunder, and forming a conductor layer on the residual semiconductor thin film layer and the field oxide film. A step of patterning the conductor layer and the residual semiconductor thin film layer, and covering the region to be the active region with the residual semiconductor thin film layer and the conductor layer on a pad oxide film functioning as a gate oxide film. And a step of forming a gate electrode composed of the stacked body of. 2. A step of forming a pad oxide film on a semiconductor substrate, a step of forming a semiconductor thin film layer on the pad oxide film, and selecting an upper portion of a region to be an active region of the semiconductor substrate on the semiconductor thin film layer. A step of forming an oxidation resistant film pattern that covers the semiconductor thin film layer and a part of the semiconductor substrate selectively by thermal oxidation using the oxidation resistant film pattern as a mask in a region not covered by the oxidation resistant film pattern. A step of forming a field oxide film, the step of removing the oxidation resistant film pattern and the residual semiconductor thin film layer thereunder to expose the pad oxide film on a region to be the active region, Forming a conductor layer on a field oxide film, patterning the conductor layer, covering the region to be the active region, and forming the conductor layer on the pad oxide film functioning as a gate oxide film A method of manufacturing a semiconductor device, comprising the step of forming a gate electrode. 3. The method according to claim 2, wherein the pad oxide film on the region to be the active region is exposed, and the conductor layer is formed on the pad oxide film and the field oxide film. And a step of increasing the film thickness of the pad oxide film by means of a thermal oxidation means. 4. A step of forming a silicon oxynitride film for a pad on a semiconductor substrate, a step of forming a semiconductor thin film layer on the silicon oxynitride film for a pad, and an active region of the semiconductor substrate on the semiconductor thin film layer. A step of selectively forming an oxidation resistant film pattern covering the upper part of the region to be formed, using the oxidation resistant film pattern as a mask to selectively remove the exposed semiconductor thin film layer and the silicon oxynitride film thereunder, A step of exposing the semiconductor substrate surface in a region not covered with the oxidation resistant film pattern, and performing thermal oxidation with the oxidation resistant film pattern as a mask to form a field oxide film on the semiconductor substrate surface in the region not covered with the oxidation resistant film pattern. A step of removing the oxidation resistant film pattern to expose a residual semiconductor thin film layer thereunder, and a step of forming a conductor layer on the residual semiconductor thin film layer and the field oxide film. Patterning the conductor layer and the residual semiconductor thin film layer, covering the region to be the active region, and forming the residual semiconductor thin film layer and the conductor layer on the silicon oxynitride film for pad which functions as a gate insulating film. A method of manufacturing a semiconductor device, comprising the step of forming a gate electrode formed of a laminated body. 5. A step of forming a pad silicon oxynitride film on a semiconductor substrate, a step of forming a semiconductor thin film layer on the pad silicon oxynitride film, and an active region of the semiconductor substrate on the semiconductor thin film layer. A step of selectively forming an oxidation resistant film pattern covering the upper part of the region, the semiconductor thin film layer and the silicon oxynitride film are selectively removed by using the oxidation resistant film pattern as a mask, and the oxidation resistant film pattern is covered. Exposing the surface of the semiconductor substrate to an unprotected region; performing thermal oxidation using the oxidation resistant film pattern as a mask to form a field oxide film on the surface of the semiconductor substrate not covered by the oxidation resistant pattern; A step of removing the oxidation resistant film pattern and then removing the residual semiconductor thin film layer thereunder to expose the pad silicon oxynitride film thereunder; And a step of forming a conductor layer on the field oxide film, patterning the conductor layer, covering the region to be the active region, and forming the conductor layer on the pad silicon oxynitride film that functions as a gate insulating film. A method of manufacturing a semiconductor device, comprising the step of forming a gate electrode made of. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor thin film layer is formed of an amorphous or polycrystalline silicon thin film layer. 7. The method according to claim 2, 3 or 5, wherein the residual semiconductor thin film layer on the pad oxide film or the pad silicon oxynitride film is removed by dry etching means using a chlorine-based gas. Manufacturing method of semiconductor device.