JPH0855845A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Summary] [Objective] Regarding a method of manufacturing a semiconductor device, by reducing a bird's beak while using a conventional ordinary LOCOS method,
By increasing the area occupation ratio of the element active region, a margin of alignment between the contact hole and the element active region is secured. A selective oxidation mask layer 3 formed in a single manufacturing step is patterned twice to perform selective oxidation twice, and a relatively thin element isolation selective oxide film 10 is formed in an internal circuit region. A selective oxide film 11 for element isolation which is formed and is thicker than the selective oxide film in the internal circuit area in the peripheral circuit area
To form.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a MOS type semiconductor integrated circuit such as DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). The present invention relates to a method of forming an element isolation region of a device.

[0002]

2. Description of the Related Art Conventionally, when improving the degree of integration of a semiconductor integrated circuit device, the alignment between contact holes and element active regions such as transistors has been a problem.
Both the diameter of the contact hole and the line width of the element active region and the wiring layer are reduced as the degree of integration is improved. However, the reduction ratio (scale ratio) of the contact hole is the line width of the element active region and the wiring layer. Is smaller than the reduction ratio of.

This is due to the shape of the resist for forming the contact hole or the wiring pattern, that is, the difference in accuracy between the residual pattern and the blank pattern, and the residual pattern, that is, the accurate pattern can be easily formed, that is, ,
The line width of the wiring pattern can be easily reduced, but it is difficult to form an accurate pattern.
This is because the size of the contact hole cannot be easily reduced.

Further, in view of the operation of the element, when there is a contact hole which is not opened, it has a great influence on the operation of the element, so that the contact hole may be provided with a margin. This is smaller than the reduction ratio of the line widths of the element active region and the wiring layer.

Therefore, when the degree of integration is improved, the reduction ratio of the diameter of the contact hole becomes smaller than the reduction ratio of the element active region when the contact hole and the element active region are aligned. There is a problem that the wrinkling comes to the alignment, and the alignment margin cannot be sufficiently obtained.

Such a problem is caused especially by DRAM and SR.
This is an important problem in the alignment of the cell area such as AM.
The production yield of AM and the like is greatly affected.

In order to solve such a problem, an insulating film for element isolation, that is, a LOCOS film (selective oxide film) is formed in order to make an element active region such as a transistor as large as possible in a cell region having the same area. Attempts have been made to reduce bird's beaks.

As one of the solutions, there is a polybuffer LOCOS method which is an improvement of the conventional ordinary LOCOS method. This is a method of depositing a polycrystalline silicon film on the entire surface of a semiconductor substrate and then masking a silicon nitride film pattern. As described above, the polycrystalline silicon is oxidized by wet oxidation to form an element isolation insulating film.

[0009]

However, even when the polybuffer LOCOS method as described above is used, bird's beaks cannot be sufficiently reduced, and the obtained element isolation shape is good. There is also a problem that it is not, and it is difficult to sufficiently improve the integration degree.

Therefore, the present invention provides a conventional conventional LO.
By using the COS method, bird's beaks are reduced and the area occupancy ratio of the element active region is increased to secure a margin of alignment between the contact hole and the element active region.

[0011]

According to the present invention, in a method of manufacturing a semiconductor device, a selective oxidation mask layer (3 in FIG. 2) formed in one manufacturing step is patterned twice to be selected twice. Oxidation is performed to form a relatively thin selective oxide film for element isolation (10 in FIG. 2) in the internal circuit region, and a selective oxide film in the internal circuit region (see FIG. 2) in the peripheral circuit region.
10) thicker than the selective oxide film for element isolation (1 in FIG. 2).
1) is formed.

[0012]

Since the selective oxide film for element isolation in the element region for the internal circuit is formed by one selective oxidation step, the selective oxidation film for element isolation in the peripheral circuit element region formed by two selective oxidation steps is formed. Since it can be made thinner than the film, bird's beaks are reduced in the internal circuit element region, and a high dielectric breakdown voltage is maintained in the peripheral circuit element region by the relatively thick element isolation selective oxide film.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 and 2 are the first embodiment of the present invention. In the first selective oxidation step, a step of manufacturing an element isolation region in which a thick selective oxide film is formed in a peripheral circuit element area (peripheral part) It is a figure explaining. In the figure, for convenience, the internal circuit area (cell portion) and the peripheral circuit area (peripheral portion) are shown close to each other.

First, referring to FIG. 1A, a silicon oxide semiconductor substrate 1 is initially oxidized by a hydrochloric acid oxidation method at a temperature of 900 ° C. to form a pad oxide film 2 having a thickness of 100 Å, and then a CVD film is formed thereon. By law 1
A silicon nitride film 3 having a thickness of 500Å is deposited. Next, as shown in FIG. 1B, the photoresist pattern 4 is formed by etching the photoresist so that the pattern corresponding to the selective oxidation region of the peripheral circuit region becomes a blank pattern.

1C, the exposed portion of the silicon nitride film 3 is removed by etching using the photoresist pattern 4 as a mask, and then the photoresist pattern 4 is removed. Next, as shown in FIG. 1D, the selective oxide film 6 having a thickness of 2500 Å is formed by wet oxidation with the substrate temperature set to 900 ° C.

Next, as shown in FIG. 2E, after a new photoresist is applied, the selective oxidation region of the internal circuit region (cell portion), that is, the pattern corresponding to the well oxidation region 8 is changed to a void pattern. A second photoresist pattern 7 is formed by etching the photoresist.

2F, the exposed portion of the silicon nitride film 3 is removed by etching using the photoresist pattern 7 as a mask, the photoresist pattern 7 is removed, and boron (B) for forming a well is formed at 180 KeV. 1 × 10 ¹³ c in acceleration energy
Approximately 0.6μ by implanting a dose of m ^-2
The ion implantation region 9 is formed at a depth of m.

Next, referring to FIG. 2G, a well oxide film 10 of about 500 Å is formed by oxidizing the hydrochloric acid with the substrate temperature kept at 900 ° C. At the time of this well oxidation, the selective oxidation region 5 is further added. The selective oxide film 11 which is oxidized and has an increased thickness is formed.
The well oxidation means that a silicon nitride film or a silicon oxynitride film is formed on the surface of the silicon semiconductor substrate 1 during activation annealing of the well region in a nitrogen atmosphere, which adversely affects the film quality of the gate oxide film. In order to prevent the influence, it is an oxidation for forming an oxide film of about 500 Å formed prior to annealing.

Then, with the substrate temperature kept at about 1100 ° C., annealing is performed in a nitrogen atmosphere for 300 minutes to diffuse and activate the implanted ions to form a well region 12 having a depth of about 3.0 μm. After that, the channel cut region 13 is formed so as to be in contact with the increased selective oxide film 11 by ion-implanting boron with a dose amount of 5 × 10 ¹³ cm ⁻² at an acceleration energy of 180 KeV.

In this case, in the internal circuit region, although ion for channel cutting is implanted into a deep region and does not function as a channel cutting region so much, the withstand voltage required in the internal circuit region is not so high. Problem does not occur.

2 (h) Finally, by removing the silicon nitride film 3 used as a mask in the selective oxidation, the well oxide film 10, that is, the internal circuit element separated by the thin selective oxide film. The active region and the peripheral circuit element active region separated by the thick selective oxide film 11 are defined.

The manufacturing conditions in the above embodiment are as follows:
It is not limited to the specific numerical values described,
For example, the thickness of the initial oxide film 2 is in the range of 50 to 100Å, the thickness of the nitride film 3 is in the range of 1000 to 1500Å,
The thickness of the selective oxide film 6 is in the range of 2000 to 4000Å,
The thickness of the well oxide film 10 may be in the range of 300 to 600 Å. Also, in the ion implantation for forming the well, it is necessary to implant the ions with the acceleration energy that passes through the silicon nitride film 3 and the selective oxide film 6, and the acceleration energy depends on the thickness of the silicon nitride film 3 and the selective oxide film 6. Is appropriately determined.

FIG. 3 and FIG. 4 explain a manufacturing process of an element isolation region in which a thin well oxide film is formed in the peripheral circuit region (peripheral portion) in the first selective oxidation process according to the second embodiment of the present invention. It is a figure. In the figure, for convenience, the internal circuit area (cell portion) and the peripheral circuit area (peripheral portion) are shown close to each other.

Referring to FIGS. 3A to 3C, the purpose of forming the silicon nitride film 3 pattern in the steps of FIGS. 3A to 3C in the second embodiment is to form a well oxide film. Although it is different from the purpose of forming a selective oxide film in the first embodiment, the process itself is completely the same as the process of FIGS. 1A to 1C in the first embodiment, and the description thereof will be omitted.

Referring to FIG. 3D, the well oxide region 8 is formed in the silicon nitride film 3 shown in FIG.
After forming the opening corresponding to
1 × 10 at an acceleration energy of 180 KeV ¹³cm^-2
By implanting a dose of about 0.6 μm
An ion implantation region is formed at the depth. Then the substrate temperature
About 500 by oxidizing with hydrochloric acid at 900 ℃
After forming the well oxide film 10 of Å, increase the substrate temperature to about 1
Keep the temperature at 100 ℃ in a nitrogen atmosphere for 300 minutes.
Nealing diffuses and activates the implanted impurities.
Forming the well region 12.

Next, referring to FIG. 4 (e), after coating a new photoresist, the photoresist is etched so that the pattern corresponding to the selective oxidation region 5 in the internal circuit region (cell portion) becomes a blank pattern. As a result, the second photoresist pattern 7
To form.

Next, referring to FIG. 4F, the exposed portion of the silicon nitride film 3 is removed by etching using the photoresist pattern 7 as a mask, the photoresist pattern 7 is removed, and boron for forming a channel cut region is replaced with a silicon nitride film. 2 that does not pass through 3
The shallow channel cut region 13 is formed by ion-implanting a dose amount of 5 × 10 ¹³ cm ⁻² with an acceleration energy of 0 KeV.

Next, referring to FIG. 4 (g), a selective oxide film 6 of about 2500 Å is formed by wet oxidation at a substrate temperature of 900 ° C., and the well oxide region 8 is further added during this selective oxidation. The selective oxide film 11 which is oxidized and has an increased thickness is formed.

Finally, as shown in FIG. 4 (h), by removing the silicon nitride film 3 used as a mask during the selective oxidation, the element active region for the internal circuit separated by the selective oxide film 6 and the thick and increased selection are formed. Peripheral circuit element active regions separated by oxide film 11 are defined.

In the second embodiment, the selective oxide film for element isolation in the internal circuit region is thicker than that in the first embodiment, but the internal circuit region and The degree of integration is improved as compared with the case where a selective oxide film for element isolation in the peripheral circuit region is formed.

The manufacturing conditions in the second embodiment are not limited to the specific numerical values described, and in the same steps as in the first embodiment, the manufacturing conditions are the same as those in the first embodiment. It may be performed in the same range.

In each of the above-mentioned embodiments, although the conductivity type of the silicon semiconductor substrate is not mentioned, in the DRAM etc., it is generally an n-channel type M.
Since the OSFET is formed, a p-type well may be formed by ion implantation of boron, which is a p-type impurity, and an n-type substrate or a p-type substrate may be used.

Although the specific element structures provided in the respective regions are not shown in each of the above embodiments, the present invention is not limited to the MOS type semiconductor integrated circuit device such as the DRAM or the SRAM, but is of the bipolar type. A semiconductor integrated circuit device or a BI-MOS type semiconductor integrated circuit device is also intended.

[0034]

According to the present invention, the conventional ordinary LOCO is used.
By performing the selective oxidation twice while using the S method, in the peripheral circuit region, the selective oxidation film for element isolation is formed thick to increase the withstand voltage and the internal circuit region where high integration is required. In the above, the selective oxide film for element isolation can be formed thin to reduce bird's beaks. Therefore, by increasing the area occupation ratio of the element active region, it is possible to secure a margin of alignment between the contact hole and the element active region, so that the manufacturing yield can be improved.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a manufacturing process up to the middle of the first embodiment of the present invention.

FIG. 2 is a diagram illustrating a manufacturing process of the first embodiment of the present invention after FIG. 1;

FIG. 3 is a diagram illustrating a manufacturing process up to the middle of the second embodiment of the present invention.

FIG. 4 is a diagram for explaining the manufacturing process of the second embodiment of the present invention after FIG. 3;

[Explanation of symbols]

 1 Silicon Semiconductor Substrate 2 Pad Oxide Film 3 Silicon Nitride Film 4 Photoresist Pattern 5 Selective Oxide Region 6 Selective Oxide Film 7 Second Photoresist Pattern 8 Well Oxide Region 9 Ion Implantation Region 10 Well Oxide Film 11 Increased Selective Oxide Film 12 Well area 13 Channel cut area

Claims (8)

[Claims] 1. A selective oxidation mask layer formed in a single manufacturing process is patterned twice to perform selective oxidation twice, and a relatively thin element isolation selective oxide film is formed in an internal circuit region. A method of manufacturing a semiconductor device, comprising: forming a selective oxide film for element isolation, which is thicker than a selective oxide film of an internal circuit region in the peripheral circuit region. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the selective oxide film provided in the peripheral circuit region is formed by two selective oxidation steps. 3. The method of manufacturing a semiconductor device according to claim 2, wherein the second selective oxidation step of the two selective oxidation steps is a well oxidation step. 4. The method of manufacturing a semiconductor device according to claim 3, wherein ion implantation is performed to form a channel cut region after the second selective oxidation step in the two selective oxidation steps. 5. The method of manufacturing a semiconductor device according to claim 2, wherein the first selective oxidation step of the two selective oxidation steps is a well oxidation step. 6. Ion implantation is performed to form a channel cut region after the first selective oxidation step in the second selective oxidation step and before the second selective oxidation step. The method for manufacturing a semiconductor device according to claim 5. 7. The method of manufacturing a semiconductor device according to claim 1, wherein the selective oxidation film provided in the internal circuit region is formed by a second selective oxidation step. . 8. The impurity for forming a well region is ion-implanted into a semiconductor substrate after the first selective oxidation step in the two selective oxidation steps. Item 1. A method of manufacturing a semiconductor device according to item 1.