JPH0855932A - TGA type semiconductor device - Google Patents

TGA type semiconductor device

Info

Publication number
JPH0855932A
JPH0855932A JP20930394A JP20930394A JPH0855932A JP H0855932 A JPH0855932 A JP H0855932A JP 20930394 A JP20930394 A JP 20930394A JP 20930394 A JP20930394 A JP 20930394A JP H0855932 A JPH0855932 A JP H0855932A
Authority
JP
Japan
Prior art keywords
semiconductor device
hole
type semiconductor
semiconductor element
bonding material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20930394A
Other languages
Japanese (ja)
Other versions
JP3076953B2 (en
Inventor
Katsufusa Fujita
勝房 藤田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsui High Tec Inc
Original Assignee
Mitsui High Tec Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsui High Tec Inc filed Critical Mitsui High Tec Inc
Priority to JP20930394A priority Critical patent/JP3076953B2/en
Publication of JPH0855932A publication Critical patent/JPH0855932A/en
Application granted granted Critical
Publication of JP3076953B2 publication Critical patent/JP3076953B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465Application of solder
    • H05K3/3485Application of solder paste, slurry or powder
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • H05K3/368Assembling printed circuits with other printed circuits parallel to each other
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

(57)【要約】 【目的】 本発明の目的とするところは、半導体装置の
接続端子の狭ビッチ化に際しても、実装及び取扱いが容
易な信頼性の高い接続構造を備えた半導体装置を提供す
ることにある。 【構成】 半導体装置の特定領域に、格子状に配列して
形成されたスルーホール20を設け、該スルーホール2
0の内部に充填した導電性接合材料25と、その内周面
に、加熱されることによって流動化した前記導電性接合
材料25を前記スルーホール20の内周面から容易に離
脱させることが可能な導体層20bとからなる構成とさ
れている。
(57) [Abstract] [Object] An object of the present invention is to provide a semiconductor device having a highly reliable connection structure that is easy to mount and handle even when the connection terminals of the semiconductor device are narrowed. Especially. [Structure] Through holes 20 arranged in a lattice are provided in a specific region of a semiconductor device.
It is possible to easily separate the conductive bonding material 25 filling the inside of 0 and the conductive bonding material 25 fluidized by heating on the inner peripheral surface thereof from the inner peripheral surface of the through hole 20. And a different conductor layer 20b.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、TGA型半導体装置に
係る、詳細には、半導体素子搭載基板の上面側の導電回
路パターンと下面側の導電配線パターンとを連通した貫
通孔の内周面に導体層を設けたスルーホールの構成に関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a TGA type semiconductor device, and more particularly, to an inner peripheral surface of a through hole which connects a conductive circuit pattern on the upper surface side and a conductive wiring pattern on the lower surface side of a semiconductor element mounting substrate. The present invention relates to the structure of a through hole provided with a conductor layer.

【0002】[0002]

【従来の技術】従来、IC、LSI等の半導体装置は、
実装基板(プリント基板)上の配線パターンの接続端子
に半田などを用いて接続されている。これらは、多数本
の端子リードが樹脂封止体の周縁部から突出したDI
P、SOP、QFPなどのほかに、BGA(ボール・グ
リッド・アレイ)と指称され、半導体素子搭載基板の下
面側に半田ボールが形成されており、該半田ボールを用
いて実装基板上に搭載し、接続する半導体装置が提案さ
れている。この半導体装置を実装基板(プリント基板)
に実装するには、前記実装基板上の配線パターンに載置
し、位置決めを行い、加熱により固着を行えばよく、実
装が容易であることから注目されている。
2. Description of the Related Art Conventionally, semiconductor devices such as IC and LSI are
It is connected to a connection terminal of a wiring pattern on a mounting board (printed board) by using solder or the like. These are DIs in which a large number of terminal leads protrude from the peripheral edge of the resin encapsulant.
In addition to P, SOP, QFP, etc., it is referred to as BGA (ball grid array), and solder balls are formed on the lower surface side of the semiconductor element mounting board, and the solder balls are used to mount on the mounting board. , Semiconductor devices for connection have been proposed. This semiconductor device is mounted on a board (printed board)
In order to mount the device, it is necessary to place it on the wiring pattern on the mounting board, position it, and fix it by heating.

【0003】この一例として、例えば米国特許番号第5
216278に記載されたものがある。この半導体装置
は、貫通孔の内周面に銅めっき層からなる導体層を形成
したスルーホールを設け、両面に回路パターンが形成さ
れた半導体素子搭載基板と、その表面に半導体素子を搭
載し、ボンディングワイヤの一端部を前記半導体素子の
電極パットの一つに接続し、その他端部を前記回路パタ
ーンの端子リードの一つに接続して電気的導通回路を形
成し、その表面側を封止樹脂で封止した樹脂封止体と、
前記基板の裏面側にソルダー・ボール(半田ボール)を
形成してなるいわゆるBGA(ボール・グリッド・アレ
イ)がある。
As an example of this, for example, US Pat. No. 5
216278. This semiconductor device is provided with a through hole in which a conductor layer made of a copper plating layer is formed on the inner peripheral surface of a through hole, and a semiconductor element mounting board having circuit patterns formed on both sides, and a semiconductor element mounted on the surface thereof. One end of the bonding wire is connected to one of the electrode pads of the semiconductor element, and the other end is connected to one of the terminal leads of the circuit pattern to form an electrical conduction circuit, and the surface side thereof is sealed. A resin-sealed body sealed with a resin,
There is a so-called BGA (ball grid array) in which solder balls (solder balls) are formed on the back surface side of the substrate.

【0004】このような、BGA(ボール・グリッド・
アレイ)型の半導体装置の実装基板への実装は、実装基
板(プリント基板)上の配線パターンの接続端子にクリ
ーム半田もしくはフラックスを塗布し、前記接続端子に
前記ソルダー・ボール(半田ボール)を位置決めさせ、
その後、リフロー装置に通して加熱を行ってソルダー・
ボール(半田ボール)を溶融し、実装基板(プリント基
板)上の接続端子に接続されて完了する。
Such a BGA (ball grid
When mounting an array type semiconductor device on a mounting board, cream solder or flux is applied to the connection terminals of the wiring pattern on the mounting board (printed circuit board) and the solder balls (solder balls) are positioned on the connection terminals. Let
After that, it is passed through a reflow device to heat the solder and
The balls (solder balls) are melted and connected to the connection terminals on the mounting board (printed board) to complete the process.

【0005】[0005]

【発明が解決しようとする課題】しかしながら、この種
の半導体装置の裏面には、ソルダー・ボール(半田ボー
ル)が設けられているので、搬送等の取扱いの際に、ソ
ルダー・ボールの脱落や損傷が生じ、表面状態が悪化し
てボンディング特性が低下する等の問題があった。その
ため、これを保護するキャリアを必要とし、半導体装置
のコストが高くなるという問題があった。
However, since a solder ball (solder ball) is provided on the back surface of this type of semiconductor device, the solder ball may fall off or be damaged during handling such as transportation. Occurs, and the surface condition is deteriorated and the bonding characteristics are deteriorated. Therefore, there is a problem that a carrier for protecting this is required and the cost of the semiconductor device is increased.

【0006】また、実装の際に、リフロー装置により溶
融したソルダー・ボール(半田ボール)が接合加圧もし
くは自重により潰れ、ソルダー・ボール径が大きくな
り、接続端子領域からはみ出して他の接続端子や端子リ
ードなどとの間に半田ブリッジが形成される虞があり、
狭ピッチ化された微細なパターンとの接続に対応できな
いという問題があった。
Further, at the time of mounting, the solder balls (solder balls) melted by the reflow device are crushed by the bonding pressure or the self-weight, the diameter of the solder balls is increased, and the solder balls protrude from the connection terminal area and other connection terminals or There is a risk that a solder bridge will be formed between the terminal lead, etc.,
There is a problem that it cannot be connected to a fine pattern with a narrow pitch.

【0007】本発明は、上記の実情に鑑みてなされたも
のであって、狭ピッチ化された微細なパターンとの接続
に際しても、実装及び取扱いが容易な信頼性の高い接続
構造を備えた半導体装置を提供することを目的とする。
The present invention has been made in view of the above circumstances, and is a semiconductor having a highly reliable connection structure that is easy to mount and handle even when connecting to a fine pattern with a narrow pitch. The purpose is to provide a device.

【0008】[0008]

【問題を解決するための手段】上記の目的に沿う本発明
の特徴とするところは、半導体装置の特定領域に形成さ
れたスルーホールの内部に充填した導電性接合材料を加
熱することにより、流動化し、前記スルーホールの内周
面から導電性接合材料を解離・離脱させる導体層を設け
た構成にしたことにある。すなわち、請求項1記載のT
GA型半導体装置は、半導体素子搭載基板の特定領域
に、格子状に配列したスルーホールを配し、前記半導体
素子搭載基板の上面側に半導体素子が搭載されていると
共に、その周辺を取り囲むように、該半導体素子の電極
端子に内部接続された電気的導通回路が形成されたTG
A(スルーホール・グリッド・アレイ)型半導体装置に
あって、前記スルーホールの内周面に、導電性接合材料
を容易に解離させるNiなどからなる導体層を設けると
共に、前記スルーホールの内部に前記導体層から容易に
離脱するクリーム半田などの導電性接合材料を充填して
成ることを特徴とする構造とされている。
In order to solve the problems, the present invention is characterized in that a conductive bonding material filled in a through hole formed in a specific region of a semiconductor device is heated to flow. And a conductor layer for dissociating and separating the conductive bonding material from the inner peripheral surface of the through hole is provided. That is, T in claim 1
The GA type semiconductor device has through holes arranged in a grid pattern in a specific region of the semiconductor element mounting substrate, the semiconductor elements are mounted on the upper surface side of the semiconductor element mounting substrate, and the periphery thereof is surrounded. TG formed with an electrical conduction circuit internally connected to the electrode terminals of the semiconductor element
In an A (through hole grid array) type semiconductor device, a conductor layer made of Ni or the like that easily dissociates a conductive bonding material is provided on the inner peripheral surface of the through hole, and the inside of the through hole is provided. The structure is characterized by being filled with a conductive bonding material such as cream solder that easily separates from the conductor layer.

【0009】[0009]

【作用】本発明の請求項1記載のTGA型半導体装置に
よれば、スルーホールの内部に充填された導電性接合材
料と、スルーホールの内周面に前記導電性接合材料を容
易に離脱させることの可能な導体層とを設けているの
で、これを加熱することにより、電気的結合に必要なだ
けの量の前記導電性接合材料がスルーホールの内周面か
ら実装基板の接続端子領域に離脱し、前記TGA型半導
体装置を実装基板の接続端子に容易に接合することがで
きる。 これによって、実装基板の極めて高精度で微細
な接続端子の狭ピッチ化に対応することができる。
According to the TGA type semiconductor device of the first aspect of the present invention, the conductive bonding material filled in the through hole and the conductive bonding material are easily separated from the inner peripheral surface of the through hole. Since it is provided with a conductor layer capable of forming a conductive layer, by heating this, the conductive bonding material in an amount necessary for electrical coupling is transferred from the inner peripheral surface of the through hole to the connection terminal area of the mounting board. After detaching, the TGA type semiconductor device can be easily joined to the connection terminal of the mounting substrate. This makes it possible to cope with extremely high precision and fine pitch of the connection terminals of the mounting board.

【0010】また、半導体装置の裏面側にソルダー・ボ
ール(半田ボール)の突起物を形成する必要がなく、半
導体装置の製造工程が簡素化されるので、従来技術に比
べて、その実装及びその取り扱いが容易となり、ボンデ
ィング特性を著しく向上させると共に、生産性を著しく
向上させる。
Further, since it is not necessary to form a projection of a solder ball on the back surface side of the semiconductor device, and the manufacturing process of the semiconductor device is simplified, its mounting and its mounting are improved as compared with the prior art. It facilitates handling, significantly improves bonding characteristics, and significantly improves productivity.

【0011】さらにまた、半導体装置と実装基板との接
合の良否の確認は、上面側から導電性接合材料の離脱状
態の有無を確認する簡単な外観検査で行うことができ
る。
Furthermore, the quality of the bonding between the semiconductor device and the mounting substrate can be confirmed by a simple visual inspection for confirming whether or not the conductive bonding material is separated from the upper surface side.

【0012】[0012]

【実施例】続いて、本発明の一実施例について添付図面
に基づき説明する。
Next, an embodiment of the present invention will be described with reference to the accompanying drawings.

【0013】ここで、図1は本発明の実施例に係るTG
A型半導体装置を示す平面図、図2は本発明の実施例に
係るTGA型半導体装置の構成の概要を示す断面図、図
3は本発明の実施例に係るTGA型半導体装置に設けた
スルホールの構成の概要を示す部分断面図、図4は本発
明の実施例に係る半導体装置の実装状態の概要を示す断
面図である。
Here, FIG. 1 shows a TG according to an embodiment of the present invention.
2 is a plan view showing an A-type semiconductor device, FIG. 2 is a cross-sectional view showing an outline of the configuration of a TGA type semiconductor device according to an embodiment of the present invention, and FIG. 3 is a through hole provided in the TGA type semiconductor device according to an embodiment of the present invention. 4 is a partial cross-sectional view showing the outline of the configuration of FIG. 4, and FIG. 4 is a cross-sectional view showing the outline of the mounted state of the semiconductor device according to the embodiment of the present invention.

【0014】まず、図1、2に示すように、本発明の実
施例に係るTGA型半導体装置10は、四辺形のガラス
・クロス・エポキシ樹脂から成り、アディティブ法もし
くはサブトラクティブ法などの慣用手段で形成された半
導体素子搭載基板11の上面側に形成された半導体素子
搭載層12に半導体素子13が搭載されている。
First, as shown in FIGS. 1 and 2, a TGA type semiconductor device 10 according to an embodiment of the present invention is made of a quadrangular glass cloth epoxy resin, and is formed by a conventional method such as an additive method or a subtractive method. The semiconductor element 13 is mounted on the semiconductor element mounting layer 12 formed on the upper surface side of the semiconductor element mounting substrate 11 formed in step a.

【0015】そして、一端部が前記半導体素子13の電
極端子14の1っに、他端部が前記基板11の上面側に
形成された導体回路パターン15の端子リード16の1
っに、ボンディングワイヤ17が接続されて電気的導通
回路が形成されている。
One end of one of the electrode terminals 14 of the semiconductor element 13 and the other end of the terminal lead 16 of the conductor circuit pattern 15 formed on the upper surface of the substrate 11 are connected.
First, the bonding wire 17 is connected to form an electrical conduction circuit.

【0016】これら前記半導体素子13、ボンディング
ワイヤ17及び導体回路パターン15の一端部側が封止
樹脂で樹脂封止されている。
One ends of the semiconductor element 13, the bonding wire 17 and the conductor circuit pattern 15 are resin-sealed with a sealing resin.

【0017】ここで、前記半導体装置10においては、
前記基板11の外縁部に沿ってその内部側に、前記基板
11の上面側に形成された導体回路パターン15とその
下面側に形成された導体配線パターン18の外部接続パ
ット19とを電気的に接続するスルーホール20が形成
されている。
Here, in the semiconductor device 10,
The conductor circuit pattern 15 formed on the upper surface side of the substrate 11 and the external connection pad 19 of the conductor wiring pattern 18 formed on the lower surface side of the board 11 are electrically connected to the inside along the outer edge of the board 11. Through holes 20 for connection are formed.

【0018】しかも、前記スルーホール20には、その
内周面に導電性接合材料25を容易に離脱させることが
可能な前記導体層20bが設けてあり、その内部には、
導電性接合材料25が充填された図1、2に示す構成と
されている。
In addition, the through hole 20 is provided with the conductor layer 20b on the inner peripheral surface thereof, from which the conductive bonding material 25 can be easily separated, and inside thereof,
1 and 2 filled with the conductive bonding material 25.

【0019】ここで実施の一例として、前記スルーホー
ル20の導体層20bは、内層から表層に向かって、銅
めっき層21、ニッケルめつき層22が積層されてい
る。また、その内部に充填された導電性接合材料25に
は、導電性接合材料25の一例であるクリーム半田25
aが慣用の手段で充填されている。さらに、半導体素子
搭載基板の所要部分には、絶縁体の一例であるソルダー
レジストによりカバーコート26が形成されている。
As an example of implementation, the conductor layer 20b of the through hole 20 has a copper plating layer 21 and a nickel plating layer 22 laminated from the inner layer toward the surface layer. In addition, the conductive bonding material 25 filled in the inside is a cream solder 25 which is an example of the conductive bonding material 25.
a is filled by conventional means. Further, a cover coat 26 is formed on a required portion of the semiconductor element mounting substrate with a solder resist which is an example of an insulator.

【0020】続いて、本発明の一実施例に係るTGA型
半導体装置10の実装にあっては、図4に示すように、
実装基板(PWB)23のボンディング端子24のボン
ディング位置上に、TGA型半導体装置を吸着した図示
していない移載ヘッドを移動することにより、前記ボン
ディング端子のそれぞれに対応するTGA型半導体装置
のスルーホール20を位置決めし、移載ヘッドを降下さ
せてTGA型半導体装置10を前記実装基板に載置す
る。
Subsequently, in mounting the TGA type semiconductor device 10 according to one embodiment of the present invention, as shown in FIG.
By moving a transfer head (not shown) that holds the TGA type semiconductor device onto the bonding position of the bonding terminal 24 of the mounting board (PWB) 23, the TGA type semiconductor device corresponding to each of the bonding terminals is passed through. The hole 20 is positioned, and the transfer head is lowered to mount the TGA type semiconductor device 10 on the mounting substrate.

【0021】次に、この実装基板23を図示していない
リフロー装置内に搬入して加熱すると、前記スルーホー
ル内部に充填されているクリーム半田25が溶融し流動
性がよくなり、該クリーム半田25が前記スルーホール
の内周面の導体層20bから自重で離脱し、前記TGA
型半導体装置10と前記実装基板23とが接合されて実
装が完了する。
Next, when the mounting board 23 is carried into a reflow device (not shown) and heated, the cream solder 25 filling the inside of the through hole is melted and the fluidity is improved, and the cream solder 25 is melted. From the conductor layer 20b on the inner peripheral surface of the through hole by its own weight,
The mold semiconductor device 10 and the mounting board 23 are joined to complete the mounting.

【0022】ここで、実装基板のボンディング端子24
にスクリーン印刷法により、クリーム半田を薄く塗布し
た実装基板を用いれば、より接合性を向上させることが
できる。また、本構成では、接続に必要な量のクリーム
半田が離脱するので接合半田がボンディング端子24領
域の範囲内に納まり、従来技術のBGA型半導体装置の
実装の際に生じていた、リフロー時に溶融したソルダー
ボールが、BGA型半導体装置の自重または接合加圧で
押し潰され、ボンディング端子24領域からはみ出して
隣接する他ボンディング端子24領域間で半田ブリッジ
が形成される虞がなくなる。これによって、半導体装置
の端子リード間隔をより狭ピッチ化の要望に対応するこ
とができる。
Here, the bonding terminal 24 of the mounting substrate
If the mounting substrate on which the cream solder is thinly applied by the screen printing method is used, the bondability can be further improved. Further, in this configuration, since the amount of cream solder necessary for connection is released, the bonding solder is kept within the range of the bonding terminal 24 area and melted at the time of reflow, which occurred when mounting the BGA type semiconductor device of the related art. There is no possibility that the solder balls thus formed are crushed by the weight of the BGA type semiconductor device or the bonding pressure of the BGA type semiconductor device, and are squeezed out of the bonding terminal 24 area to form a solder bridge between the adjacent other bonding terminal 24 areas. This makes it possible to meet the demand for a narrower pitch between the terminal leads of the semiconductor device.

【0023】以上、実施例に基づき説明したが、本発明
はこれら実施例に限定されるものではなく、要旨を逸脱
しない範囲での設計などの変更があっても本願に含まれ
る。
Although the present invention has been described above based on the embodiments, the present invention is not limited to these embodiments, and changes in design and the like without departing from the scope of the invention are included in the present application.

【0024】[0024]

【発明の効果】以上説明してきたように、本発明のTG
A型半導体装置によれば、内周面には容易に導電性接合
材料を離脱させることが可能な導体層を形成すると共
に、その内部に導電性接合材料を充填したスルーホール
を設けているので、従来技術のBGA型半導体装置に比
べて、ソルダーボールの形成が不要となる。その結果と
して、取扱いが容易になり生産効率が著しく向上し、製
造コストの低減化が図れる。 さらに、半導体装置の端
子リード間隔の狭ピッチ化の要望に対応することができ
る。しかも、接続状態を従来の様な高価なX線検査装置
などを使用することなく簡単なカメラなどの装置で外観
検査を行うことができる。
As described above, the TG of the present invention
According to the A-type semiconductor device, the inner peripheral surface is provided with the conductor layer capable of easily releasing the conductive bonding material, and the through hole filled with the conductive bonding material is provided therein. As compared with the BGA type semiconductor device of the prior art, the formation of solder balls is unnecessary. As a result, the handling becomes easy, the production efficiency is remarkably improved, and the manufacturing cost can be reduced. Furthermore, it is possible to meet the demand for a narrower pitch of the terminal leads of the semiconductor device. Moreover, the connection state can be inspected by a simple device such as a camera without using a conventional expensive X-ray inspection device.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の実施例に係るTGA型半導体装置を示
す平面図である。
FIG. 1 is a plan view showing a TGA type semiconductor device according to an embodiment of the invention.

【図2】本発明の実施例に係るTGA型半導体装置の構
成の概要を示す断面図である。
FIG. 2 is a cross-sectional view showing the outline of the configuration of a TGA type semiconductor device according to an embodiment of the invention.

【図3】本発明の実施例に係るTGA型半導体装置に設
けたスルーホールの構成の概要を示す部分断面図であ
る。
FIG. 3 is a partial cross-sectional view showing the outline of the configuration of through holes provided in the TGA type semiconductor device according to the embodiment of the invention.

【図4】本発明の実施例に係る半導体装置の実装状態の
概要を示す断面図である。
FIG. 4 is a cross-sectional view showing an outline of a mounted state of a semiconductor device according to an example of the present invention.

【符号の説明】[Explanation of symbols]

10 TGA型半導体装置 11 半導体素子基板 12 半導体素子搭載層 13 半導体素子 14 半導体素子の電極端子 15 導体回路パターン 16 端子リード 17 ボンディングワイヤ 18 導体配線パターン 19 外部接続パット 20 スルーホール 20a 貫通孔 20b 導体層 21 銅めっき層 22 ニッケルめっき層 23 実装基板(PWB) 24 ボンディング端子 25 導電性接合材料 25a クリーム半田 26 カバーコート DESCRIPTION OF SYMBOLS 10 TGA type semiconductor device 11 Semiconductor element substrate 12 Semiconductor element mounting layer 13 Semiconductor element 14 Electrode terminal of semiconductor element 15 Conductor circuit pattern 16 Terminal lead 17 Bonding wire 18 Conductor wiring pattern 19 External connection pad 20 Through hole 20a Through hole 20b Conductor layer 21 Copper Plating Layer 22 Nickel Plating Layer 23 Mounting Board (PWB) 24 Bonding Terminal 25 Conductive Bonding Material 25a Cream Solder 26 Cover Coat

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体素子搭載基板の特定領域に、格子
状に配列したスルーホールを配し、前記半導体素子搭載
基板の上面側に半導体素子が搭載されていると共に、そ
の周辺を取り囲むように、該半導体素子の電極端子に内
部接続された電気的導通回路が形成されたTGA(スル
ーホール・グリッド・アレイ)型半導体装置にあって、
前記スルーホールの内周面に、導電性接合材料を容易に
解離させるNiなどからなる導体層を設けると共に、前
記スルーホールの内部に前記導体層から容易に離脱する
クリーム半田などの導電性接合材料を充填して成ること
を特徴とするTGA型半導体装置の製造方法。
1. A through hole arranged in a grid pattern is arranged in a specific region of a semiconductor element mounting substrate, the semiconductor element is mounted on the upper surface side of the semiconductor element mounting substrate, and the periphery thereof is surrounded. A TGA (through hole grid array) type semiconductor device in which an electrical conduction circuit internally connected to an electrode terminal of the semiconductor element is formed,
A conductive layer made of Ni or the like that easily dissociates the conductive bonding material is provided on the inner peripheral surface of the through hole, and a conductive bonding material such as cream solder that easily separates from the conductive layer inside the through hole. And a TGA type semiconductor device manufacturing method.
JP20930394A 1994-08-09 1994-08-09 TGA type semiconductor device Expired - Fee Related JP3076953B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20930394A JP3076953B2 (en) 1994-08-09 1994-08-09 TGA type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20930394A JP3076953B2 (en) 1994-08-09 1994-08-09 TGA type semiconductor device

Publications (2)

Publication Number Publication Date
JPH0855932A true JPH0855932A (en) 1996-02-27
JP3076953B2 JP3076953B2 (en) 2000-08-14

Family

ID=16570726

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20930394A Expired - Fee Related JP3076953B2 (en) 1994-08-09 1994-08-09 TGA type semiconductor device

Country Status (1)

Country Link
JP (1) JP3076953B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0942636A3 (en) * 1998-03-12 2001-03-14 Lucent Technologies Inc. Solder bonding printed circuit board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0942636A3 (en) * 1998-03-12 2001-03-14 Lucent Technologies Inc. Solder bonding printed circuit board

Also Published As

Publication number Publication date
JP3076953B2 (en) 2000-08-14

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