JPH0855971A - Master slice type gate array - Google Patents

Abstract

(57) [Abstract] [Purpose] To provide a gate array of a master slice type for miniaturizing a chip and improving the basic performance of the gate array. [Configuration] The special basic cell 101 is formed by arranging a first cell 100 and a second cell 200 adjacent to each other. First
Cell 100 has two PMOSs 102 and two NMOs.
S4 and the shared diffusion region 1 having an area sufficient to provide the contact region 14 only on the NMOS4 side.
Source / drain region 1 on the side of the PMOS 102
A space for providing the contact region 14 is not provided in 12. The second cell 200 has two PMOSs 2
And the two NMOSs 204, and the shared diffusion region 12 having an area sufficient to provide the contact region only on the PMOS 2 side, and the source / on the NMOS 204 side.
The drain region 212 is not provided with a space for providing the contact region 14. As a result, the chip area becomes smaller.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a master slice type gate array, and more particularly to a master slice type gate array for reducing the size of a master slice silicon chip and improving the basic performance of the gate array.

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a structure of a basic cell of a gate array formed on a conventional master slice silicon chip (hereinafter referred to as a chip). As shown in FIG. 4, the basic cell 1 normally includes two PMOSs 2.
And two NMOSs 4, and they are arranged with this as a basic unit. Each PMOS 2 and NMOS 4 shares a diffusion layer with a gate region 6 formed of polysilicon or the like, regions 8 and 10 which are diffusion regions, and adjacent PMOS or NMOS in order to draw out each gate, source and drain terminal. A shared diffusion region 12 is provided. Since it is a master-slice type gate array, each area 6, 8, 10 and 12 requires a minimum area for providing a contact hole for connection with a wiring in order to maintain versatility. In other words, each area 6, 8, 10, 12
It has a sufficient area for providing a region (contact region) 14 for providing a contact hole.

Alternatively, in the basic cell 1 shown in FIG. 1, since the terminals are often used by being connected to each other, the NMOS gate terminals arranged at both ends and the PMOS are arranged.
In some cases, it may be connected to the gate terminal in advance. Even if they are connected in advance in this way, there is no problem with the NAND, NOR and inverter. Further, there is a basic cell in which a smaller NMOS for RAM is attached.

Semi-customized L such as gate array
While SI has the advantages of shortening the development period and responding to small-lot and high-mix production, it is not possible to remove the unused elements that are provided in advance on the chip, resulting in poor utilization efficiency of the chip area and miniaturization. It has the disadvantage of causing waste in the LSI. In order to overcome this disadvantage, it is desired to miniaturize the gate array itself and to efficiently use the basic cell included in the chip.

Conventionally, in order to further reduce the chip area in the structure of various basic cells as described above, Japanese Unexamined Patent Publication No.
Japanese Patent No. 283049 discloses a configuration in which a sub-potential region is not provided for each basic cell but is provided collectively for each of a plurality of basic cells to actually reduce the well area and reduce the chip area. .

Further, in Japanese Patent Laid-Open No. 60-145642, a wiring structure is formed into a three-dimensional multilayer structure, and this wiring region is provided on a basic cell to improve the wiring efficiency of each basic cell, thereby reducing the chip area. A configuration is disclosed.

[0007]

By the way, in a gate array, it is often the case that a plurality of PMOSs or NMOSs are connected in series to form a circuit having a predetermined function. For example, in a 2-input NOR circuit, two PM
OS and two NMOSs in a 2-input NAND circuit are respectively connected in series, and in any case, the shared diffusion region is not connected to any part. Such circuits are often used in practice and can account for over 30% of all basic cells.

However, in the prior art, since the cell structure itself of the basic cell is all the same, the shared diffusion region occupying a considerable part of the cell area is not actually needed when the position wiring is performed as described above. In some cases, it must be reserved. In other words, since it is a gate array, it must be secured regardless of whether it is used or not, which is wasteful.

A resistance is generated in proportion to the length of the diffusion layer between the two transistors. If the length of the shared diffusion region is wide as described above, it acts as a parasitic resistance and delays. Since the time becomes long, the switching speed of the circuit becomes slow.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a master slice type gate array for reducing the size of a chip and improving the basic performance of the gate array. It is in.

[0011]

In order to achieve the above object, the invention according to claim 1 provides an NMOS and a PM.
In a master slice type gate array in which basic cells including an OS are arranged in an array, a first cell having a shared diffusion region having an area sufficient to provide a contact region only on the NMOS side and a PMOS side only A second cell having a shared diffusion region having an area sufficient to provide a contact region, the first cell and the second cell
It is characterized in that it includes a special basic cell which is arranged adjacent to the cell of.

According to a second aspect of the present invention, in the master slice type gate array according to the first aspect, the special basic cells are mixedly arranged at a predetermined ratio.

[0013]

According to the master-slice type gate array of the present invention having the above-described structure, an area sufficient to provide a contact region only on the PMOS or NMOS side of the first cell and the second cell is provided. The area of each cell can be reduced by the provision of the shared diffusion region. By arranging the first cell and the second cell adjacent to each other to form a special basic cell, the area of the chip can be reduced. By using this special basic cell, the PMOS
It is possible to form a circuit having a predetermined function by connecting each other or NMOSs in series.

By providing the special basic cells in a mixed manner on the chip, the chip area can be reduced.

Further, the parasitic resistance in the narrowed shared diffusion region can be reduced.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings. The same elements as those in the conventional example are designated by the same reference numerals.

FIG. 1 is a diagram showing a special basic cell arranged in an array on a chip in this embodiment. The special basic cell 101 includes a first cell 100 and a second cell 20.
It is formed by the arrangement adjacent to 0. First cell 100
Has two PMOSs 102 and two NMOSs 4, and is provided with a shared diffusion region having an area sufficient to provide a contact region only on the NMOS 4 side. The first cell 100 in FIG. 1 is a 2-input NO.
An R circuit is formed, and a contact region 14 is provided in the source / drain region 12 which is a shared diffusion region on the NMOS 4 side. In the case of a 2-input NOR circuit, the PMOS 102 side is connected in series, and thus the source / drain region 112 which is a shared diffusion region does not require a contact region. Therefore, the source / drain region 112 on the PMOS 102 side is not provided with a space for providing a contact region.

On the other hand, the second cell 200 has two PMOs.
It has S2 and two NMOSs 204, and a PMOS
A shared diffusion region having an area sufficient to provide a contact region only on the second side is provided. The second cell 200 in FIG. 1 forms a 2-input NAND circuit, and the contact region 14 is provided in the source / drain region 12 which is the shared diffusion region on the PMOS 2 side. On the NMOS 204 side, in the case of a 2-input NAND circuit,
Source / which is a shared diffusion region because it is connected in series
No contact region is required for the drain region 212. Therefore, the source / drain region 212, which is the shared diffusion region on the NMOS 204 side, has no space for providing a contact region. Note that FIG. 2 is a circuit diagram of the special basic cell shown in FIG.
The R circuit and the two-input NAND circuit on the right side.

The above first cell 100 and second cell 20
0 is the cell 100, 2 due to the narrowed source / drain regions 112, 212 of either NMOS or PMOS.
The shape of 00 can be made small, and can actually be L-shaped. A special basic cell is constructed by arranging the L-shaped protruding portions of the two so as to be aligned with the recessed portions of each other. As a result, the area can be reduced as compared to the case where two conventionally used basic cells shown in FIG. 3 are arranged side by side. Therefore, when a chip is configured with the same number of basic cells, the area of the chip can be reduced. By making the source / drain regions 112 and 212 as narrow as possible, the area efficiency thereof is reduced by about 10% as compared with the case of the two basic cells shown in FIG.

By the way, as described above, the NOR circuit,
A circuit such as a NAND circuit in which two NMOSs or PMOSs are connected in series and a shared diffusion region is not connected anywhere is often used in practice, and a circuit of all basic cells is used.
It may exceed%.

Therefore, if the special basic cells and the standard basic cells are mixedly arranged at a predetermined ratio, for example, 3: 7, to form a gate array, the area is reduced by about 3% as a whole. Therefore, the size of the chip can be reduced and the basic cell can be efficiently used.

Further, by narrowing the source / drain regions 112 and 212 which do not require contact regions,
It is also possible to reduce the parasitic resistance proportional to the length between the two transistors. In fact, the sheet resistance between the series connections can be reduced to less than half, thus improving the basic performance of the circuit.

According to this embodiment, it is possible to provide a basic cell in which a shared diffusion region which is not only unnecessary but adversely affects the basic performance of the circuit is eliminated.

Furthermore, by mixing the standard basic cells in a predetermined ratio, not only the chip area can be reduced but also the basic performance of the circuit can be improved.

In the above embodiment, the 2-input NOR circuit and the 2-input NAND circuit are taken as an example, but a plurality of PMOSs are used.
The present invention is not limited to this as long as they are connected to each other or NMOSs in series.

[0026]

As described above, according to the present invention, in each cell, the shared diffusion region which requires the contact region has a sufficient area, and the shared diffusion region which does not have the contact region does not need the contact region, and the region is not required. Since the cell area is narrowed, the cell area can be reduced, and as a result, the chip area can be reduced.

By arranging the special basic cells according to the present invention and the standard basic cells in a mixed manner at a predetermined ratio, the chip can be downsized and the basic cells can be efficiently used. Is possible.

Further, since the chip area can be reduced, the number of chips that can be cut from one wafer can be increased, and the yield can be improved.

Further, since the resistance value parasitic on the narrowed shared diffusion region can be reduced by the above structure, the switching speed can be increased and the basic performance of the circuit can be improved. .

[Brief description of drawings]

FIG. 1 is a diagram showing an embodiment of a gate array of a master slice system according to the present invention, showing a special basic cell arranged on a chip.

FIG. 2 is a circuit diagram of the special basic cell shown in FIG.

FIG. 3 is a diagram in which two conventionally used basic cells are arranged side by side.

FIG. 4 is a diagram showing a structure of a basic cell of a conventional gate array.

[Explanation of symbols]

 2, 102 PMOS 4, 204 NMOS 12, 112, 212 Source / drain region 14 Contact region 100 First cell 101 Special basic cell 200 Second cell

Claims (2)

[Claims] 1. A master slice type gate array in which basic cells including NMOS and PMOS are arranged in an array, and a first diffusion layer having a shared diffusion region having a sufficient area for providing a contact region only on the NMOS side. A cell and a second cell having a shared diffusion region having a sufficient area for providing a contact region only on the PMOS side, and the first cell and the second cell are arranged adjacent to each other. A master slice type gate array characterized by including a special basic cell. 2. The master slice type gate array according to claim 1, wherein the special basic cells are mixedly arranged at a predetermined ratio.