JPH0863509A - Simulation method - Google Patents

Abstract

(57) [Summary] [Purpose] When incorporating a part designed by a design system with a delay formula into a part designed by a design system with another delay formula, incorporate the entire part without re-characterizing. A simulation method capable of performing the above is provided. [Structure] The delay time for each logic gate in the macro module unit 18 and the gate array unit 17 that composes the end-debed array type SOG LSI 19 is obtained (step 101, step 103), and the delay file 1 in which they are stored,
The delay time for each logic gate is read from step 2 (step 105), the read results are written on the simulation model (step 106), and the delay simulation is performed (step 107).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is a simulation for an LSI, and in particular, an LS capable of achieving a higher density by incorporating a high-density module (megacell, memory, etc.) that does not depend on the substrate.
It relates to a simulation method in I design.

[0002]

2. Description of the Related Art In a conventional delay simulation at the time of designing an LSI (a logic simulation in which the signal propagation time of each logic gate is taken into consideration), a signal propagates on each logic gate before the simulation for LSI design is executed. The required time (delay time) is calculated by using a delay calculation program prepared in advance, the delay time is written in the desired simulation model, and then the simulation model in which the delay time is written is used. I was doing a simulation for LSI design. In the delay calculation program, a delay formula (table) is prepared in advance by, for example, creating a library of delay parameters (load capacitance dependency coefficient, etc.) for each gate.
Connection information between gates that differs for each LSI (netlist)
The delay time at each gate is calculated by inputting the above and the respective wiring capacitances. Usually, it takes several months to extract (characterize) delay parameters of all gates in one library.

[0003]

However, like the embedded array type SOG type gate array LSI which has been rapidly popularized in recent years, a macro module designed by an LSI design system for standard cells (such as a mega cell or a memory Density module) is used by embedding it in a chip designed by a gate array LSI design system, and when each LSI design system adopts a different delay type, the entire macro module is used for the gate array. There was a problem that the delay simulation of the entire chip could not be performed unless it was re-characterized for the delay formula of the LSI design system. Especially macro modules
RAM (random access memory), etc., which are automatically generated by a module generator and, when incorporating them into an LSI, re-characterization of the entire module has been a major cause of increasing the design period.

The present invention has been made in view of the above-mentioned problems, and a portion A (group) designed by a design system having a certain delay type is designed to be a portion B (group) designed by another design system having a delay type. It is an object of the present invention to provide a simulation method capable of being incorporated without re-characterizing the entire part A when incorporating it into a group) (see FIG. 7). A further object of the present invention is to provide a simulation method that enables a plurality of LSIs designed by design systems having different delay formulas to be simulated as one system.

[0005]

In a simulation method for designing a chip in which a plurality of parts designed by at least two or more different design systems are installed in any part, an output gate of the part to be installed is incorporated. The part design system characterizes and the part design system to be incorporated receives capacitance information of the input pin of the part to be incorporated and performs delay simulation. In a simulation method for designing a plurality of parts designed by at least two or more different design systems as one system, an output gate of any one of the plurality of parts is characterized by a design system of another part. Then, the design system of the other part receives the capacitance information of the input pin of any one of the parts and performs the delay simulation.

In a simulation method when performing a chip design in which a plurality of parts designed by at least two or more different design systems are incorporated into any one of the parts, a logic gate of the incorporated part to be driven is output pin of the incorporated part. Is placed in the vicinity of the input pin, and the slope of the waveform of the input signal of the input pin of the built-in portion is set as a standard slope, and the capacitance of the input pin is set so that the slope of the waveform of the input signal of the input pin becomes the standard slope. In consideration of the above, the size of the output transistor of the gate driving the input pin is determined and the delay simulation is performed. In a simulation method for designing a plurality of parts designed by at least two or more different design systems as one system,
The slope of the waveform of the input signal of the input pin of any one of the plurality of parts is a standard slope, and the slope of the waveform of the input signal of the input pin is the standard slope,
In consideration of the capacitance of the input pin, the size of the output transistor of the gate driving the input pin is determined and the delay simulation is performed.

[0007]

As described above, according to the simulation method, the part A (group) designed by the design system having a certain delay formula is changed to the part B (group) designed by the design system having another delay formula. When incorporating (see FIG. 7), it becomes possible to incorporate without recharacterizing the entire part A. Moreover, it becomes possible to simulate a plurality of LSIs designed by design systems having different delay expressions as one system. As a result, the delay parameter can be easily extracted (characterized). And, this significantly reduces the design period.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below in detail with reference to the drawings. FIG. 1 is an explanatory diagram showing a first embodiment of the present invention. FIG. 2 is a block diagram showing the first embodiment of the present invention. FIG. 3 is a flowchart showing the first embodiment of the present invention. In this embodiment, the gate array unit 17 is designed by the gate array LSI design system 7 and the macro module unit 18 is designed by the standard cell LSI design system 6 embedded array type SOG LSI (hereinafter, E type LSI). 19) as an example. The macro module unit 18 is directly connected to the input pin 11 as an input external interface terminal, the input gate 12 directly connected to the input pin 11, the output pin 15 as an output external interface terminal, and the output pin 15. Output gate 14 and output gate 1
4 is composed of a gate 13 as a preceding stage gate and another logic gate group not shown. Further, the gate 10 is connected to the input pin 11 of the macro module unit 18, and the plurality of gates 16 are connected to the output pin 15. The output gate 14 is for a gate array.
The transistor size characterized by the delay formula in the delay calculation program 3 of the LSI design system 7 is used.

Standard cell LSI design system 6 used to design the macro module section 18 and gate array LSI design system 7 used to design the gate array section 17.
Is a delay calculation program 41, 3 in which a delay formula (table) is prepared in advance by, for example, creating a library of delay parameters (load capacitance dependence coefficient, etc.) for each gate,
The logic simulators 42 and 4 that actually execute the delay simulation are provided. Further, the netlist 43 contains connection information for each gate of the macro module unit 18, the delay file 1 has delay time for each logic gate of the macro module unit 18, and the capacitance file 5 has connection information of the macro module unit 18. The capacitance of each input pin is stored. On the contrary, the connection information in the gate array unit 17 is stored in the netlist 44, and the delay time for each logic gate in the gate array unit 17 and the delay time in the output gate 14 in the macro module unit 18 are stored in the delay file 2. ing.

Next, a delay simulation processing method will be described. In the present embodiment, the description of the delay time calculation formula (delay formula) itself is omitted, but the elements (data) necessary for the delay time calculation are the intrinsic delay time of each gate,
The load capacitance of each gate, the load capacitance dependence coefficient, the slope of the input signal of each gate, and the input waveform dependence coefficient are mentioned. First,
Using the delay formula of the delay calculation program 41 in the standard cell LSI design system 6, the macro module unit 1
Delay calculation is performed for each logic gate (input gate 12, gate 13, output gate 14, etc.) in 8 to obtain the delay time (step 101). And these are delay files 1
It is written in and stored (step 102).

At this time, the load capacitance of the output gate 14 is the wiring capacitance from the output gate 14 to the output pin 15.
Further, when calculating the delay time of the input gate 12, the slope of the input waveform of the signal to the input gate 12 should be taken into consideration, but in the present embodiment, the number of input pins 11 of the input gate 12 is two. By limiting to the following, even if the inclination of the waveform of the input signal becomes gentle (even if it is inclined), it can be ignored. This is a result of measuring how much the input waveform to the input gate 12 affects the gate delay with a circuit simulator, and the gate with 2 inputs or less has more inputs than the multi-input gate (3 input NAND or 4 input NAND). This is because it was determined that the influence of the input waveform was small because the fluctuation of the waveform-dependent portion was 1/10.

Next, the gate array LSI design system 7
Using the delay formula of the delay calculation program 3 therein, the delay calculation is performed for each logic gate in the gate array unit 17 and the output gate 14 of the macro module unit 18 to obtain the delay time (step 103). Then, these are written to the delay file 2 and stored (step 104). Specifically, as the delay calculation program 3 of the gate array design system 7, for the gate 10 connected to the input pin 11 of the macro module unit 18 in the gate array unit 17, the input pin stored in the capacitance file 5 is used. The load capacitance of each 11 (the sum of the wiring capacitance from the input pin 11 to the input gate 12 and the gate capacitance of the input gate 12) can be received from the standard cell LSI design system 6,
Also, as described above, the output gate 14 is limited to the transistor size that has been characterized by the gate array LSI design system 7, so that the delay parameter of the transistor size can be used.
Output pin 15 load capacitance (from output pin 15 to each gate 1
Since the sum of the wiring capacitance up to 6 and the gate capacitance of the gate 16) can also be calculated in the gate array design system 7, the load capacitance dependent delay time of each gate can be calculated using those data.

Further, the delay time depending on the slope of the waveform of the input signal of the output gate 14 can be ignored.
It is a design constraint of the macro module unit 18 in advance that the inclination of the waveform of the output signal of the gate 13, which is the preceding gate of the output gate 14, should not be less than the standard inclination. On the other hand, the gate 16 connected to the output pin 15
With respect to the above, there is no problem because the delay calculation program 3 calculates the slope of the waveform of the output signal of the output gate 14 (the input signal for the gate 16).

The delay time of each logic gate thus obtained is read from the delay files 1 and 2 (step 10).
5) The read result is written on the simulation model (step 106). By the way, both the delay files 1 and 2 are SDF (Standard
Since the delay file) format is used, the delay file 1 can be read by the logic simulator 4 of the gate array design system 7. Regarding the output gate 14, among the total delay times, the load capacitance dependent delay time due to the wiring capacitance from the output gate 14 to the output pin 15 and the inherent delay time of the output gate 14 are from the delay file 1, and The wiring capacitance from the output pin 15 to the gate 16 and the load capacitance dependent delay time due to the gate capacitance of the gate 16 are written from the delay file 2 on the simulation model.

Then, delay simulation is performed using the simulation model in which the delay time of each logic gate is written (step 107).

As described above, according to the first embodiment of the present invention, the macro module section 18 designed using the standard cell LSI design system 6 of different delay type is used in the gate array LSI design system 7. LSI 19 to design
It is now possible to capture an entire module without re-characterizing it. Further, since it is not necessary to transfer the waveform of each signal at the boundary of the macro module unit 18 between the two systems, the interface is simplified, and the macro module unit 18 can be closed.
In other words, stand-alone delay calculation is possible.

Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 4 is an explanatory view showing the second embodiment of the present invention. FIG. 5 is a block diagram showing a second embodiment of the present invention. FIG. 6 is a flow chart showing the second embodiment of the present invention. In this embodiment, the gate array unit 24 is designed by the gate array LSI design system 7, and the macro module unit 25 is designed by the standard cell LSI design system 6 by an embedded array type SOG LSI (hereinafter, E type). 29 will be described as an example. In addition, a part of the description overlapping with the first embodiment will be omitted.

The macro module section 25 is directly connected to the input pin 11 as an input external interface terminal, the input gate 21 directly connected to the input pin 11, the output pin 15 as an external interface terminal, and the output pin. And an output gate 22 and another logic gate group (not shown). Furthermore, the input interface gate 20 is connected to the input pin 11 of the macro module section 25, and the output interface gate 23 is connected to the output pin 15. In the present embodiment, these input / output interface gates 20 and 23 are considered to be the boundary gates of the gate array section 24 and the macro module section 25, and physically, the input pin 11 and the input interface gate 20, and the output pin 15 and the output interface gate. 23 are arranged close to each other (100 μ or less).

Standard cell LSI design system 6 used to design the macro module section 25 and gate array LSI design system 7 used to design the gate array section 24.
Is a delay calculation program 41, 3 in which a delay formula (table) is prepared in advance by, for example, creating a library of delay parameters (load capacitance dependence coefficient, etc.) for each gate,
The logic simulators 42 and 4 that actually execute the delay simulation are provided. Further, the netlist 51 includes connection information for each gate of the macro module unit 25, the delay file 30 includes the delay time of each logic gate of the macro module unit 25, and the capacity file 5 includes the macro module unit 25. The load capacitance for each input pin is stored. On the contrary, in the netlist 52, the connection information in the gate array unit 24 is
The delay time is stored for each logic gate of the gate array section 24.

Next, the processing method of the delay simulation will be described. First, the delay formula of the delay calculation program 41 in the standard cell LSI design system 6 is used to calculate the delay of each logic gate (the input gate 21, the output gate 22, etc.) in the macro module unit 25 to obtain the delay time. (Step 201). Then, these are written to the delay file 30 and stored (step 20).
2). At this time, the load capacitance of the output gate 22 is the sum of the wiring capacitance from the output gate 22 to the output pin 15 and the standard load capacitance. The standard load capacitance here is the sum of the gate capacitance of the output interface gate 23 and the wiring capacitance from the output pin 15 to the output interface gate 23. Regarding the gate capacitance of the output interface gate 23 here, the output interface gate 23 is previously stored in the gate array section 25.
There is only one type of gate used for the above, and a design constraint is set so that the number of gates 23 connected to the output pin 15 is one. The wiring capacitance from the output pin 15 to the output interface gate 23 is set to the worst value (100 μ or less) expected from the processing capability of the placement and routing program in the gate array LSI design system 7.

Then, the delay calculation of the input gate 21 is performed assuming that the slope of the waveform of the input signal of the input gate 21 is the standard slope used in the delay formula of the standard cell LSI design system 6. Further, the output of the input interface gate 20 is considered in consideration of the capacitance of each input pin 11 of the macro module unit 25 stored in the capacitance file 5 so that the slope of the waveform of the input signal of the input gate 21 becomes a standard slope. The gate array unit 25 is provided with a design constraint of determining the transistor size.

Next, the gate array LSI design system 7
Using the delay formula of the delay calculation program 3 therein, the delay calculation is performed for each logic gate in the gate array section 24 to obtain the delay time (step 203). Then, this is written to the delay file 31 and stored (step 204). Specifically, as the delay calculation program 3 of the gate array design system 7, the input interface gate 10 in the gate array unit 24, which is connected to the input pin 11 of the macro module unit 25, is stored in the capacitance file 5. The capacitance for each input pin 11 (the sum of the wiring capacitance from the input pin 11 to the input gate 21 and the gate capacitance of the input gate 21) can be received from the standard cell LSI design system 6. It is possible to calculate the load capacity dependent delay time of.

As for the output interface gate 23 of the gate array section 24, the macro module section 2
Even if the waveform of the input signal from the output pin 15 of No. 5 is blunted (tilted) to some extent, the gate array unit 24 is provided with a design constraint that the number of the input pins 11 of the gate 23 is set to 1 so that the influence can be ignored. Therefore, the delay time of the gate can be calculated.

The delay time of each logic gate thus obtained is read from the delay files 30 and 31 (step 205), and the read result is written on the simulation model (step 206). Then, delay simulation is performed using the delay time of each logic gate (step 207).

As described above, according to the second embodiment of the present invention, the macro module section 25 designed using the standard cell LSI design system 6 of different delay type is used in the gate array LSI design system 7. LSI 29 to be designed
It is now possible to capture an entire module without re-characterizing it. In addition, since it is not necessary to transfer the waveform of each signal at the boundary of the macro module unit 25 between the two systems, the interface is simplified, and the macro module unit 25 is closed.
In other words, stand-alone delay calculation is possible. In addition, it is not necessary to provide a new design constraint for incorporating the macro module unit 25 into the gate array unit 24 when designing the macro module unit 25.

FIG. 7 is a conceptual diagram (1) of the present invention. In the first and second embodiments, the macro module units 18, 25
Is designed by the standard cell LSI design system 6,
The gate array units 17 and 24 have been described by taking the case of being designed by the gate array LSI design system 7 as an example, but in the design simulation method of the present invention, the macro module is designed by the standard cell system and the chip is the gate array. That is not to be construed as limited. That is, when a part (group) designed by a design system having a certain delay formula and a part (group) designed by another design system having another delay formula are combined as shown in FIG. It is a common technique for delayed simulation without re-characterizing the entire part.

FIG. 8 is a conceptual diagram (2) of the present invention. Further, in the first and second embodiments, an example in which a module designed by another design system is incorporated into one LSI has been described, but the simulation method of the present invention is not limited to this. It can also be applied to a case where a plurality of LSIs designed by a design system having different delay formulas as shown in (1) are subjected to delay simulation as one system.

[0028]

As described in detail above, according to the simulation method of the present invention, the part A (group) designed by the design system having a certain delay formula is designed by the design system having another delay formula. When a part B (group) is installed (see FIG. 7), the whole part A can be installed without re-characterizing, and a plurality of LSIs designed by a design system with different delay formulas can be integrated into one. Since the system can be simulated, the delay parameter can be easily extracted (characterized). And this can significantly reduce the design period.

[Brief description of drawings]

FIG. 1 is an explanatory diagram showing a first embodiment of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a flowchart showing a first embodiment of the present invention.

FIG. 4 is an explanatory diagram showing a second embodiment of the present invention.

FIG. 5 is a block diagram showing a second embodiment of the present invention.

FIG. 6 is a flowchart showing a second embodiment of the present invention.

FIG. 7 is a conceptual diagram (1) of the present invention.

FIG. 8 is a conceptual diagram (2) of the present invention.

[Explanation of symbols]

1, 2, 30, 31 Delay file 3, 41 Delay calculation program 4, 42 Logic simulator 5 Capacity file 6 Standard cell LSI design system 7 Gate array LSI design system 17, 24 Gate array section 18, 25 Macro module section

Claims (12)

[Claims] 1. A simulation method for designing a chip in which a plurality of portions designed by at least two or more different design systems are incorporated into any one of the portions, wherein an output gate of the incorporated portion is incorporated into a design system of the incorporated portion. The simulation method, characterized in that the design system of the part to be incorporated receives the capacitance information of the input pin of the part to be incorporated and performs delay simulation. 2. The simulation method according to claim 1, wherein the number of the input pins of the input gate of the incorporated portion is 2 or less. 3. The simulation method according to claim 1, wherein the slope of the input signal to the output gate of the incorporated portion is constant. 4. A simulation method for designing a plurality of parts designed by at least two or more different design systems as one system, wherein an output gate of any one of the plurality of parts is used as another part. Of the design system, and the design system of the other part receives the capacitance information of the input pin of any one of the parts and performs the delay simulation. 5. The simulation method according to claim 4, wherein the number of the input pins of the input gate of any one of the portions is 2 or less. 6. The simulation method according to claim 4, wherein the slope of the input signal to the output gate in any one of the portions is constant. 7. A simulation method for performing a chip design for incorporating a plurality of portions designed by at least two or more different design systems into any one of the portions, wherein a logic gate of the incorporated portion is driven. The input pin is arranged in the vicinity of the output pin, and the inclination of the waveform of the input signal of the input pin of the built-in portion is set as a standard inclination, and the inclination of the waveform of the input signal of the input pin becomes the standard inclination. The simulation method is characterized in that the delay simulation is performed by determining the output transistor size of the gate that drives the input pin in consideration of the capacitance of. 8. The simulation method according to claim 7, wherein the input gate capacitance of the logic gate in the incorporated portion is made constant. 9. The simulation method according to claim 7, wherein the number of input pins of the logic gate in the incorporated portion is 1 or less. 10. A simulation method for designing a plurality of parts designed by at least two or more different design systems as one system, the input signal of an input pin of any one of the plurality of parts. Taking the capacitance of the input pin into consideration, the output transistor size of the gate that drives the input pin is set so that the slope of the waveform is a standard slope and the slope of the waveform of the input signal of the input pin is the standard slope. A simulation method characterized by determining and performing a delay simulation. 11. The simulation method according to claim 10, wherein the input gate capacitance of the logic gate in the incorporated portion is constant. 12. The simulation method according to claim 10, wherein the number of input pins of the logic gate in the incorporated portion is 1 or less.