JPH0864829A - Semiconductor device and liquid crystal display device using the same - Google Patents

Abstract

(57) [Summary] [Structure] Gate electrode 2 and gate insulating layer 4 on insulating substrate 1.
And a semiconductor pattern comprising a semiconductor layer 5 and a source / drain electrode 8 formed so as to intersect the gate electrode 2 in the semiconductor pattern region, wherein the gate has a forward tapered end. Electrode 2
And the semiconductor pattern whose end is forward tapered is formed thereon, and the forward taper angle θ of the gate electrode is formed.
A semiconductor device configured such that g is 3 times or less of the forward taper angle θs of the end portion of the semiconductor pattern (provided that it is less than 90 °). [Effect] The gate insulating layer 4 at the portion overcoming the gate electrode 2
The generation of cracks can be suppressed, the short circuit between the gate electrode 2 and the drain electrode 8 can be reduced, and the manufacturing yield of the TFT-liquid crystal display device can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device including a thin film transistor and an active matrix type liquid crystal display device using the same.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a switching element provided corresponding to each of a plurality of pixel electrodes arranged in a matrix on a display panel, and simply adopts a time division method. The contrast is better than that of the simple matrix system used, and it is a technology that is especially essential for color display.

As one of the problems to be solved in realizing an active matrix type liquid crystal display device, a substrate in which a thin film transistor (TFT), a scanning signal line, a video signal line and a pixel electrode are formed on a transparent substrate such as glass. There is a reduction in manufacturing cost. In this regard, Japanese Patent Laid-Open No. 62-3265
No. 1 discloses that the semiconductor layer of the TFT and the gate insulating layer are simultaneously formed in the same pattern to reduce the number of photolithography steps.

[0004]

However, in the above method, the etching speed is higher in the portion where the semiconductor pattern of the TFT passes over the gate electrode than in the case where the end portion of the semiconductor pattern is flat. There is a problem that cracks occur, the leakage current between the semiconductor layer and the gate electrode becomes large, and a short circuit (G / D short) easily occurs between the source / drain electrode and the gate electrode formed on the semiconductor layer. It was

An object of the present invention is to provide a semiconductor device having an electrode structure and a liquid crystal display device using the same, which solves the above problems.

[0006]

The gist of the present invention for achieving the above-mentioned object is as a gist.

(1) A semiconductor device having a gate electrode, a semiconductor pattern made of an insulating layer and a semiconductor layer on an insulating substrate, and source and drain electrodes formed so as to intersect the gate electrode in the semiconductor pattern region. The gate electrode having an electrode end portion forward-tapered and the semiconductor pattern having an end portion forward-tapered are formed thereon, and the forward taper angle θg of the gate electrode is equal to the semiconductor pattern end portion. Of the forward taper angle θs of 3 times or less (however, it is less than 90 °).

(2) The gate electrode is Ta, ITO, M
_{oSi 2, TaSi 2, CrSi 2} , WSi 2, TiN, T
It is made of a material selected from aN, and the forward taper angle θg of the gate electrode is not more than twice the forward taper angle θs of the end portion of the semiconductor pattern (however, it is less than 90 °). Existing semiconductor device.

(3) The gate electrode is made of Cr, Mo,
The gate electrode is made of a material selected from W, Al, Cu, Au, and Ni, and the forward taper angle θg of the gate electrode is 3 times or less than the forward taper angle θs of the end portion of the semiconductor pattern (however, 90 °).
The semiconductor device is configured so that it is less than).

(4) Forward taper angle θg of the gate electrode
Is 0.5 to 0.5 of the forward taper angle θs at the end of the semiconductor pattern.
It is in a semiconductor device that is three times (but less than 90 °).

(5) The semiconductor device has a forward taper angle θg of the gate electrode of 10 ° to 40 °.

(6) The gate electrode having an electrode end portion forward-tapered and the semiconductor pattern having an end portion forward-tapered are formed on the gate electrode, and the gate electrode is formed from a lower end portion to an upper end portion. Film thickness (B) against retreat distance (A)
The ratio (taper ratio: B / A) is less than or equal to 3 times the taper ratio (B ′ / A ′) at the end of the semiconductor pattern.

(7) The taper ratio (B /
A) is a semiconductor device having a value of 0.2 to 0.8.

(8) The gate electrode is arranged near each intersection of a plurality of scanning signal lines formed on one of the pair of substrates and the video signal line, and the gate electrode is composed of the scanning signal line and the drain electrode. In a liquid crystal display device including a video signal line and a thin film transistor in which a source electrode is connected to a pixel electrode, the electrode end is forward-tapered, and the end is forward-tapered. A semiconductor pattern is formed, and the forward taper angle θ of the gate electrode is
g is configured to be 3 times or less of the forward taper angle θs of the end portion of the semiconductor pattern (provided that it is less than 90 °), and held between the other transparent substrate and a liquid crystal alignment film. And a liquid crystal display device having a liquid crystal layer.

(9) The gate electrode having an electrode end portion forward-tapered and a semiconductor pattern having an end portion forward-tapered are formed on the gate electrode, and the upper end portion of the gate electrode recedes from the lower end portion. The ratio of the film thickness (B) to the distance (A) (taper ratio: B / A) is configured to be 3 times or less than the taper ratio (B ′ / A ′) of the end portion of the semiconductor pattern, and the other A liquid crystal display device having a liquid crystal layer sandwiched between a transparent substrate and a liquid crystal alignment film.

By the above, the length of the crack generated at the end of the forward tapered semiconductor pattern can be reduced to 1/2 or less of the slope length of the insulating layer. As a result, the G /
D short circuit can be suppressed.

The semiconductor pattern is disposed near each intersection of the scanning signal line and the video signal line of the liquid crystal display element, the gate electrode is the scanning signal line, the drain electrode is the video signal line, and the source electrode is the pixel electrode. Further, it is possible to provide a matrix type liquid crystal display device in which TFTs connected to the same layer are used as active elements.

The present invention is effective for the inverted stagger structure TFT in which the gate electrode is formed under the semiconductor pattern.
It is also effective for a positive stagger TFT (top gate structure) in which the source and drain electrodes are formed under the semiconductor pattern.

The semiconductor pattern of the present invention may be an insulating layer or a semiconductor layer only, and is formed so that the semiconductor pattern and the wiring intersect. Further, it can be similarly formed on a wiring board of an ordinary electronic device.

[0020]

In a TFT having a structure in which a source / drain electrode crosses over a gate electrode on a semiconductor pattern having a semiconductor layer and a gate insulating layer, the forward taper angle of the electrode end is equal to the forward taper angle of the end of the semiconductor pattern. It is controlled to not more than twice, preferably 0.5 to 3 times. This makes it possible to reduce the cracks that occur at the end of the electrode,
Since a short circuit can be prevented, a highly reliable semiconductor device can be obtained.

When a semiconductor pattern is formed by an isotropic dry etching method, usually, at the end of the semiconductor pattern,
Those having a certain forward taper angle are formed. However, in the portion that goes over the gate electrode, etching progresses faster than in the flat portion, and cracks occur at the forward tapered end portion.

When the forward taper angle of the end of the gate electrode is controlled to be 3 times or less than the forward taper angle of the end of the semiconductor pattern, the step coverage of the insulating layer and the semiconductor layer thereabove is improved, and the end of the semiconductor pattern is improved. It is possible to suppress the length of the cracks generated on the inclined surface of the portion to be short, and to suppress leakage current from the semiconductor layer due to poor insulation of the insulating layer, short circuit between the gate electrode and the source and drain electrodes, and the like.

The forward taper angle at the end of the semiconductor pattern is 30.
If it is larger than 0, it is not necessary to make the forward taper angle at the end of the gate electrode so small. The forward taper angle is 20
In the case of about 0 °, the insulating film in the taper portion becomes thicker, cracks due to etching are hard to occur, and the forward taper angle of the gate electrode may be set to 60 ° or less.

When the forward taper angle is as small as 10 ° or less, the forward taper angle at the end of the gate electrode is 3 or less.
Double, that is, 30 ° or less can shorten the length of cracks generated on the tapered slope of the insulating layer of the semiconductor pattern, and suppress G / D short circuit.

Note that the smaller the forward taper angle of the gate electrode, the shorter the length of cracks formed on the forward taper slope of the insulating layer of the semiconductor pattern, and the greater the leak current reduction effect and the short circuit prevention effect. However, when the forward taper angle is unnecessarily small, the cross-sectional area of the electrode decreases and the resistance of the scanning signal line increases. Therefore, about 3 times the forward taper angle at the end of the semiconductor pattern is preferable.

It is not necessary to completely prevent cracks due to etching during pattern processing on the forward taper slope of the insulating layer of the semiconductor pattern. If the length of the taper slope is ½ or less, the leak current and drain ， The probability of a short circuit between gates is small, and it shows electrically stable transistor characteristics. Further, if the crack has a length of ⅓ or less, the stability can be further improved.

[0027]

Embodiments of the present invention will be described with reference to the drawings.

Example 1 FIG. 1 shows a perspective view of a thin film transistor (TFT) formed on a glass substrate. Board 1
A chromium film having a film thickness of 100 nm is formed thereon by a sputtering method. This is processed into the scanning signal line and the gate electrode 2 by photoetching. Next, the end portion of the gate electrode is forward-tapered with a forward taper angle θg by using a wet etching method.

As the gate insulating layer 4, the semiconductor layer 5 and the contact layer 6, a silicon nitride film, a non-doped amorphous silicon film and a phosphine-doped amorphous silicon film are successively formed by a plasma chemical vapor deposition (plasma CVD) method. Next, these laminated films are patterned. As for the processing, in order to reduce the number of masks and the number of processing steps, the same mask is collectively processed by a dry etching method. Since the etching characteristic of the dry etching method is isotropic, side etching proceeds on the surface to form a forward taper state with an angle θs as shown in FIG.

As the video signal line, the pixel electrode, the source and the drain electrode, indium tin oxide (ITO) is formed to a film thickness of about 300 nm by a sputtering method, and a pattern is processed by a wet etching method using a photoresist. The contact layer 6 is dry-etched using the same photoresist to form a channel region. Finally, a silicon nitride film is formed as a passivation layer by the plasma CVD method.

FIG. 2 shows the forward taper angle θs of the gate insulating layer 4.
Is constant at about 10 ° (taper ratio = 0.18), the forward taper angle θg of the edge of the chromium film which is the gate electrode 2 is θg.
FIG. 6 is a plan view showing a situation of a portion where a gate electrode 2 of a semiconductor pattern has crossed over when the above is changed.

The forward taper angle θg of the gate electrode 2 is 6 ° to 1
When the angle is 0 ° (taper ratio is 0.1 to 0.18), no crack is observed in the silicon nitride film at the overcoming portion. From this, cracks do not occur when θg is a low angle of 10 ° or less.

The above-mentioned θg is about 3 times θs and is between 23 ° and 2 °.
In the case of 5 ° (taper ratio of 0.47 to 0.7), a crack (C) corresponding to about 1/4 of the length of the forward taper slope is generated, but such a crack of the gate insulating layer 4 is generated. Even if it exists on the forward taper slope, it has no influence on the electrical characteristics of the TFT.

However, the above θg is 70 times four times or more of θs.
When the angle becomes 80 to 80 (taper ratio is 2.7 to 5.6), a crack (C) larger than about 1/2 of the length of the forward taper slope is generated. A perspective view of the TFT in such a case is shown in FIG. If the leak current between the gate electrode 2 and the semiconductor layer 5 becomes large and the crack (C) is large, short circuit between the gate electrode 2 and the drain electrode 8 will occur frequently.

Note that θs can be formed at about 10 ° to 30 ° by the dry etching method using SF ₆ gas.

Further, θg can be controlled by changing the composition of the etchant of the chromium film which is the gate electrode 2. This etchant is composed of a mixed solution of nitric acid, ceric ammonium nitrate, perchloric acid and water. Of these, the concentration of ceric ammonium nitrate determines mainly the etching rate in the vertical direction. Also, nitric acid penetrates into the close contact interface between the chromium film and the resist, and the nitric acid second
Lateral etching progresses when cerium ammonium enters. The ratio of the vertical and horizontal etching rates is a major factor in determining the forward taper angle θg of the edge portion of the chromium film as the gate electrode 2.

FIG. 4 shows the forward taper angle θ of the gate insulating layer 4.
When s is 10 °, the forward taper angle θg of the gate electrode 2 is
The ratio of nitric acid and cerium (II) nitrate nitrate for forming the TiO2 to 3 times or less is shown.

When the amount of ceric ammonium cerium nitrate is 20% and the nitric acid concentration is 9 mol / l, θg is 6 ° to 10 °, and at 8 mol / l, the forward taper processing cannot be performed.

On the other hand, in the case where the amount of ceric ammonium nitrate is 15%, the etching rate in the vertical direction is smaller than that in the case of 20%, so that the infiltration rate in the horizontal direction is relatively high. θg becomes smaller. That is, nitric acid concentration 9
2 ° to 3 ° at mol / l, 7 at 8 mol / l
° is obtained.

In addition to the etchant composition, the difference in θg is due to the adhesion between the chromium film and the etching resist. Roughness (RMS) of the chromium film surface is one of the factors that determine the adhesion.

FIG. 4 shows the relationship between the surface roughness (RMS) of the chromium film and θg. For a film having a small RMS of 1.07 (small surface irregularities), θg is 10 ° (however, nitric acid concentration: 9 mol / l). On the other hand, an etchant having the same composition has an RMS of 1.20 (larger surface irregularities), and a film having an RMS of 1.43 (larger surface irregularities) has a surface angle of 20 °. Therefore, the surface roughness (RMS) of the film is also an important factor for the forward taper etching of the gate electrode 2.

The shape of the pattern end portion subjected to the forward taper processing is approximated to that in which the forward taper slope can be approximated by a straight line as shown in FIG. 5A, as shown in FIG. 5B or FIG. Some are difficult. Although (a) can be easily defined by the taper angle, it cannot be simply defined by the taper angle in the case of (b) or (c). In such a case, the width of the taper portion, that is, the receding distance of the upper end portion from the lower end portion (base: A)
And the film thickness (B), and the taper ratio (B / A) define the forward taper. Therefore, the taper ratio (B
/ A) are both 0.62.

FIG. 6 is a graph showing the relationship between the forward taper angle θg of the gate electrode 2 and the G / D breakdown voltage. The depths of cracks (C) in the gate insulating layer 4 at the time when the gate electrode 2 was crossed over were shown at each measurement point.

When the forward taper angle θs of the SiN film which is the gate insulating layer 4 is 10 °, the G / D breakdown voltage is as high as 400 V when θg is 10 °. The cut depth of the crack (C) was zero. However, when θg is 30 °, the length is about 1
A crack (C) of μm occurs, but the G / D withstand voltage has almost no effect. However, when θg exceeds 30 °, G / D
The withstand voltage also drastically decreases accordingly. This is because the cut length of the crack (C) in the gate insulating layer became longer than half the length of the forward tapered slope.

Further, as the effect other than the above by processing the end portion of the gate electrode 2 into a forward taper, as shown in FIG. 7, a material such as a poly-ITO film having a poor step coverage is used for the drain electrode 8. When using, the crack due to etching may enter the drain electrode 8 and the electrode 8 may be disconnected (hereinafter referred to as D disconnection). This disconnection of D can be suppressed by setting the taper angle of the gate electrode 2 to 10 ° to 40 ° (or the taper ratio of 0.2 to 0.8).

As a chromium film etchant for the gate electrode 2,
4 to 7 nitric acid to 1 part by weight of ammonium cerium nitrate.
It is possible to use θg of 30 ° or less by using a mixture of parts by weight. In particular, in the case of 5 parts by weight of nitric acid, θ
g of about 10 ° is obtained. However, if it is less than 4 parts by weight of nitric acid, it is difficult to form a predetermined taper angle, and it becomes too large with respect to θs, and the gate insulating layer 4 is cracked. On the other hand, if it exceeds 7 parts by weight, θg becomes too small depending on the close contact state between the chromium film and the photoresist, and the pattern processing accuracy of the gate electrode 2 deteriorates.

Example 2 As a material of the gate electrode 2,
Conductive materials with high specific resistance (Ta, ITO, MoSi ₂ ,
When TaSi ₂ , CrSi ₂ , WSi ₂ , TiN, TaN) is used, in order to reduce the gate delay, it is necessary to increase the film thickness to reduce the resistance value. However, if the film thickness is increased, the step difference at the end portion of the gate electrode 2 becomes large, and cracks are likely to occur at the portion where the gate insulating layer 4 gets over the gate electrode 2.

To obtain a resistance value similar to that when a 100 nm thick chromium film is used for the gate electrode 2, for example, T
105 nm for a, 1160 nm for poly ITO, Cr
Si ₂ , MoSi ₂ , TaSi ₂ , WSi ₂ or TiSi
_For silicide such as ₂ , 190-775 nm, TiN, T
In the case of aN, it is necessary to form the film with a film thickness of about 500 nm.

The large step difference of the gate electrode 2 made of the above-mentioned material causes cracks by making the θg (or taper ratio) of the gate electrode 2 less than twice the θs (or taper ratio) of the gate insulating layer 4. Suppresses the occurrence of (C),
The G / D short circuit could be suppressed.

On the other hand, as a material for the gate electrode 2, a low resistance material such as Al, Cu, Au, Ni, Mo or W is used.
When using, the electrode film thickness is reduced. 20n for Al
m, Cu 13 nm, Ni 53 nm, Mo 44 n
With m and W, it can be 43 nm. In this case, by setting θg (or taper ratio) of the gate electrode 2 to 3 times or less with respect to θs (or taper ratio) of the gate insulating layer 4, crack generation can be suppressed and G / D short circuit can be suppressed. did it.

[Embodiment 3] When SiO ₂ having a low dielectric constant or a two-layer film of SiO ₂ and SiN is used as the gate insulating layer 4, in order to obtain the same capacity as that of an insulating layer composed of a single SiN layer. , It is necessary to conversely set the film thickness to an amount corresponding to the dielectric constant.

SiN film having a dielectric constant of 2.0, film thickness 350 n
To achieve the same capacitance as that of m, the SiO ₂ 200n
It is necessary to set it to about m. In this case, the gate electrode 2
A crack (C) is likely to occur in the SiO ₂ gate insulating layer 4 at a portion that goes over the range, and the occurrence rate of electrical defects increases.

The θs of the gate insulating layer 4 is 10 ° (or the taper ratio: 0.17), and the θg of the gate electrode 2 is 10 °.
By setting the angle (or taper ratio: 0.17) substantially the same, it was possible to suppress the occurrence of cracks and the occurrence of G / D shorts.

[Embodiment 4] FIG. 8 is a schematic sectional view of a liquid crystal display device using the TFT of the present invention. A liquid crystal substrate 10 formed with the TFT of the present invention as shown in the above embodiment and a counter substrate 9 thereof are produced, an alignment film 11 is provided on the facing surfaces of the both substrates 10 and 9, and a liquid crystal 12 is sealed between them. As a result, a TFT drive type liquid crystal display device was obtained. The liquid crystal display device has a highly reliable liquid crystal display device capable of preventing a G / D short circuit, a leak current, and an ITO drain disconnection at the portion where the semiconductor pattern and the drain electrode 8 pass over the gate electrode 2. TFT-LC
D) can be manufactured with high yield.

[0055]

According to the present invention, the generation of cracks in the gate insulating layer in the TFT semiconductor pattern can be suppressed, so that a G / D short circuit between the gate electrode and the drain electrode, a leak current, an ITO drain disconnection, etc. can be significantly reduced. It is possible to reduce the manufacturing yield of the TFT-LCD.

[Brief description of drawings]

FIG. 1 is a schematic perspective view of a thin film transistor of the present invention.

FIG. 2 is a plan view of a thin film transistor of the present invention.

FIG. 3 is a schematic perspective view of a conventional thin film transistor section.

FIG. 4 Nitric acid concentration and second nitric acid in etchant
FIG. 6 is a graph showing the relationship between the cerium ammonium concentration and the forward taper angle θg of the gate electrode.

FIG. 5 is a schematic cross-sectional view of a forward taper shape of an end portion of a wiring pattern.

FIG. 6 is a graph showing the relationship between the forward taper angle θg of the gate electrode and the gate / drain breakdown voltage.

FIG. 7 is a plan view of a gate electrode overriding portion.

FIG. 8 is a schematic cross-sectional view of a liquid crystal display device of the present invention.

[Explanation of symbols]

1 ... Substrate, 2 ... Gate electrode, θg ... Forward taper angle of gate electrode, 4 ... Gate insulating layer, θs ... Forward taper angle of gate insulating layer, 5 ... Semiconductor layer, 6 ... Contact layer, 8 ... Drain electrode, 9 ... counter substrate, 10 ... liquid crystal substrate, 11 ... alignment film,
12 ... Liquid crystal.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuro Minemura 7-1, 1-1 Omika-cho, Hitachi-shi, Ibaraki Hitachi Ltd. Hitachi Research Laboratory

Claims (9)

[Claims] 1. A semiconductor device comprising a gate electrode, a semiconductor pattern formed of an insulating layer and a semiconductor layer on an insulating substrate, and source and drain electrodes formed so as to intersect the gate electrode in the semiconductor pattern region, The gate electrode having an electrode end portion forward-tapered and the semiconductor pattern having an end portion forward-tapered are formed thereon, and the forward taper angle θg of the gate electrode is equal to that of the semiconductor pattern end portion. 3 times or less of the forward taper angle θs (however, 9
The semiconductor device is characterized in that it is less than 0 °. 2. A semiconductor device comprising a gate electrode, a semiconductor pattern including an insulating layer and a semiconductor layer on an insulating substrate, and source and drain electrodes formed so as to intersect with the gate electrode in the semiconductor pattern region, The gate electrode having an electrode end portion forward-tapered and the semiconductor pattern having an end portion forward-tapered are formed on the gate electrode, and the gate electrode is made of Ta, ITO, MoSi ₂ ,
The gate electrode is made of a material selected from TaSi ₂ , CrSi ₂ , WSi ₂ , TiN, and TaN, and the forward taper angle θg of the gate electrode is 3 of the forward taper angle θs of the end portion of the semiconductor pattern.
A semiconductor device, which is configured to be equal to or less than twice (but less than 90 °). 3. A semiconductor device comprising a gate electrode, a semiconductor pattern made of an insulating layer and a semiconductor layer on an insulating substrate, and source and drain electrodes formed so as to intersect with the gate electrode in the semiconductor pattern region, The gate electrode having an electrode end portion forward-tapered and the semiconductor pattern having an end portion forward-tapered are formed thereon, and the gate electrode is made of Cr, Mo, W, Al, C.
The gate electrode is made of a material selected from u, Au, and Ni, and the forward taper angle θg of the gate electrode is 3 times or less (but less than 90 °) the forward taper angle θs of the end portion of the semiconductor pattern. A semiconductor device having the above structure. 4. The forward taper angle θg of the gate electrode is 0.5 to 3 times the forward taper angle θs of the end portion of the semiconductor pattern (provided that it is less than 90 °). The semiconductor device according to. 5. The forward taper angle θg of the gate electrode is 10
The semiconductor device according to claim 1, wherein the semiconductor device has an angle of 40 to 40 degrees. 6. A semiconductor device comprising a gate electrode, a semiconductor pattern formed of an insulating layer and a semiconductor layer on an insulating substrate, and a source and drain electrode formed so as to intersect with the gate electrode in the semiconductor pattern region, The gate electrode having an electrode end portion forward-tapered and the semiconductor pattern having an end portion forward-tapered are formed on the gate electrode, and the gate electrode has a retreat distance (A) from a lower end portion to an upper end portion. Ratio of film thickness (B) (taper ratio: B / A)
Of the semiconductor pattern is 3 times or less than the taper ratio (B ′ / A ′) of the end portion of the semiconductor pattern. 7. The semiconductor device according to claim 6, wherein the gate electrode has a taper ratio (B / A) of 0.2 to 0.8. 8. A gate electrode and a drain electrode are arranged near each intersection of a plurality of scanning signal lines and video signal lines formed on one of a pair of substrates so as to intersect with each other, and a gate electrode is a scanning signal line and a drain electrode is an image. In a liquid crystal display device comprising a signal line and a thin film transistor in which a source electrode is connected to a pixel electrode, a gate electrode having a forward tapered end on an electrode end and a semiconductor having a forward tapered end on the gate electrode A pattern is formed, and the forward taper angle θg of the gate electrode is 3 times or less than the forward taper angle θs of the end portion of the semiconductor pattern (however,
The liquid crystal display device is characterized in that it has a liquid crystal layer sandwiched between the other transparent substrate and a liquid crystal alignment film between the other transparent substrate. 9. A pair of substrates are arranged near each intersection of a plurality of scanning signal lines and video signal lines formed on one substrate so as to intersect with each other, and a gate electrode is a scanning signal line and a drain electrode is a video signal. In a liquid crystal display device comprising a signal line and a thin film transistor in which a source electrode is connected to a pixel electrode, a gate electrode having a forward tapered end on an electrode end and a semiconductor having a forward tapered end on the gate electrode A pattern is formed, and the ratio of the film thickness (B) to the receding distance (A) from the lower end to the upper end of the gate electrode (taper ratio: B / A)
Has a taper ratio (B '/ A') of the semiconductor pattern end portion of 3 times or less, and has a liquid crystal layer sandwiched between the other transparent substrate and a liquid crystal alignment film. Liquid crystal display device characterized by.