JPH0864830A - Active matrix substrate and method of fabrication thereof - Google Patents

Abstract

(57) [Abstract] [Purpose] High mobility TFT and good OF in the same substrate
An active matrix substrate having a TFT having F characteristics is formed without increasing the number of manufacturing steps. [Structure] The display unit 2 on an active matrix substrate 1 is provided with pixel TFTs 4 connected to pixel electrodes 107 arranged in a matrix. A data signal output circuit and a scanning circuit are formed as the drive circuit section 3 on the active matrix substrate 1. Pixel TFT4
An LDD region 10 to which boron and phosphorus are added is formed in contact with the source region 5 and the drain region 7. The LDD region 10 can be formed without increasing the number of manufacturing processes by the phosphorus ion implantation process and the boron ion implantation process for forming the CMOS forming the data signal output circuit and the scanning circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driver monolithic active matrix substrate used in an active matrix driving type liquid crystal display device and a method for manufacturing the same.

[0002]

2. Description of the Related Art In recent years, thin film transistors (hereinafter referred to as TFTs) have been developed for application to image display elements such as flat panel displays including liquid crystal display devices.
In particular, a driver monolithic panel in which a display section and a drive circuit section are formed on the same substrate using a polycrystalline silicon TFT has been actively developed.

An example of application of a conventional active matrix substrate to a liquid crystal display device will be described below with reference to FIGS.

FIG. 5 is a plan view showing a conventional driver monolithic type active matrix substrate, and FIG. 6 is an enlarged view of one pixel portion in the display section 101 of FIG.
FIG. 7 is a partially enlarged view of the complementary circuit section used in the data output circuit section 102 and the scanning circuit section 103. 8 is an electrically equivalent circuit diagram of FIG. 6, and FIG. 9 is an electrically equivalent circuit diagram of FIG. 7.

5 to 9, the display unit 10 is provided on the substrate.
1 is formed, and a data output circuit section 102 and a scanning circuit section 103 are formed around the display section 101 as a drive circuit section. A data signal line 104 and a scanning signal line 105 are connected to the data output circuit unit 102 and the scanning circuit unit 103, respectively. The display unit 101 includes a plurality of data signal lines 104 parallel to each other.
And a plurality of scanning signal lines 105 which are parallel to each other are formed so as to intersect with each other. An N-channel type TFT or a P-channel type TFT is provided as the pixel TFT 106 near each intersection.
And a pixel electrode 107 is connected to each pixel TFT 106. The pixel TFT 106 is driven by a scanning signal from the scanning circuit unit 103, and a data signal voltage from the data signal line 104 is applied to the pixel electrode 107. .

The complementary circuit used in the output section of the data output circuit section 102 and the scanning circuit section 103 is mainly used for outputting one of the signals from the left and right lines, as shown in FIG. N channel type TF
It is composed of a CMOS in which T108 and P-channel TFT 109 are provided in a complementary type, and the speedup of the circuit and the power consumption reduction are achieved.

In a liquid crystal panel manufactured by bonding the active matrix substrate and a counter substrate having a counter electrode formed thereon and enclosing a liquid crystal material between them, the voltage applied between the pixel electrode and the counter electrode. By driving the liquid crystal by controlling the liquid crystal display device, image display can be realized by utilizing the electro-optical characteristics of the liquid crystal.

[0008]

In the above-mentioned conventional active matrix substrate, the TF formed in the data output circuit section 102 and the scanning circuit section 103 which are the drive circuit section.
Since high mobility is required for T108 and 109, TF
Polycrystalline silicon or single crystal silicon is used for the semiconductor layer of T. However, since a low OFF current is required for the pixel TFT 106 formed in the display unit 101, T
When polycrystalline silicon or single crystal silicon is used as the semiconductor layer of the FT, it is necessary to improve the OFF characteristic of the pixel TFT 106.

A light-doped drain (hereinafter referred to as LDD) structure as shown in FIG. 10 is conventionally known as a technique for improving the OFF characteristic of a TFT. This TF
T is a LD provided inside the source region 111 and the drain region 112 at both ends of the substrate 110 and further inside.
D regions 113 and 113 and these LDD regions 113 and 1
Semiconductor layer 11 having a channel region 114 between
5 is formed. A gate insulating film 116 is formed thereon so as to cover almost the entire surface of the substrate 110 and the semiconductor layer 115, and a gate electrode 7 is formed thereon so as to face the channel region 114. The interlayer insulating film 11 is formed on almost the entire surface of the substrate 110 so as to cover the gate electrode 117.
8 is formed, and the source electrode 119 and the drain electrode 120 are respectively formed thereon, and the gate insulating film 11
6 and the contact hole 121 formed in the interlayer insulating film 118, respectively, and is electrically connected to the source region 111 and the drain region 112, respectively. In this way, the LDD structure TFT is formed.

However, the conventionally known manufacturing method has a problem that the number of manufacturing steps such as a mask forming step for forming the LDD region 113 is increased and the yield is reduced.

On the other hand, Japanese Patent Laid-Open Nos. 5-21801 and 5-21460 disclose methods for forming a high resistance offset region in a source region and a drain region. Further, in Japanese Patent Publication No. 2-61032, a TFT having different mobilities is formed in a display section and a drive circuit section, and a TFT having high mobility is formed only in a drive circuit section requiring high mobility.
A method of forming is disclosed. However, JP-A-5-
In order to form a high resistance offset region in the method disclosed in Japanese Patent Laid-Open No. 21801 or JP-A-5-21460, and in the method disclosed in Japanese Patent Publication No. 2-61032, high mobility is obtained. In order to form the semiconductor layer by separating the portion where the requirement is not required and the portion where the requirement is not required, both methods have a problem that the manufacturing process is increased and the yield is reduced.

The present invention solves the above-mentioned problems of the prior art, and has a high mobility field effect transistor and excellent OFF.
It is an object of the present invention to provide an active matrix substrate and a method for manufacturing the same, in which a field-effect transistor having characteristics can be obtained without increasing the number of manufacturing steps and reducing the yield.

[0013]

In the active matrix substrate of the present invention, pixel electrodes for display are arranged in a matrix in a display section, and pixel switching elements for controlling data signal input to each pixel electrode are provided for each pixel. A scanning signal drive circuit unit that is connected to the electrodes and controls ON / OFF of each pixel switching element, and a data signal drive circuit unit that outputs a data signal to the pixel electrode via each pixel switching element are provided. In the active matrix substrate, the switching element of the scan signal drive circuit and the data signal drive circuit and the pixel switching element include a first transistor having a source region and a drain region doped with phosphorus, and a source region and a drain region. The second transistor with boron added, and phosphorus or boron added Are those having a third transistor region phosphorus and boron is added adjacent to at least one of the channel region side of the source region and the drain region are provided, the objects can be achieved. Further, the region to which phosphorus and boron are added may be formed only between the channel region and one of the source region and the drain region.

In the active matrix substrate of the present invention, phosphorus or boron is added to the source region and the drain region, and phosphorus and boron are added adjacent to at least one of the source region and the drain region on the channel region side. The third transistor in which the region is formed may be an N-type field effect transistor, and P
Type field effect transistor may be used.

Further, in the active matrix substrate of the present invention, the semiconductor layer of the transistor has a mobility μ ≧ 5.
It is preferable that the substrate or the thin film is made of any one of cm ² / V · s of polycrystalline silicon, single crystal silicon, sapphire and diamond.

A method of manufacturing an active matrix substrate according to the present invention is the method of manufacturing an active matrix substrate according to claim 1, wherein the source region and the drain region to which the phosphorus is added and the phosphorus and boron are added. Implanting ionized impurities containing phosphorus into the region, and implanting ionized impurities containing boron into the source region and the drain region to which the boron is added and the regions to which the phosphorus and boron are added. The above-mentioned object is achieved by including a process.

[0017]

In the present invention, the switching element and the pixel switching element of the scanning signal driving circuit and the data signal driving circuit are the field effect transistor in which phosphorus is added to the source region and the drain region, and the source region and the drain region. A field effect transistor in which boron was added, and phosphorus or boron was added to the source region and the drain region, and a region to which phosphorus and boron were added was formed adjacent to at least one of the source region and the drain region. It is composed of a field effect transistor.

The region to which phosphorus and boron are added is adjacent to at least one of the source region and the drain region, depending on the added amount of phosphorus and the added amount of boron.
It becomes either the high resistance offset region or the LDD region. The offset region is an intrinsic semiconductor in which phosphorus and boron are added in the same amount, and the LDD region is in which phosphorus and boron are not added in equal amounts and a dopant remains, that is, carriers are present. In any case, the field-effect transistor in which the LDD region or the offset region in which the charge is hard to pass is formed can improve the OFF characteristic.

The phosphorus- and boron-doped regions are implanted with ionized impurities including phosphorus in the source and drain regions to form a phosphorus-doped field effect transistor in the source and drain regions. It can be formed by implanting phosphorus in the step and implanting boron in the step of implanting ionized impurities containing boron in order to form a field effect transistor in which boron is added to the source region and the drain region. . Since both implantation steps are performed in manufacturing an active matrix substrate having a CMOS in the drive circuit section, it is not necessary to increase the number of manufacturing steps.

A field effect transistor in which a region containing phosphorus and boron is formed adjacent to at least one of a source region and a drain region is an N-type field effect transistor in which phosphorus is added to the source region and the drain region. It may be present or may be a P-type field effect transistor added with boron.

The region to which phosphorus and boron are added may be formed adjacent to only one of the source region and the drain region. In this case, if there is only one region to which phosphorus and boron are added, it is not necessary to secure that much region, and the device becomes smaller.

When the semiconductor layer of the field effect transistor is formed by using a substrate or a thin film made of polycrystalline silicon, single crystal silicon, sapphire or diamond having a mobility of μ ≧ 5 cm ² / V · s, a data output circuit, etc. Simpler configuration.

[0023]

Embodiments of the present invention will be described below. In each of the following embodiments, the same numbers are used for the parts having the same functions as the conventional example, and the description thereof is omitted.

(Embodiment 1) FIG. 1 is a sectional view of a driver monolithic active matrix substrate which is Embodiment 1 of the present invention. 2 is an enlarged plan view of one pixel portion of the display unit shown in FIG. 1 and 2, a display unit 2 is formed on the active matrix substrate 1, and a data output circuit 102 and a scanning circuit 103 as a drive circuit unit 3 are formed around the display unit 2. The display unit 2 includes a plurality of data signal lines 104 parallel to each other.
And a plurality of scanning signal lines 105 which are parallel to each other are formed so as to intersect with each other. A pixel TFT 4 is formed in the vicinity of each intersection, the source region 5 is connected to the data signal line 104 by the source electrode 6, and the drain region 7 is connected to the pixel electrode 107 by the drain electrode 8. This pixel TFT
Reference numeral 4 is an N-channel type TFT in which phosphorus is added to the source region 5 and the drain region 7, and the source region 5 and the drain region 7 at both ends and the channel region 9 at the center are provided. LDD regions 10 to which phosphorus and boron are added are formed in contact with the drain regions 7, respectively.

Further, the data output circuit section 1 connected to the data signal line 104 and the scanning signal line 105, respectively.
02 and the drive circuit unit 3 of the scanning circuit unit 103 are mainly composed of an N-channel type TFT 108 and a P-channel type TFT.
It is composed of a CMOS provided with a complementary type 109, and speedup of the circuit and reduction of power consumption are achieved.

The active matrix substrate 1 can be manufactured as follows.

First, as shown in FIG. 3A, a 50 nm semiconductor layer 12 is formed on a glass substrate or an insulating substrate 11 having an insulating film formed on the surface thereof. Various materials such as polycrystalline silicon, single crystal silicon, sapphire, and diamond can be used as the semiconductor layer 12, but polycrystalline silicon, single crystal silicon, and sapphire having a mobility μ ≧ 5 cm ² / V · s. Alternatively, it is preferable to use a thin film made of diamond because the structure of the drive circuit unit 3 such as the data output circuit can be simplified. The lower limit of the mobility μ of 5 cm ² / V · s is determined as a result of the present inventors performing a simulation regarding circuit design. According to this simulation, the following good results were obtained when the mobility μ was set to μ = 5 cm ² / V · s or more, which is a value near the upper limit value in the active element using amorphous silicon. . When the mobility μ of the active element is 5 cm ² / V · s or more, the size of the element forming the pixel section TFT 4 and the circuit can be reduced, so that problems such as a reduction in yield and a reduction in aperture ratio do not occur. .

Then, a gate insulating film 13 is formed on the insulating substrate 11 and the semiconductor layer 12 to have a thickness of about 10 over the entire surface.
A 0 nm SiO ₂ film is formed, and a thickness of 3
A scanning signal line 105 made of Al of 00 nm and a gate electrode 14 branched from the scanning signal line 105 are formed.
The gate electrode 14 is formed above the central portion of the semiconductor layer 12 with the gate insulating film 13 interposed therebetween.

Further, as shown in FIG. 3B, a doping mask 15 is formed by using a photoresist to open a portion into which phosphorus is injected, and ionized impurities including phosphorus are accelerated at a voltage of 90 keV and a dose amount. 4 x 10 ¹⁵ cm
Inject at ^-2 . N-channel TFT by this injection process
108 and the source region 5 and the drain region 7 of the pixel TFT 4, phosphorus is injected, and the P-channel TFT 109
Phosphorus is not implanted into the regions to be the source region 5a and the drain region 7a. In addition, the semiconductor layer 2 below the gate electrode 4 is not implanted with phosphorus and is not channeled to the channel region 9 of the TFT.
Becomes

Next, as shown in FIG. 3 (c), a doping mask 16 is formed by using a photoresist to open a portion into which boron is to be implanted, and ionized impurities including boron are accelerated with a accelerating voltage of 65 keV and a dose. Quantity 65 x 10 ¹⁵
Inject at cm ^-2 . P channel T by this injection process
Boron is injected into the LDD region 10 of the FT 109 and the pixel TFT 4, and the N-channel TFT 108 and the pixel TF are
Boron is not implanted into the source region 5 and the drain region 7 of T4. In addition, the semiconductor layer 2 under the gate electrode 4
Becomes the channel region 9 of the TFT without boron implantation.

After that, as shown in FIG.
An interlayer insulating film 17 is formed of SiN _x of 00 nm, predetermined portions of the gate insulating film 13 and the interlayer insulating film 17 are removed, and contact holes 18 are formed so as to reach the source regions 5 and 5a and the drain regions 7 and 7a. . The source electrode 6 and the drain electrode 8 are formed thereon with a thickness of 500 nm. Furthermore, the display unit 2 has a thickness of 100.
The pixel electrode 107 made of ITO of 8 nm is used as the drain electrode 8
Connect to and form.

In the active matrix substrate 1 thus obtained, the LDD region 10 is formed in contact with the source region 5 and the drain region 7 of the pixel TFT 4, so that the TFTs 108 and 109 of the driving circuit unit 3 are raised. Even if the mobility was increased, the off characteristics of the pixel TFT 4 could be improved. Further, since the LDD region 10 can be formed by two implantation steps for forming the CMOS of the drive circuit section 3, the active matrix substrate 1 can be formed without increasing the number of manufacturing steps. .

(Embodiment 2) In Embodiment 2, FIG.
As shown in (f), the LDD region 10 was formed so as to contact only the source region 5 of the pixel TFT 4a. The active matrix substrate 1a can be manufactured in the same manner as the active matrix substrate 1 of the first embodiment except for the step of implanting ionized impurities containing boron. In this case, since the LDD region 10 to which phosphorus and boron are added is on one side, it is not necessary to secure that much region, and the device becomes smaller.

First, in the same manner as in Example 1, the semiconductor layer 1
2, the gate insulating film 13 and the gate electrode 14 are formed,
As shown in FIG. 4B, ionized impurities containing phosphorus are implanted.

Next, as shown in FIG. 4 (e), a doping mask 16a is formed by using a photoresist to open a portion for implanting boron, and ionized impurities including boron are accelerated at a voltage of 65 keV and a dose. Quantity 65 × 10
Inject at ¹⁵ cm ^-2 . By this implantation step, the source region 5a and the drain region 7 of the P-channel TFT 109 are
a, and boron is injected into the LDD region 10 on the source region 5 side of the pixel TFT 4a, and the N-channel TFT 108
Boron is not implanted into the source region 5 and the drain region 7 of the pixel TFT 4a. In addition, the gate electrode 14
The semiconductor layer 12 below the T layer is not implanted with phosphorus or boron and
It is the channel region 9 of the FT.

After that, as shown in FIG.
An interlayer insulating film 17 is formed of SiN _x of 00 nm, predetermined portions of the gate insulating film 13 and the interlayer insulating film 17 are removed, and contact holes 18 are formed so as to reach the source regions 5 and 5a and the drain regions 7 and 7a. . A source electrode 6 and a drain electrode 8 having a thickness of 500 nm are formed thereon. Furthermore, the display unit 2 has a thickness of 100 nm.
The pixel electrode 107 made of ITO is formed.

In the active matrix substrate 1a thus obtained, the LDD region 10 in contact with only the source region 5 of the pixel TFT 4a is formed.
Even if the TFTs 108 and 109 of the drive circuit section were made to have high mobility, the off characteristics of the pixel TFT 4a could be made good. Further, since the LDD region 10 can be formed by two implantation steps for forming the CMOS of the drive circuit section 3, the active matrix substrate 1a can be formed without increasing the number of manufacturing steps.

As described above, the first and second embodiments of the present invention are described.
2 has been described, the present invention is not limited to this, and various modifications can be made.

In the first embodiment, the LDD region 10 in which phosphorus and boron are added is in contact with the source region 5 and the drain region 7 of the pixel TFT 4, or in the second embodiment, only the source region 5 of the pixel TFT 4a is in contact. Although the LDD region 10 to which phosphorus and boron are added is formed as a result, a high resistance offset region may be formed by adjusting the implantation conditions.

Further, an ionized impurity containing boron was implanted into the source region 5 and the drain region 7 of the pixel TFTs 4 and 4a to form an N-channel type TFT, but an ionized impurity containing phosphorus was implanted. A P-channel type TFT may be formed.

Further, although the TFT having the LDD region 10 is provided in the pixel TFTs 4 and 4a in the first and second embodiments, it is L
The TFT having the DD region 10 or the high resistance region may be formed as a constituent element of peripheral circuits such as the data output circuit unit 102 and the scanning circuit unit 103.

Furthermore, in the first and second embodiments, the gate insulating film 13 is formed of a SiO ₂ film and the interlayer insulating film 17 is formed of SiN _x.
The gate insulating film 13 and the interlayer insulating film 17 are formed by
May be formed of SiN _x , or SiO ₂ / SiN _x
It may be a multilayer structure film. Further, the gate electrode 14, the source electrode 6 and the drain electrode 8 may be made of an alloy such as Al-Si, or may be made of a metal such as Ti, Ta, Cr or Cu. Further, the pixel electrode 107 may use a transparent conductive film such as ZnO ₂ .

Further, the doping masks 15, 16 and 16a used in the impurity implantation step may be formed of an insulating film such as SiO ₂ and the implantation conditions such as acceleration voltage and dose amount may be changed. In addition, after the implantation, steps such as activation of impurities may be added. Further, the steps of implanting the ionized impurities containing phosphorus and the ionized impurities containing boron may be performed in reverse order.

Further, the display section 2 may be provided with other components such as a load capacitance and a resistance, if necessary, and the drive circuit section 3 may be formed with an electric circuit such as another capacitance and a resistance. Good. Further, the field effect transistors 108, 109, 4, 4a formed in the display section 2 and the drive circuit section 3 are
It can also be applied to a field effect transistor using a substrate made of polycrystalline silicon, single crystal silicon, sapphire or diamond having a mobility of μ ≧ 5 cm ² / V · s.

[0045]

As described above, according to the present invention, a high mobility field effect transistor is formed on a substrate portion where high mobility is required, and a low off current in the same substrate is required. It is possible to form a field effect transistor having a good off-characteristic in a desired portion, and to form an LDD region and an offset region without increasing the number of manufacturing steps, so that an active matrix substrate can be manufactured with high yield. .

[Brief description of drawings]

FIG. 1 is a sectional view of a driver monolithic active matrix substrate that is Embodiment 1 of the present invention.

FIG. 2 is an enlarged plan view showing one pixel portion of the display unit 2 in FIG.

3A to 3D are cross-sectional views showing a manufacturing process of the active matrix substrate of Example 1 of the present invention.

4 (e) to (f) are cross-sectional views showing a method for manufacturing an active matrix substrate according to a second embodiment of the present invention.

FIG. 5 is a plan view showing a conventional active matrix substrate.

6 is an enlarged plan view showing one pixel portion of the display unit 101 of FIG.

7 is a partially enlarged plan view of a complementary circuit used in the data output circuit unit 102 and the scanning circuit unit 103 of FIG.

8 is an electrical equivalent circuit diagram of FIG.

9 is an electrical equivalent circuit diagram of FIG. 7. FIG.

FIG. 10 is a cross-sectional view showing a conventional TFT having an LDD structure.

[Explanation of symbols]

 2 display part 3 drive circuit part 4,4a pixel TFT 5,5a source region 6 source electrode 7,7a drain region 8 drain electrode 9 channel region 10 LDD region 11 insulating substrate 12 semiconductor layer 13 gate insulating film 14 gate electrode 15, 16, 16a Doping mask 17 Interlayer insulating film 18 Contact hole 102 Data output circuit 103 Scanning circuit 104 Data signal line 105 Scanning signal line 107 Pixel electrode 108 N-channel TFT 109 P-channel TFT

Claims (4)

[Claims] 1. A pixel electrode for display is arranged in a matrix in a display section, and a pixel switching element for controlling a data signal input to each pixel electrode is provided so as to be connected to each pixel electrode. In the active matrix substrate provided with a scanning signal drive circuit section for controlling ON / OFF and a data signal drive circuit section for outputting a data signal to a pixel electrode through each pixel switching element, the scanning signal drive circuit and The switching element of the data signal drive circuit and the pixel switching element are a first transistor having a source region and a drain region doped with phosphorus, and a second transistor having a source region and a drain region doped with boron. At least one of a source region and a drain region doped with phosphorus, phosphorus or boron The active matrix substrate having a third transistor region phosphorus and boron is added adjacent to the channel region side is provided. 2. The active matrix substrate according to claim 1, wherein the third transistor is an N-type field effect transistor or a P-type field effect transistor. 3. The semiconductor layer of the transistor is composed of a substrate or a thin film made of any one of polycrystalline silicon, single crystal silicon, sapphire and diamond having a mobility of μ ≧ 5 cm ² / V · s. 1 or 2
The active matrix substrate described. 4. The method for manufacturing an active matrix substrate according to claim 1, wherein ionized impurities containing phosphorus are added to the source region and the drain region to which the phosphorus is added and the region to which the phosphorus and boron are added. A method of manufacturing an active matrix substrate, comprising: a step of implanting; a step of implanting an ionized impurity containing boron into the source region and the drain region to which boron is added; and a region to which phosphorus and boron are added.