JPH0865262A - Non-hit switching system - Google Patents
Non-hit switching systemInfo
- Publication number
- JPH0865262A JPH0865262A JP6201676A JP20167694A JPH0865262A JP H0865262 A JPH0865262 A JP H0865262A JP 6201676 A JP6201676 A JP 6201676A JP 20167694 A JP20167694 A JP 20167694A JP H0865262 A JPH0865262 A JP H0865262A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- transmission line
- pointer
- transmission
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はＮＮＩ（同期インタフェ
ース）で規定された信号を伝送するＳＤＨ伝送システム
の冗長系切替方式に関し、特にＮ：１の冗長系を構成す
る伝送システムの無瞬断切替方式に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a redundant system switching system of an SDH transmission system for transmitting a signal specified by NNI (synchronous interface), and more particularly to non-interruptible switching of a transmission system constituting an N: 1 redundant system. Regarding the scheme.
【０００２】[0002]
【従来の技術】従来のＮ：１伝送路における伝送路切替
方式の一例を図２に示す。図２は現用伝送路３本に対し
て予備伝送路１本を有する３：１伝送路冗長構成をとる
場合を示している。送信側では、伝送路切替選択回路１
１により３本の現用伝送路のうちのどれを予備伝送路へ
載せるかの選択を行う。現用伝送路と予備伝送路とでは
遅延時間が同一であることはないので、受信側では伝送
路切替実行に伴い、後段装置でフレ−ム位相のジャンプ
が発生しないように、切替前にフレ−ム位相を揃える必
要がある。2. Description of the Related Art FIG. 2 shows an example of a conventional transmission line switching system in an N: 1 transmission line. FIG. 2 shows a case in which a 3: 1 transmission line redundant configuration having one backup transmission line for three active transmission lines is adopted. On the transmission side, the transmission path switching selection circuit 1
1 selects which of the three working transmission lines is to be mounted on the protection transmission line. Since the delay time is not the same between the working transmission line and the protection transmission line, the receiving side does not cause a frame phase jump in the succeeding device when the transmission line is switched, so that the frame is not changed before the switching. It is necessary to align the system phases.
【０００３】ＳＤＨ伝送方式では、ＳＴＭのフレ−ム位
相に対して内部のペイロード位相は固定されておらず、
ＡＵポインタを用いてＳＴＭフレ−ムとペイロード先頭
との相対的な位置関係を指示する方式をとっている。Ｓ
ＴＭフレ−ム位相合わせは、ＡＵポインタ値を変更して
ＳＴＭフレ−ム位相を変更することにより行っている。
受信側では、現用伝送路３本及び予備伝送路に個別にＡ
Ｕポインタ付替回路１２−１〜１２−４を有すると共
に、現用伝送路３本にそれぞれ伝送路切替回路１３−１
〜１３−３を有し、これらのＡＵポインタ付替回路１２
−１〜１２−４によりＮ＋１本のすべての伝送路のＳＴ
Ｍフレ−ム位相を同一位相に合わせている。伝送路切替
を行う時は、伝送路切替回路１３−１〜１３−３により
送信側で予備伝送路に載せた回線を元の回線出力先に接
続して切替を実行している。In the SDH transmission system, the internal payload phase is not fixed with respect to the STM frame phase.
The method uses the AU pointer to indicate the relative positional relationship between the STM frame and the beginning of the payload. S
The TM frame phase adjustment is performed by changing the AU pointer value to change the STM frame phase.
On the receiving side, A is individually assigned to three working transmission lines and the protection transmission line.
U-pointer replacement circuits 12-1 to 12-4, and three transmission line switching circuits 13-1
AU pointer replacement circuit 12
ST of all N + 1 transmission lines by -1 to 12-4
The M frame phases are matched to the same phase. When performing transmission line switching, the transmission line switching circuits 13-1 to 13-3 connect the line placed on the spare transmission line on the transmission side to the original line output destination and execute switching.
【０００４】図３にＡＵポインタ付替の原理図を示す。
図３（ａ）は送信信号を示し、この信号は伝送路を経て
受信側で図３（ｂ）に示すような予備伝送路信号、現用
伝送路信号となる。現用伝送路と予備伝送路とでは遅延
時間が異なるので、ＳＴＭフレ−ム先頭とペイロード先
頭の位置が異なっている。ＡＵポインタ付替回路の出力
信号は図３（ｃ）に示すようになり、ＳＴＭフレ−ム先
頭が揃えられる。FIG. 3 shows the principle of AU pointer replacement.
FIG. 3A shows a transmission signal, and this signal becomes a backup transmission line signal and a working transmission line signal as shown in FIG. 3B on the receiving side via the transmission line. Since the working transmission line and the protection transmission line have different delay times, the positions of the STM frame head and the payload head are different. The output signal of the AU pointer replacement circuit is as shown in FIG. 3C, and the beginning of the STM frame is aligned.
【０００５】[0005]
【発明が解決しようとする課題】この従来の伝送路切替
方式では、伝送路切替回路の入力部で現用伝送路から受
信した信号と予備伝送路から受信した信号との間でＳＴ
Ｍフレ−ムの位相がそろえられている。そして、伝送路
切替回路の出力は切替前と切替後でフレ−ム位相が変化
することはないため、後段の装置でフレ−ム同期がはず
れることはない。しかし、ＳＴＭフレ−ム位相を合わせ
るためにＡＵポインタ値を変更しているので、図３
（ｃ）に示すように、ペイロード位相は時間Ｔａだけず
れている。このため、伝送路切替前に後段の装置でペイ
ロ−ド信号に瞬断が発生するという問題点があった。In this conventional transmission path switching system, the ST between the signal received from the working transmission path and the signal received from the standby transmission path at the input part of the transmission path switching circuit.
The phases of the M frames are aligned. Since the frame phase of the output of the transmission line switching circuit does not change before and after the switching, the frame synchronization is not lost in the subsequent device. However, since the AU pointer value is changed to match the STM frame phase, FIG.
As shown in (c), the payload phase is shifted by time Ta. For this reason, there is a problem in that a pause occurs in the payload signal in the device at the subsequent stage before switching the transmission path.
【０００６】このような問題点に鑑み、本発明は、Ｎ：
１冗長構成をとるＳＤＨ伝送方式において伝送路切替実
行時に信号の瞬断を防ぐことを課題とする。In view of these problems, the present invention provides an N:
It is an object of the present invention to prevent instantaneous interruption of a signal at the time of execution of transmission line switching in an SDH transmission system having one redundant configuration.
【０００７】[0007]
【課題を解決するための手段】本発明による無瞬断切替
方式は、ＮＮＩで規定された同期信号の伝送を行い、現
用伝送路Ｎ本に対して予備伝送路１本を持つＮ：１の伝
送路冗長構成をとるＳＤＨ伝送システムにおいて、送信
側には、Ｎ本の回線のうち１本を選択して予備伝送路に
送出する伝送路切替選択回路を設け、Ｎ本の現用伝送路
の受信側にはそれぞれ、固定遅延を与える遅延回路とＡ
Ｕポインタの付替により各伝送路のＳＴＭフレ−ム位相
を同一にするＡＵポインタ付替回路と予備伝送路と現用
伝送路とを切り替える伝送路切替回路とを設け、前記Ｎ
本の現用伝送路の受信側に共通に、前記ＡＵポインタ付
替回路によって設定されたポインタ値情報Ｎ本の内の１
本を選択する選択回路を設け、予備伝送路の受信側に
は、前記ＡＵポインタ付替回路の出力ＳＴＭフレ−ム位
相と同一のフレ−ム位相を持ち、かつ前記選択回路によ
って選択されたＡＵポインタの値と同一のＡＵポインタ
値となるように信号の出力位相を調整する遅延調整回路
を設けたことを特徴とする。The instantaneous interruption switching system according to the present invention transmits a synchronization signal specified by NNI, and has N: 1 active transmission lines and one spare transmission line. In an SDH transmission system having a transmission line redundant configuration, the transmission side is provided with a transmission line switching selection circuit for selecting one of N lines and transmitting the selected line to a protection transmission line. And a delay circuit for providing a fixed delay and A
An AU pointer changing circuit for making the STM frame phase of each transmission line the same by changing the U pointer and a transmission line switching circuit for switching between the standby transmission line and the working transmission line are provided.
One of the N pieces of pointer value information set by the AU pointer replacement circuit is commonly used for the receiving side of the working transmission line of the book.
A selection circuit for selecting a book is provided, and the AU selected by the selection circuit has the same frame phase as the output STM frame phase of the AU pointer replacement circuit on the reception side of the backup transmission line. It is characterized in that a delay adjustment circuit for adjusting the output phase of the signal is provided so that the AU pointer value is the same as the pointer value.
【０００８】本発明によればまた、前記遅延調整回路
が、前記ＡＵポインタ付替回路に遅延時間調整用のバッ
ファメモリを付加したものであることを特徴とする無瞬
断切替方式が得られる。According to the present invention, there is also provided a hitless switching system characterized in that the delay adjustment circuit is a circuit in which a buffer memory for delay time adjustment is added to the AU pointer replacement circuit.
【０００９】なお、前記遅延回路による遅延量は、前記
現用伝送路を経由して送信側の入力から受信側の前記Ａ
Ｕポインタ付替回路の入力部までに至る信号の遅延時間
が、前記予備伝送路を経由した場合の送信側の入力から
受信側の前記遅延時間調整回路の入力部までの遅延時間
よりも長くなるように設定される。The amount of delay by the delay circuit is calculated from the input on the transmitting side to the A on the receiving side via the working transmission line.
The delay time of the signal reaching the input section of the U pointer replacement circuit becomes longer than the delay time from the input of the transmission side to the input section of the delay time adjustment circuit of the reception side when passing through the backup transmission path. Is set as follows.
【００１０】[0010]
【作用】現用伝送路には、遅延回路により固定遅延が与
えられる。各遅延回路の出力は、ＡＵポインタ付替回路
によってＳＴＭフレーム位相を等しく合わされる。そし
て、選択回路により、送信側で現在予備伝送路に信号を
載せている伝送路のＡＵポインタの値が選択され、遅延
調整回路に入力される。遅延調整回路は、受信した信号
をバッファメモリに書き込むと共に、ＡＵポインタから
ペイロードの先頭を知り、その書き込み先のメモリアド
レスを記憶する。また、選択回路から入力されたＡＵポ
インタの値と記憶したメモリアドレスとの比較を行い、
バッファメモリからの読み出しアドレスのタイミングを
制御して同一のポインタ値で出力させる。これにより、
伝送路切替回路の入力部でのペイロードの位相は同一と
なる。A fixed delay is given to the working transmission line by a delay circuit. The outputs of the delay circuits are made to have the same STM frame phase by the AU pointer replacement circuit. Then, the value of the AU pointer of the transmission path on which the signal is currently placed on the backup transmission path is selected by the selection circuit and input to the delay adjustment circuit. The delay adjustment circuit writes the received signal in the buffer memory, knows the beginning of the payload from the AU pointer, and stores the memory address of the write destination. In addition, the value of the AU pointer input from the selection circuit is compared with the stored memory address,
The timing of the read address from the buffer memory is controlled to output with the same pointer value. This allows
The phases of the payloads at the input section of the transmission path switching circuit are the same.
【００１１】[0011]
【実施例】次に、本発明について図面を参照して説明す
る。図１は本発明の一実施例のブロック図である。ここ
では、現用伝送路３本（Ｎ＝３）に対して予備伝送路１
本を有する３：１伝送路冗長構成をとっている。送信側
では、伝送路切替選択回路１により３本の現用伝送路の
うちのどれを予備伝送路へ載せるかの選択を行う。Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention. Here, the backup transmission line 1 is used for three active transmission lines (N = 3).
It has a 3: 1 transmission line redundant configuration including a book. On the transmitting side, the transmission path switching selection circuit 1 selects which of the three active transmission paths is to be placed on the backup transmission path.
【００１２】受信側では、現用伝送路３本にはそれぞ
れ、固定遅延をあたえるための遅延回路２−１〜２−
３、ＡＵポインタ付替回路３−１〜３−３、伝送路切替
回路６−１〜６−３が設けられている。また、３本の現
用伝送路の受信側に共通に、ＡＵポインタ付替回路３−
１〜３−３によって設定されたポインタ値情報３本の内
の１本を選択する選択回路４を設けている。更に、予備
伝送路の受信側には、ＡＵポインタ付替回路の出力ＳＴ
Ｍフレ−ム位相と同一のフレ−ム位相を持ち、かつ選択
回路４によって選択されたＡＵポインタの値と同一のＡ
Ｕポインタ値となるように信号の出力位相を調整する遅
延調整回路５を設けている。On the receiving side, delay circuits 2-1 to 2- for giving fixed delays to the three working transmission lines respectively.
3, AU pointer replacement circuits 3-1 to 3-3, and transmission path switching circuits 6-1 to 6-3 are provided. In addition, the AU pointer replacement circuit 3-is commonly used on the receiving side of the three working transmission lines.
A selection circuit 4 is provided for selecting one of the three pieces of pointer value information set by 1-3 to 3-3. Further, on the receiving side of the backup transmission line, the output ST of the AU pointer replacement circuit
A which has the same frame phase as the M frame phase and which is the same as the value of the AU pointer selected by the selection circuit 4.
A delay adjustment circuit 5 is provided to adjust the output phase of the signal so that the U pointer value is obtained.
【００１３】遅延回路２−１〜２−３の遅延量は次のよ
うにして設定される。すなわち、現用伝送路を経由して
送信側の入力から受信側のＡＵポインタ付替回路３−１
〜３−３の入力部までに至る信号の遅延時間が、予備伝
送路を経由した場合の送信側の入力から受信側の遅延時
間調整回路５の入力部までの遅延時間よりも長くなるよ
うに、あらかじめ伝送路遅延を測定したうえで設定され
る。The delay amounts of the delay circuits 2-1 to 2-3 are set as follows. That is, the AU pointer changing circuit 3-1 on the receiving side from the input on the transmitting side via the working transmission line.
3-3 so that the delay time of the signal reaching the input section becomes longer than the delay time from the input on the transmission side to the input section of the delay time adjustment circuit 5 on the reception side when passing through the backup transmission path. Are set after measuring the transmission path delay in advance.
【００１４】このように、遅延回路２−１〜２−３によ
ってあらかじめ現用伝送路の信号を遅らせておくことに
より、後述する予備伝送路の遅延調整回路５と合わせ
て、送信側の入力から受信側の伝送路切替回路６−１〜
６−３の入力部までの現用伝送路を通った信号の遅延時
間と予備伝送路を通った信号の遅延時間とを等しくし
て、両者の信号の位相を同一にすることができる。遅延
回路２−１〜２−３によって固定遅延を与えられた信号
は、次に、ＡＵポインタ付替回路３−１〜３−３によっ
てＳＴＭフレ−ム位相を等しく合わせられる。As described above, by delaying the signal of the active transmission line in advance by the delay circuits 2-1 to 2-3, the signal is received from the input of the transmission side together with the delay adjustment circuit 5 of the standby transmission line described later. Transmission line switching circuit 6-1
By making the delay time of the signal passing through the working transmission path up to the input section 6-3 equal to the delay time of the signal passing through the protection transmission path, the phases of both signals can be made the same. The signals given the fixed delays by the delay circuits 2-1 to 2-3 are then made to have the same STM frame phase by the AU pointer replacement circuits 3-1 to 3-3.
【００１５】なお、この時点ではペイロ−ドの位相は合
っていない。しかしながら、ＳＴＭフレ−ム内のペイロ
−ドの位相は、ＡＵポインタにより指示されているの
で、選択回路４によりＡＵポインタの値から送信側で現
在予備伝送路に信号を載せている伝送路のＡＵポインタ
の値が選択され、遅延調整回路５へ入力される。At this point in time, the phases of the payloads are not in phase. However, since the phase of the payload in the STM frame is designated by the AU pointer, the selection circuit 4 uses the value of the AU pointer to determine the AU of the transmission path on which the signal is currently placed on the backup transmission path on the transmission side. The pointer value is selected and input to the delay adjustment circuit 5.
【００１６】遅延調整回路５は、図示のＡＵポインタ付
替回路に遅延時間調整用のバッファメモリを付加したも
のである。遅延調整回路５は、予備伝送路から受信した
信号をバッファメモリに書き込むと共に、受信したＡＵ
ポインタからペイロードの先端を知り、その書き込み先
のメモリアドレスを記憶する。また、選択回路４から入
力されたＡＵポインタ値と前記メモリアドレスとを比較
してメモリからの読み出しアドレスのタイミングを制御
して同一のポインタ値で出力させる。The delay adjusting circuit 5 is obtained by adding a buffer memory for adjusting a delay time to the illustrated AU pointer replacement circuit. The delay adjustment circuit 5 writes the signal received from the backup transmission line into the buffer memory and also receives the received AU.
The end of the payload is known from the pointer, and the memory address of the write destination is stored. In addition, the AU pointer value input from the selection circuit 4 is compared with the memory address to control the timing of the read address from the memory and output the same pointer value.
【００１７】これにより、現用伝送路を通った信号も予
備伝送路を通った信号も同一のＳＴＭフレ−ム位相、同
一のＡＵポインタを持つことになり、伝送路切替回路６
−１〜６−３の入力部でのペイロードの位相は同一とな
るので、切替を無瞬断で実行できる。As a result, both the signal passing through the working transmission line and the signal passing through the protection transmission line have the same STM frame phase and the same AU pointer, and the transmission line switching circuit 6
Since the phases of the payloads at the input units -1 to 6-3 are the same, switching can be performed without interruption.
【００１８】[0018]
【発明の効果】以上説明したように、本発明ではＮＮＩ
で規定された信号を伝送するＳＤＨ伝送システムの中の
Ｎ：１の冗長系を構成する伝送システムにおいて、予備
伝送路を通った信号と現用伝送路を通った信号とでＳＴ
Ｍフレ−ム位相、ＡＵポインタ値の両者を同一になるよ
うに制御できるようにしたことにより、無瞬断で伝送切
替を実施できる。As described above, according to the present invention, NNI is used.
In an SDH transmission system that transmits a signal specified by the above, in a transmission system that configures an N: 1 redundant system, a signal that passes through a backup transmission line and a signal that passes through a working transmission line ST
By controlling both the M frame phase and the AU pointer value to be the same, transmission switching can be performed without interruption.
【図１】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of one embodiment of the present invention.
【図２】従来例のブロック図である。FIG. 2 is a block diagram of a conventional example.
【図３】ＡＵポインタ付替の原理を説明するための信号
のタイムチャート図である。FIG. 3 is a time chart of signals for explaining the principle of AU pointer replacement.
１、１１ 伝送路切替選択回路 ２−１〜２−３ 遅延回路 ３−１〜３−３、１２−１〜１２−４ ＡＵポインタ
付替回路 ４ 選択回路 ５ 遅延調整回路 ６−１〜６−３、１３−１〜１３−３ 伝送路切替回
路1, 11 Transmission line switching selection circuit 2-1 to 2-3 Delay circuit 3-1 to 3-3, 12-1 to 12-4 AU pointer replacement circuit 4 Selection circuit 5 Delay adjustment circuit 6-1 to 6- 3, 13-1 to 13-3 Transmission line switching circuit
Claims (3)
い、現用伝送路Ｎ本に対して予備伝送路１本を持つＮ：
１の伝送路冗長構成をとるＳＤＨ伝送システムにおい
て、 送信側には、Ｎ本の回線のうち１本を選択して予備伝送
路に送出する伝送路切替選択回路を設け、 Ｎ本の現用伝送路の受信側にはそれぞれ、固定遅延を与
える遅延回路とＡＵポインタの付替により各伝送路のＳ
ＴＭフレ−ム位相を同一にするＡＵポインタ付替回路と
予備伝送路と現用伝送路とを切り替える伝送路切替回路
とを設け、 前記Ｎ本の現用伝送路の受信側に共通に、前記ＡＵポイ
ンタ付替回路によって設定されたポインタ値情報Ｎ本の
内の１本を選択する選択回路を設け、 予備伝送路の受信側には、前記ＡＵポインタ付替回路の
出力ＳＴＭフレ−ム位相と同一のフレ−ム位相を持ち、
かつ前記選択回路によって選択されたＡＵポインタの値
と同一のＡＵポインタ値となるように信号の出力位相を
調整する遅延調整回路を設けたことを特徴とする無瞬断
切替方式。1. An NNI that performs transmission of a synchronization signal specified by NNI and has one backup transmission line for N working transmission lines:
In an SDH transmission system having a transmission line redundancy configuration of 1, the transmission side is provided with a transmission line switching selection circuit that selects one of N lines and sends it to the standby transmission line. The reception side of each of the transmission lines is provided with a delay circuit for giving a fixed delay and an S-channel
An AU pointer changing circuit that makes the TM frame phases the same and a transmission path switching circuit that switches between the standby transmission path and the working transmission path are provided, and the AU pointer is commonly used on the receiving side of the N working transmission paths. A selection circuit for selecting one of the N pieces of pointer value information set by the replacement circuit is provided, and the reception side of the backup transmission line has the same STM frame phase as the output of the AU pointer replacement circuit. Has a frame phase,
A non-instantaneous interruption switching system characterized in that a delay adjusting circuit for adjusting the output phase of the signal is provided so that the AU pointer value is the same as the value of the AU pointer selected by the selecting circuit.
て、前記遅延調整回路は、前記ＡＵポインタ付替回路に
遅延時間調整用のバッファメモリを付加したものである
ことを特徴とする無瞬断切替方式。2. The non-instantaneous interruption switching method according to claim 1, wherein the delay adjustment circuit is a circuit in which a buffer memory for delay time adjustment is added to the AU pointer replacement circuit. Switching mode.
式において、前記遅延回路による遅延量は、前記現用伝
送路を経由して送信側の入力から受信側の前記ＡＵポイ
ンタ付替回路の入力部までに至る信号の遅延時間が、前
記予備伝送路を経由した場合の送信側の入力から受信側
の前記遅延時間調整回路の入力部までの遅延時間よりも
長くなるように設定されることを特徴とする無瞬断切替
方式。3. The non-instantaneous-interruption switching method according to claim 1, wherein the delay amount of the delay circuit is from the input of the transmitting side through the working transmission line to the AU pointer changing circuit of the receiving side. The delay time of the signal reaching the input section is set to be longer than the delay time from the input on the transmission side to the input section of the delay time adjustment circuit on the reception side when passing through the backup transmission path. A non-instantaneous switching system characterized by.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6201676A JP2669355B2 (en) | 1994-08-26 | 1994-08-26 | Instantaneous interruption switching method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6201676A JP2669355B2 (en) | 1994-08-26 | 1994-08-26 | Instantaneous interruption switching method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0865262A true JPH0865262A (en) | 1996-03-08 |
| JP2669355B2 JP2669355B2 (en) | 1997-10-27 |
Family
ID=16445058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6201676A Expired - Lifetime JP2669355B2 (en) | 1994-08-26 | 1994-08-26 | Instantaneous interruption switching method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2669355B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6917584B2 (en) | 2000-09-22 | 2005-07-12 | Fujitsu Limited | Channel reassignment method and circuit for implementing the same |
| JP2009267953A (en) * | 2008-04-28 | 2009-11-12 | Oki Electric Ind Co Ltd | Redundant switching control system, method and program |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01264426A (en) * | 1988-04-15 | 1989-10-20 | Nippon Telegr & Teleph Corp <Ntt> | System for switching transmission line |
| JPH05336085A (en) * | 1992-05-28 | 1993-12-17 | Nec Corp | System for switching transmission line without momentary break |
-
1994
- 1994-08-26 JP JP6201676A patent/JP2669355B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01264426A (en) * | 1988-04-15 | 1989-10-20 | Nippon Telegr & Teleph Corp <Ntt> | System for switching transmission line |
| JPH05336085A (en) * | 1992-05-28 | 1993-12-17 | Nec Corp | System for switching transmission line without momentary break |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6917584B2 (en) | 2000-09-22 | 2005-07-12 | Fujitsu Limited | Channel reassignment method and circuit for implementing the same |
| JP2009267953A (en) * | 2008-04-28 | 2009-11-12 | Oki Electric Ind Co Ltd | Redundant switching control system, method and program |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2669355B2 (en) | 1997-10-27 |
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