JPH0865292A - Signal processor - Google Patents

Abstract

(57) [Summary] [Purpose] To obtain the stable integration judgment result of the control code. In the timing generation circuit 7, a clear pulse is output to the integration determination circuit 8 and an update pulse is output to the update circuit 9 every 18 frames. The integration determination circuit 8 makes an integration determination of the control code during the 18th frame from the immediately preceding clear pulse to the input of the next clear pulse, and outputs the determination result to the update circuit 9. The update circuit 9 updates this control code at the timing of the update pulse.
The sync pulse detection protection circuit 10 detects the master frame identification signal and detects whether or not the master frame is in a sync state. When in the master frame synchronization state, the master frame synchronization flag is set to low level and output to the update circuit 9. When the detection pulse of the master frame identification signal is input from the synchronization pulse detection protection circuit 10, the internal master frame generation circuit 21 generates a master frame pulse in synchronization with this and outputs it to the update circuit 9. The update circuit 9 is
The output of the integration determination circuit 8 is further updated in synchronization with the master frame pulse and is output to the circuit in the subsequent stage.

Description

Detailed Description of the Invention

[0001]

This invention relates to, for example, satellite broadcasting (B
The present invention relates to a signal processing device suitable for use in a PCM decoder of a (S broadcasting) receiver, and more particularly to a signal processing device capable of extracting a stable integration determination result of a control code.

[0002]

2. Description of the Related Art The transmission format of audio data in satellite broadcasting (BS broadcasting) has A mode and B mode types as shown in FIG. It is transmitted in units of a frame of bits. The period of this one frame is 1 ms, and therefore 1000 frames are transmitted per second.

The frame sync code arranged at the beginning of the frame shown in FIG. 10 is a signal for detecting the start of the frame on the receiver side, and has a specific 16-bit pattern as shown in the figure. . The control code following the frame synchronization code is also composed of 16 bits and includes a voice mode identification signal for identifying the A mode and the B mode as well as a signal as shown in FIG.
The 14th code (b14) in this control code is used as a master frame identification signal, and 36 frames (36m
It is set to logic 1 once in s).

Generally, this control code is a demodulator on the receiving side, and by integrating it for N frames (N is an integer), it is possible to obtain a stable and correct control code even at low C / N. . Then, based on the result, the internal operation on the receiving side is determined.

FIG. 11 shows a P mounted on a satellite broadcast receiver.
3 is a block diagram showing an example of a CM decoder unit. In FIG. 11, the QPSK-demodulated audio bit stream (audio data string) is supplied to the frame synchronization detection unit 1. The frame synchronization detector 1 detects the 16-bit frame synchronization signal shown in FIG. 10 from the audio data string and determines the frame synchronization. When the frame synchronization is detected, the frame synchronization detection unit 1 sets the frame synchronization flag to a low level, and supplies it to the control code integration determination unit 3 and the master frame synchronization detection unit 4, respectively.

On the other hand, the main timing generator 2 generates various timing signals from the input audio bit stream and outputs them to the control code integration determiner 3, master frame synchronization detector 4 and signal processor 5. ing.

FIG. 12 is a block diagram showing the configurations of the control code integration determination unit 3 and the master frame synchronization detection unit 4. The control code integration determination unit 3 is composed of a timing generation circuit 7, an integration determination circuit 8, and an update circuit 9, and the master frame synchronization detection unit 4 is
It is composed of a synchronous pulse detection protection circuit 10.

The timing generator 7 receives the control code supplied from the main timing generator 2 when the low-level frame synchronization flag is input from the frame synchronization detector 1, that is, when the frame synchronization is established. Count the gate pulse, and its value is a predetermined value (eg 18)
When, the clear pulse is output to the integration determination circuit 8. The update pulse is output to the update circuit 9 with a slight delay.

The integration judgment circuit 8 extracts the 16-bit control code shown in FIG. 10 from the input audio bit stream, and after the clear pulse is input from the timing generation circuit 7, the next clear pulse is input. The control code is integrated for the period up to. That is, in the case of this example, the control codes for 18 frames are integrated.

The integration here means adding corresponding bits of the 16-bit control code. The content of the control code is changed with the master frame, that is, 36 frames as the minimum unit. In other words, the control code of each frame is the same control code during at least one master frame.

For example, a predetermined bit of the control code is a logical 1
When the noise is not generated, the addition value of 18 frames of that bit is 18. Also, the added value of 18 frames of bits whose logic is 0 should be 0.

On the other hand, when noise occurs, the added value of 18 frames of the bit of logic 1 is 1
It becomes a predetermined value smaller than 8, and the added value of 18 frames of the bit of logic 0 becomes a value larger than 0. However, since the number of times that the logic is inverted due to noise is usually relatively small, a predetermined threshold value is set, and the logic value of the bit is determined based on the threshold value.

For example, of the data for 18 frames,
Even if an error occurs in the data up to 3 frames,
To allow this, bits with an addition value of 16 or more are determined to be logical 1, and bits having an addition value of 3 or less are determined to be logical 0. Such a determination is performed for each of all 16 bits, and according to the principle of majority voting,
The logic of each 16-bit bit is determined, and the 16-bit control code obtained as a result of the determination is output to the update circuit 9 as a correct control code.

The integration determination circuit 8 is a timing generation circuit 7
Each time a clear pulse is input, the determination result of the control code for 18 frames up to that time is output to the update circuit 9, the added value up to that point is cleared, and the control code for the next 18 frames is integrated. Start processing. Immediately after the integration determination circuit 8 outputs the control code subjected to the integration determination to the update circuit 9, the update pulse is input from the timing generation circuit 7 to the update circuit 9. The update circuit 9 updates the control code supplied from the integration determination circuit 8 at the timing when this update pulse is input.

On the other hand, the sync pulse detection protection circuit 10 of the master frame sync detection section 4 includes a main timing generation section 2
The master frame identification signal (the 14th bit of the 16-bit control code shown in FIG. 10) is detected from the audio bitstream with reference to the gate pulse of the master frame identification signal supplied from the audio bitstream.

As described above, the logic of the master frame identification signal is changed from 0 to 1 every 16 frames. The synchronization pulse detection protection circuit 10 outputs the master frame identification signal from the main timing generation unit 2 when the frame synchronization flag output from the frame synchronization detection unit 1 is at a low level, that is, in the state where the frame synchronization is secured. A gate pulse is supplied, and a master frame identification signal of logic 1 is detected from the audio data string with reference to this gate pulse.

When the logic 1 master frame identification signal is detected, the detection pulse is output to the timing generation circuit 7 as a reset pulse. The timing generation circuit 7 resets a built-in counter when receiving a reset pulse input from the synchronization pulse detection protection circuit 10. Then, from that time, counting of the gate pulse of the control code for 18 frames is started. This allows
The clear pulse and the update pulse output from the timing generation circuit 7 are synchronized with the master frame of the audio data string. Therefore, the control code after the integration determination output by the update circuit 9 is a signal synchronized with the master frame of the audio data string.

The control code after the integration judgment output from the control code integration judgment unit 3 is a signal processing for performing processing such as descrambling, deinterleaving, BCH correction, range bit correction, data companding, range control, and output selection. Part 5
Is supplied to. In addition to the timing signal output from the main timing generator 2, the audio bit stream is also supplied to the signal processor 5. The signal processing unit 5 processes the input voice data string in accordance with the control code after the integration determination supplied from the control code integration determination unit 3.

The data output from the signal processing unit 5 is a digital filter / D / A converter (DF-DAC) 6
Is input to the speaker, D / A converted, and then output as a sound signal to a speaker (not shown) or the like.

FIG. 13 is a flow chart showing an algorithm for determining the control code integration in the circuit shown in FIG. That is, when the receiver receives and demodulates the audio data string including the control code, in step S1, the frame synchronization detector 1 determines whether or not the frame synchronization is established. And if the frame is synchronized,
In step S2, the sync pulse detection protection circuit 10 in the master frame sync detector 4 determines whether or not master frame (MF) synchronization is established.

If it is in an asynchronous state, the process proceeds to step S3, and the timing generation circuit 7 is caused to generate a timing signal for integration determination regardless of the reset pulse output from the synchronous pulse detection protection circuit 10. Then, in step S4, the update circuit 9 is caused to update the control code (CB) by free-run regardless of the master frame.

If it is determined in step S2 that master frame synchronization is established, step S2 is performed.
5, the timing generation circuit 7 generates a timing signal for integration determination in synchronization with the reset pulse output from the synchronization pulse detection protection circuit 10. And step S
In step 6, the update circuit 9 updates the control code for each master frame.

FIG. 14 is a timing chart showing how the control code is updated in the master frame cycle. In FIG. 14, a is a control code included in the voice data string transmitted from the satellite, and is 00,0 in the figure.
Numbers such as 1, 11, and 10 represent upper and lower 8 bits of 16 bits in hexadecimal notation. Further, b indicates the transmission timing of the master frame identification signal included in the control code.

On the other hand, c to f in FIG. 14 indicate signals generated on the receiver side, and c indicates a frame synchronization flag generated by the frame synchronization detecting section 1. This flag indicates an asynchronous state at "H" (high level), and indicates a synchronous state at "L" (low level). Further, d represents a reset pulse supplied from the synchronization pulse detection protection circuit 10 to the timing generation circuit 7.

Further, e is an integration decision circuit 8 to an update circuit 9
The control code integration determination result output to
Indicates the integration determination result output from the update circuit 9 in synchronization with the master frame.

[0026]

By the way, in the conventional configuration, some reception failure occurs, the C / N of the received demodulated data is lowered, and the frame synchronization is achieved.
Even when the master frame is out of synchronization, the timing generation circuit 7 is reset when the master frame identification signal is detected. Therefore, as shown in FIG. 14, even after 18 frames have passed, the result of the integration judgment of the control code may not be updated and the previous value may be held as it is. Therefore, this may cause the demodulator to malfunction.

The present invention has been made in view of the above problems, and a signal processing apparatus capable of performing stable integration determination of a control code even when the C / N of received demodulated data is lowered. It is intended to provide.

[0028]

According to a first aspect of the present invention, there is provided a signal processing device comprising: a frame synchronization detecting means for detecting a frame synchronization signal from a received data sequence (for example, the frame synchronization detecting section 1 in FIG. 1); Master frame synchronization detecting means (for example, the master frame synchronization detecting unit 4 in FIG. 1) for detecting the master frame identification signal from the control code, the control code is extracted from the received data string, the control code is integrated, and the integration determination result of the control code is obtained. A signal processing apparatus comprising: a control code integration determining unit (for example, control code integration determining unit 3 in FIG. 1) for outputting, wherein the control code integration determining unit integrates the control code for a predetermined period, and An integration determination circuit that determines the control code (for example, the integration determination circuit 8 in FIG. 2) and an update circuit that stores the output of the integration determination circuit and updates at a predetermined timing (for example, the update in FIG. 2). A road 9) supplies a period designating timing signal to specify the duration of the integration in the integrating decision circuit, a timing generation circuit for supplying an update timing signal to specify the timing of the update to the update circuit (e.g. FIG. 2
Of the timing generation circuit 7), the timing generation circuit, in the state where the frame synchronization is detected by the frame synchronization detection means and the master frame synchronization is detected by the master frame synchronization detection means,
It is characterized in that reset is prohibited.

The master frame synchronization detecting means internally generates a master frame pulse at the cycle of the master frame when the master frame synchronization is detected (for example, the internal master frame generation circuit of FIG. 2). 21) is provided, and the update circuit updates the output of the integration determination circuit based on the update timing signal output from the timing generation circuit, and then performs the integration based on the master frame pulse generated by the internal master frame generation circuit. The output of the judgment circuit can be further updated.

[0030]

In the signal processing apparatus having the above structure, the reset of the timing generation circuit 7 is prohibited when in the master frame synchronization state. Therefore, the C / N of the received demodulated data
Even in a state in which is decreased, the integration determination result of the control code can be reliably extracted.

[0031]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The signal processing apparatus of the present invention will be described below with reference to the embodiments shown in the drawings. FIG. 1 is a block diagram showing the configuration of an embodiment of the signal processing apparatus of the present invention.
In FIG. 1, the same reference numerals as those in each of the blocks in FIG. 11 have the same functions, and therefore, the description of part of them will be omitted.

That is, this embodiment is basically constructed in the same manner as in the case of FIG. 11, and the signal supplied from the master frame synchronization detection unit 4 to the control code integration determination unit 3 is the same as in the example of FIG. Is a reset pulse, whereas in the embodiment of FIG. 1, it is a master frame pulse and a master frame synchronization flag. Other configurations are similar to those in FIG.

FIG. 2 shows a configuration example of the control code integration determination unit 3 and the master frame synchronization detection unit 4 in the embodiment of FIG. The basic configuration of the control code integration determination unit 3 is shown in FIG.
Although similar to the case shown in FIG. 2, the master frame synchronization detection unit 4 has an internal master frame generation circuit 21 in addition to the synchronization pulse detection protection circuit 10.

The master frame sync flag generated by the sync pulse detection protection circuit 10 is supplied to the update circuit 9. Further, the detection signal of the master frame identification signal is supplied from the synchronization pulse detection protection circuit 10 to the internal master frame generation circuit 21. The internal master frame generation circuit 21 is also supplied with one frame pulse for one frame (1 ms) from the main timing generation section 2 and with a frame synchronization flag from the frame synchronization detection section 1. There is.
The internal master frame generation circuit 21 generates a master frame pulse and supplies it to the sync pulse detection protection circuit 10 and the update circuit 9 of the control code integration determination unit 3. Other configurations are similar to those in FIG.

FIG. 3 shows a more detailed configuration example of the sync pulse detection protection circuit 10, the internal master frame generation circuit 21, and the update circuit 9 in FIG. The synchronization pulse detection protection circuit 10 has a gate circuit 31, which uses the gate pulse of the master frame identification signal supplied from the main timing generator 2 as a reference to identify the master frame from the audio data string. The signal is extracted and output to the master frame identification signal detection circuit 32.

The master frame identification signal detection circuit 32 is
When the master frame identification signal is detected, the detection signal is output to the determination circuit 33. The determination circuit 33 determines whether or not master frame synchronization is established, and outputs a master frame synchronization flag to the gate circuit 34 according to the determination result. The gate circuit 34 outputs the master frame synchronization flag supplied from the determination circuit 33 when the frame synchronization flag is at a low level (when frame synchronization is established).

The internal master frame generation circuit 21 is provided with a counter 41. This counter 41 receives the master frame identification signal detection signal from the master frame identification signal detection circuit 32, and the main timing generation unit 2 When one pulse (frame pulse) is counted in one frame supplied by the above, and the count value reaches a preset predetermined value (36 in this embodiment), the master frame pulse To occur. The gate circuit 42 outputs the master frame pulse to the update circuit 9 when the frame synchronization flag is at a low level, that is, when the frame synchronization is established.

The update circuit 9 is provided with a register 51, and the register 51 updates and holds the control code supplied from the integration determination circuit 8 at the timing when the update pulse is input from the timing generation circuit 7. To do. Then, the control code held in the register 51 is transferred to the internal master frame generation circuit 21 in the register 52.
The gate circuit 42 is further updated and held in synchronization with the master frame pulse output from the gate circuit 42. Then, the control code held in the register 51 or 52 is selected by the selection circuit 53 and supplied to the signal processing unit 5 in FIG. Control circuit 54
Controls the selection circuit 53 in response to a master frame synchronization flag supplied from the gate circuit 34 of the synchronization pulse detection protection circuit 10 and a master frame cycle update flag supplied from a circuit (not shown). There is.

Next, the operation will be described with reference to FIG.
Since the operation of the configuration shown in is basically the same as that shown in FIG. 11, the description thereof will be omitted. Therefore, the operation of the configuration shown in FIGS. 2 and 3 will be described below.

When the frame synchronization flag supplied from the frame synchronization detection unit 1 is at a low level, the timing generation circuit 7 refers to FIGS. 6 and 7 for the frame synchronization determination processing in the frame synchronization detection unit 1. That is, later), that is, when the frame synchronization is established, the gate pulse of the control code supplied from the main timing generation unit 2 is counted, and when the count value reaches 18, the integration determination circuit 8 clears it. Supply a pulse. The integration determination circuit 8 has been operated since the last time the clear pulse was supplied.
Next, the integration judgment processing of the control code included in the voice data string input until the clear pulse is supplied is executed in the same manner as in the above case, and the judgment result is output to the update circuit 9.

The register 51 of the update circuit 9 updates and holds this control code at the timing when the update pulse is supplied from the timing generation circuit 7.

The update pulse output from the timing generation circuit 7 is once every 18 frames. That is, it is generated twice during 36 frames, which is the same period as the master frame. As a result, the integration determination circuit 8 shifts the generation timing of the update pulse so as to cross the master frame.
Even when the integration determination process is executed by, the integration determination process can be reliably performed on the control codes for 18 frames in the same master frame before that. Therefore, it is possible to execute the correct processing more reliably.

The gate circuit 31 of the sync pulse detection protection circuit 10 passes the input audio data sequence at the timing when the gate pulse is supplied from the main timing generator 2. Since this gate pulse is generated at the generation timing of the master frame identification signal, the gate circuit 31 eventually separates and extracts the master frame identification signal. Master frame identification signal detection circuit 32
Detects a master frame identification signal from the signal supplied from the gate circuit 31.

That is, as described above, the master frame identification signal is set to logic 1 every 36 frames. When the signal of logic 1 is detected once every 36 frames, the master frame identification signal detection circuit 32 outputs the detection signal to the counter 41. Counter 41
Counts a frame pulse when a signal indicating that the master frame identification signal is detected is input from the master frame identification signal detection circuit 32. And
When the count value reaches 36, the count value is reset to 0 and the operation of counting the frame pulse again is repeated. And when the count reaches 36,
The master frame pulse is output to the determination circuit 33.

The judgment circuit 33 receives the detection signal supplied from the master frame identification signal detection circuit 32 and the counter 41.
From the master frame pulse supplied from the above, it is determined whether or not the master frame synchronization state is established (for details, see FIG.
And FIG. 10), the gate circuit 3 sets the master frame synchronization flag corresponding to the master frame synchronization state.
4 is output. The gate circuit 34 allows the master frame synchronization flag to pass when the frame synchronization flag output by the frame synchronization detection unit 1 indicates that the frame synchronization state is in the frame synchronization state. When the master frame synchronization flag is not passed. Therefore, the master pulse sync flag is output from the sync pulse detection protection circuit 10 only in the frame sync state.

Similarly, the internal master frame generation circuit 21
The gate circuit 42 of 1 passes the master frame pulse output from the counter 41 when the frame synchronization flag indicates that it is in the frame synchronization state, and does not pass when it is not in the frame synchronization state. Therefore, the master frame pulse is also output to the update circuit 9 only when in the frame synchronization state.

The control code held in the register 51 of the updating circuit 9 is updated and held in the register 52 every time a master frame pulse is supplied from the gate circuit 42 of the internal master frame generating circuit 21. Therefore, by adjusting the timing of the frame pulse generated by the main timing generation unit 2 and supplied to the counter 41 of the internal master frame generation circuit 21, the timing of the control code after the integration determination output from the register 52 is changed to a signal. It is possible to change the timing to an appropriate timing and output the signal by the signal processing in the processing unit 5.

When the master frame synchronization flag supplied from the gate circuit 34 represents master frame synchronization and the master frame cycle update flag represents update of the master frame cycle, the control circuit 54 selects the selection circuit. Control 53 to select the output of register 52.
On the other hand, when the master frame is asynchronous, or
When the update of the master frame cycle is unnecessary, the output of the register 51 is selected.

FIG. 4 shows a flow chart of an algorithm relating to the control code integration judgment of the embodiment shown in FIGS. 2 and 3. That is, when the receiver receives and demodulates the voice data string including the control code, in step S11, the frame synchronization detector 1 waits until frame synchronization is achieved.
When the frame is synchronized, the timing generation circuit 7 is caused to generate a timing signal for integration determination in step S12.

Next, in step S13, the sync pulse detection protection circuit 10 of the master frame sync detector 4 determines whether or not master frame sync is established.
When it is determined that the master frame is synchronized,
Moving to step S14, it is determined whether or not the control code after the integration determination needs to be updated with reference to the internally generated master frame pulse. If it is determined in step S14 that the control code after the integration determination is required to be updated by the master frame pulse, step S14
In step 15, the master frame pulse from the internal master frame generation circuit 21 is supplied to the update circuit 9, and the control code is updated for each master frame. That is, the selection circuit 5
3 selects the output of the register 52.

When it is determined in step S13 or step S14 that the master frame is not synchronized or the update is not necessary in the master frame cycle, the process proceeds to step S16, regardless of the master frame pulse. , Free run to update the control code. That is, the selection circuit 53 selects the output of the register 51.

Next, FIG. 5 is a timing chart showing how the control code is updated in the master frame cycle in the signal processing apparatus of the present invention shown in FIGS. The signals indicated by a to f in FIG. 5 correspond to the signals indicated by a to f in FIG. 14 described above, and therefore detailed description of each signal will be omitted.

In FIG. 5, g represents a master frame sync flag output by the sync pulse detection protection circuit 10. Further, h represents a master frame pulse output from the internal master frame generation circuit 21.

The frame sync flag (FIG. 5 (c)) is at a low level (in the state where the frame is synced), and the master frame sync flag (FIG. 5) is also set.
(G)) is at a high level (when master frame synchronization is established), 18 frames (18 m) from that time
After s), when the integration determination result is output to the update circuit 9,
In the update circuit 9, the result of the integration judgment is stored in the register 51.
Is updated with (FIG. 5 (e)). Then, the value is further stored in the register 52 as data synchronized with the master frame pulse output from the internal master frame generation circuit 21.
Is updated and stored in the memory, and is output via the selection circuit 53 (FIG. 5 (f)).

FIG. 6 shows a process when the frame sync detector 1 in FIG. 1 detects the frame sync, that is, a process when the frame sync is detected when the frame sync is not established. First step S2
At 1, the frame sync signal is detected. Then, in step S22, it is determined whether or not the frame synchronization signal is detected. If not detected, step S23
, The variable n is set to 0, and the process returns to step S21.

When it is determined in step S22 that the frame synchronization signal is detected, the process proceeds to step S24, and it is determined whether or not the frame synchronization signal could be detected in the immediately preceding frame. In the immediately preceding frame, when the frame sync signal cannot be detected, it means that the frame sync signal cannot be continuously detected.
The process proceeds to step S25, 1 is set in the variable n, and the process returns to step S21.

If it is determined in step S24 that the frame synchronization signal could be detected even in the immediately preceding frame, it means that the frame synchronization signal could be continuously detected, and thus step S26. , The variable n is incremented by 1, and step S2
Proceed to 7. In step S27, it is determined whether or not the variable n is equal to 3, and when it is not equal to 3, that is, when the variable n is 0, 1 or 2, the process returns to step S21 and the subsequent processes are repeatedly executed. To do. Step S2
When it is determined that the variable n is equal to 3 in 7, that is, when the frame synchronization signal can be detected in three consecutive frames, it is determined to be in the frame synchronization state and the frame synchronization flag is set. Set to low level.

On the other hand, FIG. 7 shows a processing example of the frame synchronization detecting section 1 for determining whether or not the frame synchronization is lost in the frame synchronization state. First step S4
At 1, the frame sync signal is detected. Step S
In 42, it is determined whether or not the frame synchronization signal can be detected. If the frame synchronization signal can be detected, the process proceeds to step S43, and the variable n indicating the number of detectable times is incremented by one. If the incremented variable n is less than 3 (n = 0, 1 or 2), the process returns to step S41.

If it is determined in step S44 that the variable n = 3, the process proceeds to step S45 to perform the process in the frame synchronization state. Further, the process proceeds to step S46, the variables n and m are cleared to 0, and then the process returns to step S41.

If it is determined in step S42 that the frame synchronization signal could not be detected, the process proceeds to step S47, the variable m indicating the number of undetectable times is incremented by 1, and the process proceeds to step S48.

In step S48, it is determined whether the variable m has a value equal to 7. When the variable m is not equal to 7, that is, when the value is any one of 0 to 6, the process returns to step S41 and the subsequent processes are repeatedly executed. If it is determined in step S48 that the variable m is equal to 7, that is, if the frame synchronization signal cannot be detected seven times, it is determined that the frame synchronization is out of sync, and the frame synchronization flag is set. To a high level.

FIG. 8 shows the sync pulse detection protection circuit 1 of FIG.
The determination circuit 33 of 0 represents an example of processing for determining whether or not the master frame synchronization state is established when the master frame synchronization state is not established. First step S
At 61, the master frame identification signal is detected.
In step S62, it is determined whether or not the master frame identification signal can be detected. If the master frame identification signal cannot be detected, the process proceeds to step S63, and the variable n is set to 0.
Is set, and the process returns to step S61.

When it is determined in step S62 that the master frame identification signal can be detected, the process proceeds to step S64, and in the immediately preceding master frame,
It is determined whether the master frame identification signal can be detected. If it is determined that the master frame identification signal could not be detected in the immediately preceding master frame, it means that the master frame identification signal could not be continuously detected.
In step 65, the variable n is set to 1, and the process returns to step S61.

If it is determined in step S64 that the master frame identification signal could be detected even in the immediately preceding master frame, the process proceeds to step S66, the variable n is incremented by 1, and the step S67 is performed.
At, it is determined whether the variable n is equal to 2. When the variable n is not equal to 2, that is, when it is 0 or 1, the process returns to step S61 and the subsequent processes are repeatedly executed. If it is determined in step S67 that the variable n is equal to 2, that is, if the master frame identification signal can be detected twice consecutively, the master frame synchronization flag is set and the master frame synchronization flag is set. Set to low level.

FIG. 9 shows an example of processing for the determination circuit 33 to determine whether or not master frame synchronization is lost in the master frame synchronization state. First, in step S71, the master frame identification signal is detected. In step S72, it is determined whether or not the master frame identification signal could be detected. When the master frame identification signal can be detected, the process proceeds to step S73, and the variable N indicating the number of detectable times is set.
Is incremented by 1 and the incremented variable N
Is less than 2 (N = 0 or 1), step S74
When it is determined in step S77, the process proceeds to step S77.

When it is determined in step S74 that N = 2, the process proceeds to step S75, and the process in the frame synchronization state is performed. Further, the process proceeds to step S76, the variables N and M are cleared to 0, and then the process proceeds to step S77.

When it is determined in step S72 that the master frame identification signal could not be detected, the process proceeds to step S78, and the variable M indicating the number of undetectable times is set to 1
Increment only. Next, in step S79,
It is determined whether the variable M is equal to 7. If the variable M is not equal to 7, that is, if the variable M is any value from 0 to 6, the process proceeds to step S77, and it is determined whether the frame synchronization is lost. If the frame synchronization is not lost, the process returns to step S71.

When it is determined in step S79 that the variable M is equal to 7, that is, when the master frame identification signal cannot be detected 7 times, and in step S77, it is determined that the frame synchronization is lost. If the master frame synchronization is lost,
Set the master frame sync flag to high level.

[0069]

As described above, according to the signal processing apparatus of the present invention, the reset of the timing generation circuit is prohibited in the state where the master frame is synchronized. Can be constantly updated, and malfunction of the demodulator can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a signal processing device of the present invention.

2 is a block diagram showing a configuration example of a control code integration determination unit 3 and a master frame synchronization detection unit 4 in FIG.

3 is a block diagram showing a configuration example of a sync pulse detection protection circuit 10, an update circuit 9, and an internal master frame generation circuit 21 of FIG.

FIG. 4 is a flowchart illustrating the operation of the embodiment of FIGS. 1 to 3.

FIG. 5 is a timing chart explaining the operation of the embodiment shown in FIGS.

6 is a flowchart showing a processing example of frame synchronization detection of the frame synchronization detection unit 1 of FIG.

7 is a flowchart showing a processing example of frame asynchronization detection of the frame synchronization detection unit 1 of FIG.

8 is a flowchart showing a processing example of master frame synchronization detection of the determination circuit 33 of FIG.

9 is a flowchart showing a processing example of master frame asynchronous detection of the determination circuit 33 of FIG.

FIG. 10 is a diagram showing a transmission format of audio data of satellite broadcasting.

FIG. 11 is a block diagram showing a configuration example of a conventional signal processing device.

12 is a block diagram showing a configuration example of a control code integration determination unit 3 and a master frame synchronization detection unit 4 in FIG.

FIG. 13 is a flowchart illustrating the operation of the examples shown in FIGS. 11 and 12.

14 is a timing chart explaining the operation of the example shown in FIGS. 11 and 12. FIG.

[Explanation of symbols]

 1 frame synchronization detection unit 2 main timing generation unit 3 control code integration determination unit 4 master frame synchronization detection unit 5 signal processing unit 6 DF-DAC unit 7 timing generation circuit 8 integration determination circuit 9 update circuit 10 synchronization pulse detection protection circuit 21 internal Master frame generation circuit

Claims (2)

[Claims] 1. A frame synchronization detecting means for detecting a frame synchronization signal from a received data string, a master frame synchronization detecting means for detecting a master frame identification signal from the received data string, and a control code extracted from the received data string, A signal processing device comprising: a control code integration determining means for integrating a control code and outputting an integration determination result of the control code, wherein the control code integration determining means integrates the control code for a predetermined period. , An integration determination circuit that determines the control code from the integration result, an update circuit that stores the output of the integration determination circuit and updates at a predetermined timing, and a period designation that specifies the integration period in the integration determination circuit. A timing generation circuit that supplies a timing signal and also supplies an update timing signal that specifies the update timing to the update circuit. The timing generation circuit is characterized in that reset is prohibited in a state where the frame synchronization detecting unit detects the frame synchronization and the master frame synchronization detecting unit detects the master frame synchronization. Signal processing device. 2. The master frame synchronization detection means comprises an internal master frame generation circuit which internally generates a master frame pulse at a cycle of the master frame when the master frame synchronization is detected, and the update circuit is After updating the output of the integration determination circuit based on the update timing signal output from the timing generation circuit, the output of the integration determination circuit is further increased based on the master frame pulse generated by the internal master frame generation circuit. The signal processing device according to claim 1, which is updated.