JPH0865346A - Coded signal transmission system - Google Patents

Abstract

(57) [Summary] [Object] To reduce the circuit scale of a coded signal transmission system that encodes and transmits a plurality of signals between units or devices. A transmission side 1 of a unit or a device has a clock signal CLK, a frame end pulse EP by a counter 9 and a decoder 10, a code generated by a coding unit 7 and serialized by a shift register 8. The receiving side 2 has a configuration for transmitting the encoded signal CS, and the receiving side 2 parallelly shifts from the shift register 3 at the timing of the frame end pulse EP with the shift register 3 that sequentially shifts by the clock signal CLK to receive the encoded signal CS. And a logic processing unit 4 which decodes the coded signal of and adds it to the status receiving unit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a coded signal transmission system for coding and transmitting various signals between units or devices. When connecting various units such as a backboard panel, etc., which are configured by mounting various electronic parts on a printed circuit board, and transmitting various signals such as control signals and alarm signals between the units, for example, it is obtained from 64 monitoring points. When transmitting the generated alarm signal between the units, it is necessary to transmit 64 bits if 1 bit is allocated to the corresponding monitoring point, but if this is coded, 6 bits will suffice. Therefore, it is possible to reduce transmission bits by encoding. By serializing and transmitting this coded signal, the number of connection lines between the units can be reduced.

[0002]

2. Description of the Related Art FIG. 9 is an explanatory view of a conventional example.
2 is a transmission side and a reception side of a unit or a device, 43 is a shift register, 44 is a logic processing unit, 45 is a state receiving unit, 4
6 is a state transmission source, 47 is a coding unit, 48 is a shift register, 49 is a counter, 50 is a decoder, 51 is a counter, 52 is a decoder, CLK is a clock signal, FP is a frame pulse indicating the beginning of a frame, and EP is EP. Frame end pulse indicating the end of the frame, CS indicates a coded signal.

Transmitting side 4 between units or between devices
From 1 to the receiving side 42, the clock signal CLK, the frame pulse FP, and the coded signal CS are transmitted. The state transmission source 46 of the transmission side 41 is for transmitting a plurality of control signals, supervisory signals and the like collectively to the reception side 42, and adds a plurality of types of signals to the encoding unit 47. The coding unit 47 converts 2 ⁿ types of signals into n-bit coded signals, sets the n-bit parallel coded signals in the shift register 48, and outputs the clock signal CLK.
According to the above, it is sent to the reception side 42 as a serial coded signal CS.

The counter 49 counts the clock signal CLK, applies the set timing signal to the shift register 48, and adds the count content to the decoder 50.
The decoder 50 outputs a frame pulse FP indicating the beginning of the frame.

The receiving side 42 sequentially shifts and receives the coded signal CS by the shift register 43, and adds the parallel output signal to the logic processing section 44. Also, the counter 51 uses the frame pulse FP as a reset pulse to generate a clock signal CL
K is counted, the content of the count is decoded by the decoder 52 to form a frame end pulse EP, and the frame end pulse EP is added to the logic processing unit 44. The logic processing unit 44 adds the decoded output signal of the coded signal to the state receiving unit 45 including a microprocessor at the timing when the frame end pulse EP is added.

FIG. 10 is an explanatory diagram of a conventional code.
It is assumed that n = 4 and 16 types of states are coded with 4 bits. When this code is used, the coding unit 47
Is input with 16 kinds of signals from the state transfer source 46,
It outputs a 4-bit coded signal. Then, it is serially converted by the shift register 48 and transmitted. On the reception side 42, the shift register 43 converts the coded signal into 4-bit parallel coded signals and adds the coded signals to the logic processing section 44. The logic processing unit 44 applies the decoded output signal at the timing of the frame end pulse EP to the state receiving unit 45.

FIG. 11 is a diagram for explaining the operation of the conventional example.
(A) shows the clock signal CLK, (b) shows the frame pulse FP, (c) shows the frame end pulse EP, and (d) shows the coded signal CS. From the sender 41 to the receiver 42,
The clock signal CLK shown in (a), the frame pulse FP shown in (b), and the coded signal CS having 4 bits as one frame shown in (d) are transmitted. On the reception side 42, the counter 51 is reset by the frame pulse FP, the clock signal CLK is counted, and when the clock signal CLK for one frame is counted, the decoder 5
2 to (c), a frame end pulse EP indicating the completion of reception for one frame is added to the logic processing unit 44, and the logic processing unit 44 outputs the decoded output signal for one frame at the timing of this frame end pulse EP. As status receiver 4
Transfer to 5.

[0008]

When transmitting a large number of types of control signals and supervisory signals between units or devices,
It is desired to reduce the number of signal lines, and as described above, the number of transmission bits can be reduced by coding, and the number of signal lines can be reduced by serializing and transmitting. Since this serial coded signal is transmitted as one frame as shown in FIG. 11, it is necessary for the receiving side to recognize the end of the frame and decode and output it.

Therefore, on the receiving side 42, the counter 51 and the decoder 52 form a frame end pulse EP indicating the end of one frame, which is used as the decoding output timing in the logic processing unit 44. Is. Therefore,
When the number of bits in one frame increases, there is a problem that the circuit scale of the counter 51 and the decoder 52 increases accordingly. An object of the present invention is to reduce the scale of a receiving circuit for coded signals.

[0010]

The coded signal transmission system of the present invention will be described with reference to FIG. 1. A plurality of signals are coded between units or devices, and the coded signals are serially clocked. In a coded signal transmission system for transmitting from a transmission side 1 to a reception side 2 together with a signal CLK, the transmission side 1 has a clock signal CLK, a serialized coded signal CS, and a frame end pulse of this coded signal. Also, the receiving side 2 has a configuration for sending EP and the receiving side 2 shifts the coded signal CS in parallel based on the clock signal CLK and the coded signal parallelized by the shift register 3 at the end of the frame. A logic processing unit 4 for decoding and outputting at the timing of the pulse EP is provided.

Further, in a coded signal transmission system in which a plurality of signals are coded between units or devices and the coded signals are serially transmitted together with the clock signal CLK from the transmission side 1 to the reception side 2, 1 has a configuration in which a coded signal in which a single or a plurality of patterns obtained by cyclic shift of one coded signal are assigned to the same code is transmitted in series with a clock signal CLK, and a receiving side 2 is A shift register 3 for sequentially shifting the digitized signal by the clock signal CLK, and the shift register 3
And a logic processing unit for decoding and outputting the parallel output signal of.

Further, in a coded signal transmission system in which a plurality of signals are coded between units or devices and the coded signals are serially transmitted together with the clock signal CLK from the transmitting side 1 to the receiving side 2, 1 is a single or a plurality of patterns obtained by cyclic shift of one coded signal, and a code in which a pattern of "1" (or "0") bits being odd (or even) is assigned to the same code. The receiving side 2 has a configuration for serially transmitting the coded signal together with the clock signal CLK, and the reception side 2 is a logic for outputting the shift register 3 for sequentially shifting the coded signal by the clock signal and the parallel output signal of the shift register for decoding. And a processing unit.

[0013]

On the transmitting side 1, the signal from the state transmission source 6 is coded by the coding unit 7, and the shift register 8 sends out the coded signal CS serially converted according to the clock signal CLK. Further, the frame end pulse EP indicating the end of the frame is displayed by the counter 9 and the decoder 10.
Is generated and sent to the receiving side 2. The receiving side 2 adds the coded signal CS to the shift register 3 and outputs the clock signal CL.
The signal is shifted and received according to K, the parallel output signal is added to the logic processing unit 4, and the decoded output signal is added to the state receiving unit 5 at the timing of the frame end pulse EP from the transmission side 1.
Therefore, at the receiving side 2, the frame end pulse EP
Since a counter and a decoder for forming the circuit are not required, the circuit scale can be reduced.

In the coding unit 7 of the transmitting side 1, a single or a plurality of patterns obtained when one coded signal is cyclically shifted is assigned to the same code. For example, 4
The bit “0101” becomes “101” due to the cyclic shift.
Therefore, the two patterns have the same code. Then, the coded signal is continuously transmitted. On the receiving side 2, the coded signal CS is parallelized by the shift register 3. However, the decoding can be performed even when the parallel output timing is not synchronized with the transmission side 1. That is, in the above case, "0101" or 1
"1010" due to the shift of the clock signal CLK is also decoded as the same code. Therefore, the transmitting side 1 does not need the structure for forming the frame pulse and the frame end pulse.

Further, in the coding unit 7 of the transmission side 1, a single or plural patterns obtained when one coded signal is cyclically shifted and "1" (or "0") is an odd number (or even number). ) Pattern is assigned as the same code. For example, when "1" is an even number, the above "010"
1 "and" 1010 "are assigned as one code, and" 0111 "," 0010 "and the like are not used because" 1 "is an odd number. It is possible to alleviate the restriction on the conversion timing and avoid erroneous decoding due to a transmission bit error.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is an explanatory view of a first embodiment of the present invention, in which 1 is a transmitting side, 2 is a receiving side, which are provided in units or devices, respectively, and are interconnected via wiring such as a backboard panel. Connected to. The transmission side 1 inputs 2 ⁿ types of signals to the encoding unit 7 from the state transmission source 6 that combines a plurality of types of control signals and supervisory signals, and converts the signals into n-bit encoded signals. This n-bit coded signal is applied to the shift register 8 and set by the output signal of the counter 9 which counts the clock signal CLK, and the coded signal CS serially converted according to the clock signal CLK is transmitted to the receiving side 2.

The counter 9 applies a pulse indicating the set timing to the shift register 8 and counts the clock signal CLK so that the frame end pulse EP is output from the decoder 10 when the clock signal CLK for one frame is counted. Control. The frame end pulse EP, the clock signal CLK, and the coded signal CS are transmitted from the transmission side 1 to the reception side 2.

The receiving side 2 sequentially shifts and receives the coded signal CS according to the clock CLK by the shift register 3, adds the parallel output signal to the logic processing section 4, and outputs the decoded output signal by the frame end pulse EP to the status receiving section. Add to 5. Therefore, the counter 49 on the transmitting side in the conventional example
Counter 51 on the receiving side
The decoder 52 (see FIG. 9) can be omitted.
That is, the circuit scale can be reduced.

2A and 2B are diagrams for explaining the operation of the first embodiment of the present invention. FIG. 2A shows a clock signal CLK, FIG. 2B shows a frame end pulse EP, and FIG. 2C shows a coded signal CS.
The coded signal CS shows the case where one frame is composed of 4 bits, and the shift register 8 outputs the clock signal CLK.
Are transmitted serially in synchronism with, and are converted in parallel by the shift register 3 of the receiving side 2, and the end of the frame can be represented by the frame end pulse EP from the transmitting side. It should be noted that although a case where a space is formed between frames is shown, the coded signal C is transmitted from the transmission side so as not to generate a space.
It is also possible to send S continuously and send a frame end pulse EP indicating the end of each frame.

FIG. 3 is an explanatory diagram of the logic processing unit according to the first embodiment of the present invention. As described above, the coded signal CS is 4
The case where the bit structure is shown and 16 kinds of states are shown is shown. In the figure, 11 _{1 to} 11 ₁₆ and 12 _{1 to} 12 ₁₆
Is an AND circuit, 13 is an inverter, 3 is a shift register, and 5 is a status receiving unit.

The shift register 3 sequentially shifts and receives the coded signal CS in accordance with the clock signal CLK and outputs it in parallel in 4 bits. When the coded signal of the 4-bit parallel output is, for example, “0000”, the output signal of the AND circuit 11 ₁ to which the four inverters 13 are connected becomes “1”, and the timing when the frame end pulse EP is “1”. Then, the output signal of the AND circuit 12 ₁ becomes "1". At that time, the output signals of the other AND circuits 12 _{2 to} 12 ₁₆ become “0”. Therefore, the state receiving unit 5 performs the receiving process as the state 1.

If the coded signal is "0001",
The output signal of the AND circuit 11 ₂ to which the three inverters 13 are connected becomes "1", and only the output signal of the AND circuit 12 ₂ becomes "1" at the timing when the frame end pulse EP is "1". Therefore, the state receiving unit 5 changes the state 2
Will be processed as reception. Also, the coded signal is "1.
If it is 111 ", the output signal of the AND circuit 11 ₁₆ to which the inverter 13 is not connected becomes" 1 ", and only the output signal of the AND circuit 12 ₁₆ becomes" 1 "at the timing when the frame end pulse EP is" 1 ". Therefore, the state receiving unit 5 performs the receiving process as the state 16.

FIG. 4 is an explanatory view of the second embodiment of the present invention, in which 21 is a transmitting side, 22 is a receiving side, 23 is a shift register, 24 is a logic processing section, 25 is a state receiving section, and 26 is a state. Transfer source, 27 is a coding unit, 28 is a shift register, 2
9 is a counter.

In this embodiment, the coding unit 2 on the transmitting side 21 is used.
In 7, the same code is assigned to a single or a plurality of patterns obtained when one coded signal is cyclically shifted, and the clock signal CLK and the coded signal CS are continuously transmitted from the transmission side 21 to the reception side 22. To be sent to.

FIG. 5 is an explanatory diagram of the code of the second embodiment of the present invention, showing the case of a 4-bit configuration, for example, "0".
000 "is the same pattern even if it is cyclically shifted,
If this is set to state 1 and "0001" is cyclically shifted, four types of patterns "0010", "0100", and "1000" are obtained, and these are set to the same state 2. When "0011" is cyclically shifted, "0110", "1"
There are four types of patterns, "100" and "1001", and these are in the same state 3. Also, when "0101" is cyclically shifted, it becomes "1010", and there are two types of patterns. Set to 4. Also, “011
When 1 is cyclically shifted, "1110", "110"
There are four types of patterns of "1" and "1011", and these are the same state 5. Similarly, even if "1111" is cyclically shifted, they are the same pattern, and this is state 6.

FIG. 6 is an operation explanatory view of the second embodiment of the present invention, where (a) shows the clock signal CLK and (b) shows the coded signal CS. The coded signal CS is the clock signal C
For example, in the case of a coded signal CS having a 4-bit structure, a correct coded signal is always extracted when 4 bits are taken out while shifting by 1 bit from the beginning. be able to. Therefore,
It is possible to receive and decode the coded signal without using the frame pulse FP and the frame end pulse EP.

FIG. 7 is an explanatory diagram of a logic processing unit of the second embodiment of the present invention, 23 denotes a shift register, 25 is a state receiving unit, 31 _{1-31 6} AND circuit, 33 denotes an inverter. The clock signal CLK from the transmission side and the coded signal CS are added to the shift register 23, and the coded signal CS is converted into 4 bits in parallel.

In this case, the AND circuits 31 _{1 to} 31 ₆ correspond to the states 1 to 6, and the parallel output signals of the shift register 23 are shifted by one bit in accordance with the clock signal CLK. Therefore, for example, in the parallel output signal when the coded signal of the state 2 is received, the output signal of the AND circuit 31 ₂ becomes “1” due to the shift of up to 3 bits, and the output signals of the other AND circuits are Continue to "0". Then, when the output signal of one AND circuit becomes "1", it becomes synchronized thereafter, and the coded signal CS continuously transmitted can be decoded.

FIG. 8 is an explanatory diagram of the code of the third embodiment of the present invention, in which decoding error due to transmission error is prevented by further restricting the code shown in FIG. That is, the pattern is a cyclically shifted pattern, and a pattern in which "1" or "0" is an odd number or an even number is assigned as the same code. For example, if the pattern has a 4-bit structure and includes an even number “1” or “0”, four types of states 1 to 4 can be represented.

In this case, the logic processing unit is shown in FIG.
An AND circuit 31 ₁ and the inverter 33 by four connecting an AND circuit 31 ₆ not connected to the inverter 33, and an AND circuit connected two inverters 33 to adjacent terminals,
It is configured to include an AND circuit in which every other terminal of the inverter 33 is connected. As a result, a coded signal in which "1" changes to "0" or vice versa due to a transmission error will not be decoded. Therefore, the status receiving unit 25 does not malfunction.

In each of the above-mentioned embodiments, the coded signal CS is 4
Although the case of a bit configuration is shown, it is also possible to transmit a large number of types of signals in a larger number of bit configurations.
Further, the logical processing unit on the receiving side is not limited to the configuration shown in FIG. 3 or FIG. 7, but can be configured to correspond to the coding logic of the coding unit on the transmitting side.

[0032]

As described above, according to the present invention, in the system for transmitting the coded signal between the units or the devices, the frame end pulse EP is transmitted from the transmission side 1 to the clock signal CLK and the coded signal CS. The frame end pulse EP is transmitted to the receiving side 2 by transmitting it to the receiving side 2.
It is possible to omit the counter and the decoder for generating the, and there is an advantage that the circuit scale of the receiving side 2 can be reduced.

By transmitting a coded signal in which a single or a plurality of patterns obtained by the cyclic shift of one coded signal are assigned to the same code, the frame pulse FP and the frame end pulse EP are not used. It can be decrypted at the receiving side. Therefore, one signal line can be omitted, and the configuration of the logic processing unit can be simplified.

Further, a single or a plurality of patterns obtained by cyclic shift of one coded signal, and a pattern in which the number of "1" bits is odd or even or the number of "0" bits is odd or even is the same. By transmitting the coded signal assigned to the code, even if a 1-bit error occurs due to noise or the like, erroneous recognition does not occur, so that there is an advantage that the reliability can be improved.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a first embodiment of the present invention.

FIG. 2 is an operation explanatory diagram of the first embodiment of the present invention.

FIG. 3 is an explanatory diagram of a logic processing unit according to the first embodiment of this invention.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

FIG. 5 is an explanatory diagram of a code according to the second embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of the second embodiment of the present invention.

FIG. 7 is an explanatory diagram of a logic processing unit according to a second embodiment of this invention.

FIG. 8 is an explanatory diagram of a code according to the third embodiment of this invention.

FIG. 9 is an explanatory diagram of a conventional example.

FIG. 10 is an explanatory diagram of a code of a conventional example.

FIG. 11 is an operation explanatory diagram of a conventional example.

[Explanation of symbols]

 1 Transmitting Side 2 Receiving Side 3 Shift Register 4 Logic Processing Unit 5 State Receiving Unit 6 State Transfer Source 7 Encoding Unit 8 Shift Register 9 Counter 10 Decoder CLK Clock Signal CS Encoding Signal EP Frame End Pulse

Claims (3)

[Claims] 1. A coded signal transmission system for coding a plurality of signals between units or devices and transmitting the coded signals in series with a clock signal from a transmission side to a reception side, wherein the transmission side comprises: The clock signal, the serialized coded signal, and a frame end pulse of the coded signal are transmitted, and the receiving side parallelizes the coded signal based on the clock signal. A coded signal transmission system, comprising: a shift register for performing a shift operation; and a logic processing unit that decodes the coded signal parallelized by the shift register at the timing of the frame end pulse and outputs the decoded signal. 2. A coded signal transmission system for coding a plurality of signals between units or devices and transmitting the coded signals in series with a clock signal from a transmission side to a reception side, wherein the transmission side comprises: The coded signal, in which a single or a plurality of patterns obtained by cyclic shift of one coded signal are assigned to the same code, is serially transmitted together with the clock signal, and the receiving side is the coded signal. A coded signal transmission system comprising: a shift register for sequentially shifting the shift register according to the clock signal; and a logic processing unit for decoding and outputting a parallel output signal of the shift register. 3. A coded signal transmission system for coding a plurality of signals between units or devices and transmitting the coded signals in series with a clock signal from a transmission side to a reception side, wherein the transmission side comprises: A coded signal in which a single or a plurality of patterns obtained by cyclic shift of one coded signal and a pattern in which "1" (or "0") bits are odd (or even) is assigned to the same code. And a logic processing unit configured to send the coded signal in series with the clock signal, the shift register sequentially shifting the coded signal according to the clock signal, and decoding and outputting a parallel output signal of the shift register. A coded signal transmission system comprising: