JPH0865577A - Character superposition circuit - Google Patents

Abstract

(57) [Summary] [Purpose] Superimpose characters on a video with specified density gradation. [Structure] A video signal 1 is converted into a digital signal by an A / D converter 2 and recorded in an image memory 3. The character pattern generation circuit 4 reads out character data such as ROM, and the arithmetic circuit 5
Is input to and calculated with the data from the image memory, converted into an analog signal by the D / A converter 6 and output. The image memory and the character pattern generation circuit simultaneously input the data in the same row and the same column to the arithmetic circuit based on the signal from the address generation counter 8 based on the synchronization signal from the synchronization separation unit 7.
The arithmetic circuit is composed of a logical product circuit and a logical sum circuit, and performs a logical product operation or a logical sum operation on the basis of the data from the character pattern generation circuit. Superimpose any of the gradation characters in the image.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character superimposing circuit for superimposing and displaying characters in an image, and more particularly to a character superimposing circuit for displaying characters in arbitrary density gradation or displaying characters at arbitrary positions.

[0002]

2. Description of the Related Art A character superimposing circuit is a high-speed switch for generating a character signal in synchronization with a display controller having a built-in character generator or a kanji ROM etc. The video signal is switched to and superimposed on the video and output. However, the type of character is limited in the one with a built-in character generator, and in the one using the kanji ROM, the number of character types can be increased by using a large ROM, but in addition to the need to input a command signal from the outside,
Both are subject to restrictions such as the number of dots forming a character being predetermined. There is also a problem that the character color is only black (or white), or the density gradation can be changed but the number of variable gradations is small.

[0003]

SUMMARY OF THE INVENTION In view of the above problems, the present invention has an object to set the density (gradation) of characters or the display position of characters.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention is an A / D for converting a video signal into a digital signal.
D converter, image memory for recording signals from A / D converter, character pattern generation circuit for outputting character pattern, AND circuit for calculating signal from image memory and signal from character pattern generator And a logical sum circuit, a D / A converter that converts a signal from the arithmetic circuit into an analog signal, a sync separator that separates a sync signal from the video signal, and a signal from the sync separator as a reference As an image memory and an address generation counter that outputs an address to the character pattern generation circuit, or an image memory address generation counter that outputs an address to the image memory with a signal from the synchronization separation unit as a reference, and the synchronization Character pattern address generation counter that outputs an address to the character pattern generation circuit based on the signal from the separation unit , There is provided a character superimposing circuit which is configured by providing an address selection unit for inputting a selection of the address of a character pattern.

[0005]

With the above construction, in the character superimposing circuit according to the present invention, the character pattern generating section outputs a character signal based on the address from the address generating counter, and the arithmetic circuit outputs the character signal from the image memory. It is calculated and superimposed on the required position of the image. Since the arithmetic circuit performs a logical product operation or a logical sum operation according to the bit of the character pattern,
The character can be set to a density gradation corresponding to the number of bits. Alternatively, an address generation counter is separately provided for the image memory and the character pattern generation circuit, and the address of the character pattern can be arbitrarily selected to superimpose the character at an appropriate position in the video.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a character superposing circuit according to the present invention will be described in detail below with reference to the drawings. 1 is a block diagram of an essential part of an embodiment of a character superimposing circuit according to the present invention, and FIG. 3 is a block diagram of an essential part of another embodiment of a character superimposing circuit according to the present invention.

In FIG. 1, 1 is a video signal and 2 is an A / D.
In the converter, the video signal 1 is input to the A / D converter 2 and converted into a digital signal. An image memory 3 is a VRAM or the like, and records a signal from the A / D converter 2. A character pattern generation circuit 4 uses a ROM or a RAM. An operation circuit 5 operates the data read from the image memory 3 and the data from the character pattern generation circuit 4. Reference numeral 6 is a D / A converter, which converts the signal from the arithmetic circuit 5 into an analog signal. Reference numeral 7 denotes a sync separator, which separates the sync signal from the video signal 1. 8 is an address generation counter,
The image memory 3 based on the sync signal from the sync separator 4
And the address is output to the character pattern generation circuit 4.

In FIG. 3, reference numerals 1 to 7 are the same as those in FIG. Reference numeral 11 is an address generation counter for the image memory, and 12 is an address generation counter for the character pattern generation circuit, which outputs the address to the image memory 3 or the character pattern generation circuit 4 based on the synchronization signal from the synchronization separation unit 7. . Reference numeral 13 denotes an address selection unit, which appropriately selects an address of the address generation counter 12 for the character pattern generation circuit and sets a character display position.

Next, the operation of the character superposing circuit according to the present invention will be described. In the case of FIG. 1, the video signal 1 is input to the A / D converter 2 and converted into, for example, 8-bit digital data. The digitally converted data is taken into the image memory 3 composed of VRAM or the like and written for each image. A character pattern is written in advance in the ROM or the like of the character pattern generation circuit 4. Alternatively, a RAM may be used to write an appropriate character pattern. The character pattern generation circuit 4 reads out and outputs a character pattern in a ROM or the like in response to a signal from the address generation counter 8 and inputs it to the arithmetic circuit 5. Since the same address is used for the image memory 3 and the character pattern generation circuit 4 as the data input to the arithmetic circuit 5, the data in the same row and the same column are simultaneously input from the image memory 3 and the character generation pattern generation circuit 4.

The operation circuit 5 operates the data from the image memory 3 and the data from the character pattern generation circuit 4, and is provided with a logical product circuit (AND gate) and a logical sum circuit (OR gate), and The logical product operation or logical sum operation is performed according to the bit configuration. That is, for example, when outputting a character with a gradation of “1AH” (= “00011010”), the character pattern generation circuit 4 follows the bit configuration and outputs data at the 1st, 3rd, 6th, 7th, and 8th bits from the lower bit. The data "0" is read out from the ROM or the like, and the data "1" at the second, fourth and fifth bits from the lower bit is output. As shown in FIG. 2, when the character bit is "0", the logical product operation is performed with the data from the image memory 3, and the character data "0" outputs the character data "0" and the character data "1". The data from the image memory 3 is output, and when the character bit is "1", the logical sum operation is performed. When the character data "0" is output, the data from the image memory 3 is output. For "1", the character data "1" is output. As a result, a character with a gradation of "1AH" is output. In this way, if the number of bits of a character is n, it is possible to output at any gradation within the nth power of 2, and it is possible to freely change the density gradation by changing the bit configuration of the character. You can
The data from the arithmetic circuit 5 is converted into an analog signal by the D / A converter 6 and output.

In the case of FIG. 3, the character pattern generation circuit 4 reads a character pattern from a ROM or the like in accordance with a signal from the character pattern circuit address generation counter 12 and inputs it to the arithmetic circuit 5, and the image memory 3 generates an image memory address. counter
Read the image data recorded according to the signal from 11,
Input to the arithmetic circuit 5. The arithmetic circuit 5 is composed of, for example, an AND circuit, and calculates data from the image memory 3 and data from the character pattern generation circuit 4. The address input to the character pattern generation circuit 4 is the character pattern circuit address generation counter 12 based on the designation of the address selection unit 13.
Address, and can be set at a timing different from the address applied to the image memory 3.
As shown in FIG. 4, it is possible to superimpose characters in the video at arbitrary timing according to the setting. Therefore, the ROM or the like only needs to have a capacity capable of storing the required number of character data, or if the capacity of the ROM or the like is large, a large number of characters are stored in the ROM or the like and a character is selected from them. Then, the selected character can be displayed at the specified position.

[0012]

As described above, according to the character superimposing circuit of the present invention, a character can be displayed with an arbitrary gradation (density). Therefore, the character can be made conspicuous according to the application of the device. It is possible to display it, or to display it without disturbing the image. Further, since the character read from the character pattern ROM or the like can be superimposed on a specified position in the image, a large number of characters are stored in the ROM or the like, a character is selected from this, and the character is superimposed on the specified position. It is possible to do so.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of an embodiment of a character superimposing circuit according to the present invention.

FIG. 2 is a diagram illustrating a calculation of character data and image data.

FIG. 3 is a block diagram of a main part of another embodiment of the character superimposing circuit according to the present invention.

FIG. 4 is a diagram illustrating superposition of characters.

FIG. 5 is a diagram illustrating a conventional character pattern ROM.

[Explanation of symbols]

 1 Video Input 2 A / D Converter 3 Image Memory 4 Character Pattern Generator 5 Operation Circuit 6 D / A Converter 8 Address Generator Counter 11 Image Memory Address Generator Counter 12 Character Pattern Circuit Address Generator Counter 13 Address Selector

Claims (7)

[Claims] 1. A for converting a video signal into a digital signal
A / D converter, an image memory for recording signals from the A / D converter, a character pattern generating circuit for outputting a character pattern, and a logical product for calculating a signal from the image memory and a signal from the character pattern generating circuit. An arithmetic circuit composed of a circuit and an OR circuit, a D / A conversion section for converting a signal from the arithmetic circuit into an analog signal, a sync separation section for separating a sync signal from the video signal, and a signal from the sync separation section. A character superposing circuit composed of the image memory and an address generating counter for outputting an address to the character pattern generating circuit as a reference. 2. The arithmetic circuit performs a logical product operation or a logical sum operation for each bit in accordance with the data from the character pattern generation circuit to generate a character having a required gradation. Character superposition circuit described. 3. The character pattern generation circuit is configured by using a character pattern ROM.
Character superposition circuit described. 4. The character superimposing circuit according to claim 1, wherein the character pattern generating circuit is composed of a RAM, and the character pattern can be changed or the character display position can be moved. 5. A for converting a video signal into a digital signal
A / D converter, an image memory for recording signals from the A / D converter, a character pattern generating circuit for outputting a character pattern, and a logical product for calculating a signal from the image memory and a signal from the character pattern generating circuit. An arithmetic circuit consisting of a circuit,
A D / A converter that converts a signal from the arithmetic circuit into an analog signal, a sync separator that separates the sync signal from the video signal, and an image that outputs an address to the image memory on the basis of the signal from the sync separator. Character superposition comprising a memory address generation counter, a character pattern address generation counter for outputting an address to a character pattern generation circuit on the basis of a signal from the sync separation unit, and an address selection unit for inputting selection of a character pattern address. circuit. 6. The character superimposing circuit according to claim 5, wherein the character pattern generating circuit comprises a character pattern ROM. 7. The character superimposing circuit according to claim 5, wherein the character pattern generating circuit is composed of a RAM so that the character size can be changed or the character can be added.