JPH086814A - Instruction string extraction processor - Google Patents

Abstract

(57) [Summary] [Object] With regard to processing for a disassembler of a computer program, an object is an instruction string extraction processing device that automatically separates an instruction area and a data area of a binary program module. [Structure] The start point registration unit 2 registers the start address, which is the entrance address of the binary module 1 and the address pointed to by the address constant, as start point addresses, in the start point information storage unit 5. And the simulation part 3
For each start point information, the binary module 1 sequentially simulates the predetermined execution contents of each instruction from the start point address, and when an invalid instruction is detected, immediately processes the start point information. End, branch instruction processing unit 4
When the unconditional branch instruction is detected by the analysis, the address range is output to terminate the processing, and each branch destination address of the detected branch instruction is set as new start point information with respect to the execution route. It is configured to be added to the starting point information storage unit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction string extraction processing device for separating an instruction area and a data area of a binary program module for processing a so-called disassembler for a computer program.

[0002]

2. Description of the Related Art As is well known for computer programs, an object module is created by translating a source program into binary representation information by an assembler or the like, and this object module is combined. The program can be executed by performing edit processing to generate a load module and loading the load module into the main memory.

In a situation such as program maintenance, the contents of an object module or load module (hereinafter, collectively referred to as a binary module) consisting of the above-described binary representation of program information,
It is sometimes necessary to convert into a format of a source program expressed in a so-called assembler language, and as is well known, a tool for performing the conversion is called a disassembler.

By the way, since an instruction and data other than the instruction are mixed in the binary module and it is not possible to directly discriminate the instruction and the other data with respect to the information in the binary format, the disassembler uses the instruction information in the binary format. In order to correctly analyze the data and convert it to the assembler language, the address range between the instruction string part and the non-instruction data part in the binary module is used as the disassembler parameter for the process. Need to be given to.

Therefore, a program maintainer or the like reads the control information and other various information of the binary module of the target program, and decodes the binary representation information of the module to some extent to obtain the address range. The work requires considerable experience, knowledge and effort.

An object of the present invention is to provide an instruction string extraction processing device for automatically identifying an instruction string portion and a data portion other than an instruction from a binary module.

[0007]

FIG. 1 is a block diagram showing the configuration of the present invention. The figure shows the configuration of an instruction sequence extraction processing device, and for a binary module 1 of a computer program in binary representation, which consists of an instruction sequence of a predetermined machine language instruction and data other than the instruction, determines the address range of the instruction sequence portion. And a start point registration unit 2, a simulation unit 3, and a branch instruction processing unit 4.

The start point registration unit 2 is a binary module 1
From the control information, the entrance address and the address pointed to by the address constant are used as starting point addresses, and each starting point address and a predetermined initial value of the register are registered as starting point information in the starting point information storage unit 5.

The simulation unit 3 includes a start point information storage unit 5
For each of the start point information registered in, the binary module 1 is analyzed as a sequence of instructions from the start point address of the start point information, the predetermined execution contents of each instruction are sequentially simulated, and an invalid instruction is executed. When is detected, the process related to the start point information is ended.

When the unconditional branch instruction is detected by the analysis by the simulating section 3, the branch instruction processing section 4 judges the area from the start point address to the unconditional branch instruction as an instruction string. , The address range of the instruction string is output, the processing relating to the start point information is ended, and the branch destination address of the branch instruction detected in the analysis processing for the instruction string and the content of the register at the time of the branch Is added to the starting point information storage unit 5 as new starting point information.

[0011]

According to the instruction string extraction processing device of the present invention, the entry address which is the execution start point of the binary module, the address relating to the address constant which may be the starting point of the instruction string, and the branch detected during the processing The branch destination address of the instruction is used as the starting point address, and the area where the addresses are continuous from each starting point address is analyzed until an unconditional branch instruction is detected. If all the instructions are normal, it is used as one execution route. Judge as an instruction sequence.

In the meantime, for example, a simulation of instruction execution is performed within a range necessary to determine the branch destination of the branch instruction, and the register value is updated. If an invalid instruction is detected while the unconditional branch instruction is not detected, the root is the area other than the instruction (that is, the contents of the binary data from the start point to that point happens to be the instruction sequence. It was determined to be).

As described above, the instruction string portion can be automatically extracted from the binary module.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described below with reference to FIG. 1 and the flow chart of the processing shown in FIG.

The binary module of the computer program has, as control information of the module, one or more entry addresses in the module and a required number of entry addresses corresponding to the entry of the program designated by the source program and the address constant. The address pointed to by the address constant is shown.

The entry address is, of course, the starting point of the program, and the address pointed to by the address constant may be the starting point of a certain route in the program. Therefore, the starting point registration unit 2 in FIG. 3 reads the binary module 1 given in processing step 10 of FIG. 3, extracts all the addresses indicated by the entrance address and the address constant from the control information in processing step 11, and sets the starting point information for each address as the starting point. Register in the information storage unit 5.

Each start point information is made up of a start point address and an initial state of a set of registers included in a processing unit that executes the program of this binary module. The state of each register is the register content and content type (empty). , Numerical value, program address, etc.).

The starting point registration unit 2
Each of the fetched addresses is used as a starting point address.
Regarding the initial state of the register, according to the programming convention of the system that generated this binary module,
For example, the content of the 15th general-purpose register (R15) is the start point address, the content type is "program address", and R
Since the return address to the caller of this program should be entered in 14, the content type is set to "program address" in the same way, and the content type is set to "empty" for all other registers and no content is set. Represents

Next, the simulation unit 3 performs the processing step 12
When one piece of start point information is taken out from the start point information storage section 5 and deleted from the start point information storage section 5, the simulation based on the start point information is started.

That is, first, in the processing step 13, the starting point address is set as the instruction address, in the processing step 14, one instruction starting from the instruction address is taken out from the binary module 1, and in the processing step 15, the execution of the instruction is simulated.

In the instruction execution simulation, register update by instruction execution is simulated, and when the contents are set in the register, it can be identified that the content type is an address in the module (load address). "Program address" in "Instructions" and "Numerical value" in others.

Next, in processing step 16, it is identified whether the fetched instruction is an invalid instruction. The invalid instruction includes an undefined instruction code and a case where the content type of the register holding the branch destination address specified by the branch instruction is not “program address”.

If the instruction is not an invalid instruction in the processing step 16, it is identified in the processing step 17 as a conditional branch instruction. If the instruction is a conditional branch instruction, the branch instruction processing unit 4 in the processing step 18 The start point information that temporarily sets the branch destination as the start point address and the register state at that time as the initial state of the register is temporarily registered in the start point information storage unit 5.

After that, the simulation unit 3 performs the processing step 19
Then, the instruction address is advanced to the next step and the process step 14 is returned to.
If it is not a conditional branch instruction, it is identified as an unconditional branch instruction in processing step 20, and if it is not an unconditional branch instruction, the processing proceeds to processing step 19.

If it is an unconditional branch instruction, the branch instruction processing unit 4 outputs an address from the starting point address of the current processing to the end of the instruction word of the unconditional branch instruction as a range of the instruction sequence in processing step 21. .

Further, in the processing step 22, when the branch destination of the unconditional branch instruction is not R14, the start point information is created from the branch destination address and the state of the register at that time, and is registered in the start point information storage unit 5, Further, after all the start point information temporarily registered as described above is made valid, the control is returned to the simulation unit 3.

If it is determined in step 16 that the instruction is an invalid instruction, the branch instruction processor 4 proceeds to step 24 to register all the start point information temporarily registered in the start point information storage 5 as described above. Cancel and return control to the simulation unit 3.

The simulation unit 3 accesses the starting point information storage unit 5 in processing step 23 to identify whether there is unprocessed starting point information, and if there is unprocessing, returns to processing step 12 and
If there is no unprocessed processing, the processing related to the given binary module ends.

As a result of the above processing, as shown in FIG. 2A, the route of consecutive addresses from the starting point a indicated by the starting point information to the unconditional branch instruction is extracted as an instruction string, and each of the routes between them is extracted. The branch destination of the branch instruction is a new start point b
Etc.

Further, as shown in FIG. 2B, when an invalid instruction is detected in the processing from the starting point c, the route starting from the starting point c is the branch destination of the branch instruction as shown by the cross mark. All the routes including the route of the start point d newly set in are considered not to be instruction sequences.

[0031]

As is apparent from the above description, according to the present invention, the address range between the instruction string of the binary module and the data other than the instruction is automatically divided as the preprocessing of the disassembler, and the work is performed. There is a significant industrial effect of improving efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of the present invention.

FIG. 2 is a diagram for explaining the processing of the present invention.

FIG. 3 is a flow chart of processing of the present invention.

[Explanation of symbols]

 1 Binary module 2 Start point registration section 3 Simulation section 4 Branch instruction processing section 5 Start point information storage section 10-24 Processing steps

Claims (1)

[Claims] 1. An instruction sequence for determining an address range of a portion of the instruction sequence for a binary module (1) of a computer program in a binary representation, which consists of an instruction sequence of a predetermined machine language instruction and data other than the instruction. An extraction processing device, which has a starting point registration unit (2), a simulation unit (3), and a branch instruction processing unit (4), and the starting point registration unit (2) is the binary module (1). From the control information, the entry address and the address pointed to by the address constant are used as start point addresses, and each start point address and a predetermined initial value of the register are registered as start point information in the start point information storage unit (5), The simulation unit (3) arranges the binary module (1) for each start point information registered in the start point information storage unit (5) from the start point address of the start point information to the instruction sequence. Parsed as When the execution contents are sequentially simulated and an invalid instruction is detected, the processing relating to the start point information ends, and the branch instruction processing unit (4) unconditionally analyzes by the simulation unit (3). When a branch instruction is detected, the area from the start point address to the unconditional branch instruction is determined to be an instruction string, the address range of the instruction string is output, and the processing related to the starting point information is ended. Regarding the instruction sequence, each branch destination address of the branch instruction detected in the analysis processing and the contents of the register at the time of the branch are added to the start point information storage unit (5) as new start point information. An instruction sequence extraction processing device characterized in that it is configured.