JPH086823A - Abnormal signal output method of microcomputer - Google Patents

Abstract

(57) [Abstract] [Purpose] WD for monitoring microcomputer runaway
The monitoring circuit is simplified and the runaway detection performance is improved. [Arrangement] When an interrupt command is issued, in a microcomputer that interrupts a normal processing routine and executes an interrupt processing routine, an abnormality determination flag is set for each predetermined block of a normal processing program, and other processing blocks Then, the abnormality determination flag is reset, and when the interrupt processing program is executed, the abnormality determination flag is read, and the abnormality determination signal of the level corresponding to the abnormality determination flag is output and output. The presence / absence of an abnormality is determined from the state of the level of the abnormality determination signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of detecting a runaway of a microcomputer and outputting an abnormality determination signal in a controller that controls using a microcomputer.

[0002]

2. Description of the Related Art A conventional method for monitoring the runaway of a microcomputer and detecting the runaway of the microcomputer is disclosed in Japanese Patent Publication No. Sho 60-32217 and Japanese Patent Laid-Open No. 6-1.
2293.

In the above Japanese Patent Publication No. 60-32217, in a control computer having an interrupt function,
By setting and outputting the abnormality determination signals to different levels in the main process and the interrupt process, the main process and the interrupt process are normally alternately performed at a predetermined cycle. Each is continued for a predetermined time, and a pulse of a predetermined cycle, that is, a watchdog (hereinafter referred to as WD) pulse is output as an abnormality determination signal, and it is determined to be abnormal when the abnormality determination signal continues at the same level for a predetermined time or more. Then, a device for outputting an abnormality determination signal is disclosed.

Further, in the above-mentioned Japanese Patent Application Laid-Open No. 6-12293, in a microcomputer having an interrupt function, an interrupt confirmation flag for confirming that an interrupt has been issued is set in the interrupt processing routine, and main processing is performed. Routine detects the status of the interrupt confirmation flag and normally resets the interrupt confirmation flag if the interrupt confirmation flag is set, then the output of the output port is inverted and output. Is continued for a predetermined time, a pulse having a predetermined cycle is output as a WD pulse as an abnormality determination signal, and the abnormality determination signal continues at the same level for a predetermined time or more, that is, the WD pulse is for a predetermined time. If it is not entered within the specified range, it is judged to be abnormal and the prescribed safety measures are taken. Prevention method is disclosed.

[0005]

However, when a program runaway occurs, the WD pulse is not output, and, for example, in the infinite loop (runaway) of the main process including the WD pulse output process in the main process, the WD
The pulse cycle or the time of the Hi level and the Lo level may change compared to the normal time. Therefore, in the WD monitoring circuit for detecting the program runaway, the WD pulse cycle and the Hi level and the Lo level are detected together with the detection of no pulse. A sophisticated circuit was needed to monitor the level time.

[0006]

Therefore, according to claim 1 of the present invention, when an interrupt command is issued, a normal processing routine is interrupted to execute the interrupt processing routine. Set the abnormality determination flag for each predetermined block of the processing program, reset the abnormality determination flag in the other processing blocks, and read the abnormality determination flag during execution of the interrupt processing program An abnormality signal output of a microcomputer, characterized in that an abnormality determination signal of a level corresponding to a determination flag is output, and whether or not there is an abnormality is determined based on the level state of the output abnormality determination signal. To provide a method.

Further, according to claim 2 of the present invention, the abnormality determination flag is read at the beginning of the interrupt processing program of the above-mentioned claim 1 after the processing for inhibiting the interrupt, and the abnormality determination is performed. Another object of the present invention is to provide an abnormality signal output method for a microcomputer, which is characterized in that an abnormality determination signal of a level corresponding to the operation flag is output.

Claim 3 of the present invention
Further sets a sub-block for prohibiting interrupt processing in each of the processing blocks, and sets the abnormality determination flag in a state inconsistent with the setting in each of the interrupt prohibited sections. An object of the present invention is to provide a method of outputting an abnormal signal of a microcomputer characterized by the above.

According to claim 4 of the present invention, in addition to the above claim 2, in the case where the interrupt processing is performed asynchronously with the program of the main processing, the interrupt processing interrupts at a predetermined cycle. , At the beginning of each processing block in the first half of the main processing program, set or reset each of the above abnormality determination flags, and at the beginning of each processing block in the latter half of the main processing program, perform the above abnormality determination The flag is set to a state that conflicts with the abnormality determination flag set in each processing block in the first half above, and interrupt prohibition is released at the end of the interrupt processing program, and interrupt enable processing is performed to return to main processing. Another object of the present invention is to provide a method for outputting an abnormal signal of a microcomputer characterized by the above.

Further, claim 5 in the claims of the present invention is, in addition to the above-mentioned claim 1, a case of performing a synchronous interrupt process which is synchronized with a program of a main process other than the interrupt process and interrupts at a predetermined cycle. In the main processing program, at the beginning of each processing block, the abnormality determination flag is set or reset, and in the interrupt processing program, the counter is incremented after the processing of prohibiting the interrupt at the beginning. When the above counter reaches at least one predetermined numerical value in the interrupt processing program, the interrupt prohibition is released at the end of the interrupt processing program and the interrupt permission processing for returning to the main processing is performed. The abnormality determination flag is read, and the abnormality determination of the level corresponding to the abnormality determination flag is performed. Outputs a signal, so that the abnormality determination signal is alternately in opposite level to provide an abnormality signal output method of a microcomputer, characterized in that setting the abnormality determination flag.

Claim 6 in the claims of the present invention
Further sets the abnormality determination flag to be set or reset at the head of each processing block in the main processing program, and sets an interrupt prohibited section in each processing block. At the beginning of each interrupt prohibited section, the abnormality determination flag is set to a state that conflicts with the state set at the beginning of each processing block, and at the end of the interrupt prohibited section, the abnormality determination flag is set to Set the same state as the state set at the beginning of the processing block, and in the interrupt processing program, after the process of prohibiting the interrupt at the beginning, output the abnormality determination signal at the same level as the above abnormality determination flags, At the end of the interrupt processing program, the interrupt enable processing is released to cancel the interrupt disable and return to the main processing. It is to provide an abnormality signal output method Yuta.

[0012]

According to the method described in claim 1 of the present invention, the output state of the abnormality determination signal is determined from the abnormality determination flag set in the main processing other than the interrupt processing, and the abnormality is detected. By performing the output processing of the determination signal in the interrupt processing, the abnormality determination signal output from the microcomputer in response to an abnormal operation such as a runaway in processing other than the interrupt processing of the microcomputer having an interrupt function and the interrupt processing. Is set to a high level or a low level, the WD monitoring circuit for monitoring the runaway of the microcomputer only needs to detect the non-pulse state, and should be formed by a circuit of a very simple and inexpensive structure. You can

Further, claim 2 of the present invention
In the method described in (1), the above-described abnormality determination flag is read at the beginning of the interrupt processing program, and the abnormality determination signal of the level corresponding to the abnormality determination flag is output. Therefore, it is possible to prevent the abnormality determination signal from becoming constant at the same level even when the microcomputer is operating normally by performing other interrupt processing one after another during one interrupt processing. The circuit can detect the runaway of the microcomputer more accurately and easily.

Further, claim 3 of the present invention
The method described in 1) is a highly functional WD capable of detecting the period of a pulsed WD signal, Hi level time and Lo level time.
When the monitoring circuit is used, it is possible to detect whether the interrupt prohibition function is operating normally, and a more advanced runaway detection function can be provided.

Further, claim 4 of the present invention
When the interrupt process is performed asynchronously with the program of the main process at a predetermined cycle, the method described in (1) sets the abnormality determination flags set in the first half processing block and the second half processing block of the main process to conflicting states. By doing so, the WD monitoring circuit can detect the runaway of the microcomputer more accurately and easily.

Furthermore, in the method according to claim 5 of the present invention, when the interrupt processing is performed at a predetermined cycle in synchronization with the program of the main processing, the interrupt processing is at the beginning. After disabling interrupts,
A process of adding a counter is performed, and when the counter reaches at least one predetermined numerical value, the abnormality determination flag at that time is read, and an abnormality determination signal of a level corresponding to the abnormality determination flag is output to output the abnormality. By setting the abnormality determination flag so that the determination signals have mutually opposite levels, the WD monitoring circuit can detect the runaway of the microcomputer more accurately and easily.

Further, claim 6 of the present invention
The method described in (1) sets the abnormality determination flag at the beginning of each interrupt prohibited section to a state that conflicts with the state set at the beginning of each processing block, and at the end of the interrupt prohibited section, the abnormality determination Since the flag for use is set to the same state as the state set at the beginning of each processing block, a highly functional WD monitoring circuit that can detect the period of the pulsed WD signal, the Hi level time and the Lo level time is used. In this case, it is possible to more reliably detect whether the interrupt prohibition function is operating normally, and it is possible to provide a more advanced runaway detection function.

[0018]

The present invention will now be described in detail with reference to the embodiments shown in the drawings. FIG. 1 is a schematic block diagram showing a microcomputer system to which the microcomputer abnormal signal output method of the present invention is applied, which mainly includes a microcomputer and an abnormality determination signal, that is, a WD signal monitoring circuit. is there.

In FIG. 1, reference numeral 1 denotes a microcomputer (hereinafter referred to as a microcomputer) to which the abnormal signal output method of the present invention is applied, and 2 denotes the state of the WD signal from the microcomputer 1 and monitors the WD signal from the microcomputer. 1 is a WD monitoring circuit that outputs a runaway state detection signal to the microcomputer 1 when the runaway of the microcomputer 1 is detected.
It is connected to the input terminal of the D monitoring circuit, and the normal / abnormal determination signal output terminal of the WD monitoring circuit 2 (hereinafter referred to as the output terminal) is connected to the reset terminal of the microcomputer 1.

The output terminal of the WD monitoring circuit 2 is
Instead of the reset terminal of the microcomputer 1, it may be connected to another device that performs safety processing or warning processing such as shutting off the power supply of the system or turning on a warning light. These devices are connected to the WD monitoring circuit 2 A predetermined operation is performed by a normal / abnormal determination signal from.

Here, the WD monitor circuit 2 is only required to be able to distinguish between a pulse signal and a signal having a constant Hi or Lo level. Such a circuit is well known, and an example is shown in FIG. ing. The WD monitor circuit shown in FIG. 2 is disclosed in the specification of Japanese Patent Application Laid-Open No. 5-134899, and includes an integrator circuit for converting a pulsed WD signal into a voltage corresponding to its duty ratio. It is possible to determine whether or not the voltage converted by is a pulse signal by a comparison circuit in which a predetermined reference value is set.

In FIG. 2, a microcomputer 51
The pulse signal derived from the line 61 to the resistor R1,
An integrating circuit 62 including R2 and a capacitor C1 converts the voltage into a voltage corresponding to the duty ratio of the pulse signal. A voltage corresponding to the duty ratio of the pulse signal is derived from the line 63.

The output voltage V of the integrating circuit 62 is equal to the resistance R
3 to the inverting input terminal of the comparator 71. The power supply voltage V is applied to the non-inverting input terminal of the comparator 71.
The voltage appearing at the voltage dividing point 64 obtained by dividing cc by the resistors R4, R5, and R6 is given as the reference voltage V1. The output voltage V of the integrating circuit 62 is further supplied to the non-inverting input terminal of the comparator 72 via the resistor R7.
The voltage appearing at the voltage dividing point 65 obtained by dividing the power supply voltage Vcc by the resistors R4, R5 and R6 is input to the inverting input terminal of the comparator 72 as the reference voltage V2 (V2 <V1).

The outputs of the comparators 71 and 72 are commonly connected to the line 66 connected to the reset input terminal Reset of the microcomputer 51. Therefore, the comparator 7
When at least one of 1 and 72 outputs a low level signal, the potential of the line 66 becomes low level.
This line 66 is connected to the power source voltage Vcc via the resistor R8.
Is given. This is because the comparators 71 and 72 are of the open collector output type.

With the above configuration, when the output voltage V of the integrating circuit 62 is V2 <V <V1, the comparators 71 and 7 are provided.
Both outputs of 2 become high level. On the other hand, when the output voltage V of the integrating circuit 62 is V <V2, the comparator 71
Output becomes high level, and the output of the comparator 72 becomes low level. As a result, a current flows through the resistor R8 and this current is absorbed by the comparator 72, so that the line 66 becomes the ground potential. When V1 <V, the low-level signal derived on the line 66 is used as the runaway state detection signal,
The output of the comparator 71 becomes low level, and the output of the comparator 72 becomes high level. As a result, the line 66 becomes the ground potential, so that the microcomputer 51 is reset as in the above case.

Next, FIGS. 3 and 4 show a first method of the present invention.
3 is a flow chart showing an embodiment, FIG. 3 is a flow chart showing a main process of a microcomputer program, and FIG. 4 is a flow chart showing an interrupt process of a microcomputer program, and a main process cycle is 10 ms.
This is a program which operates in ec and performs a periodic interrupt process in which the interrupt process is performed at an interval of 1 msec using the timer interrupt function of a microcomputer asynchronously with the main process. Such a configuration is often used when performing processing such as monitoring an external signal at a fixed cycle or outputting a drive signal to a load.

As shown in FIG. 3, the main process is n (n
Is an integer greater than or equal to 2) processing blocks MB1 to MBn and a time waiting block TB, and each of the processing blocks MB1 to MBn sets a flow for setting an abnormality determination flag F and a flow for performing a predetermined process. Consists of.
Here, as in the present embodiment, each of the processing blocks MB1
If the processing time from MBn to MBn is known in advance, the abnormality determination flag F is set to 0 in the first processing block.
Is set to 1 in the latter half processing block. Needless to say, the abnormality determination flag F may be set to 1 in the first processing block and to 0 in the second processing block.

First, in the processing block MB1, the abnormality determination flag F is set to 0 in step S1a, and then a predetermined processing 1 is performed in step S1b, and then the processing block MB2 is proceeded to. In step S2a, the abnormality determination flag F is set to 0, and then a predetermined process 2 is performed in step S2b. In this way, the same flow is performed in the processing blocks in the first half.
When the integer n is 2, the processing block 2 performs the same flow as the latter processing block described later.

Next, the processing blocks in the latter half will be described from the (n-1) th processing block MBn-1. Processing block M
In Bn-1, in step Sn-1a, the abnormality determination flag F
Is set to 1, and then a predetermined process n-1 is performed in step Sn-1b, and then the process proceeds to process block MBn. In process block MBn, the abnormality determination flag F is set to 1 in step Sna. , A predetermined process n in step Snb
And proceed to the time waiting block TB. In this way, the same flow is performed in the latter processing blocks. When the integer n is 2, the processing block n-1 performs the same flow as the processing block in the first half.

The time waiting block TB has a step S10.
In step S10, if 10 msec has elapsed from the start of the main processing (YES), the processing block M
It returns to step S1a of B1. In step S10, 10
If msec has not elapsed (NO), step S10 is repeated.

Next, the interrupt processing will be described with reference to FIG. First, in step S20, an interrupt prohibition process for prohibiting other interrupts is performed, and then in step S21, the abnormality determination flag F set in the main process at this time.
And a signal of a level corresponding to the abnormality determination flag F, for example, if the abnormality determination flag is 0, a Lo level signal is output from the WD signal output terminal of the microcomputer 1.

Next, in step S22, a predetermined interrupt block 1 is processed, in step S23, the last predetermined interrupt block m (m is an integer of 1 or more) is processed, and then the process proceeds to step S24. Although not described here, between step S22 and step S23, a predetermined number of interrupt blocks are processed corresponding to the integer m, and when the integer m is 1, the step S23 is executed. No, step S22 to step S2
Go to 4.

In step S24, an interrupt permission process for unlocking other interrupts is performed, the interrupt process ends, and the process returns to the main process flow before the interrupt process is performed.

As described above, the interrupt processing shown in FIG.
The process is performed asynchronously with the main process every 1 msec. At each time, the abnormality determination flag F set in the main process is read, and the level signal corresponding to the abnormality determination flag F is read as the WD signal of the microcomputer 1. Since these are output from the output terminal, if these processes are operating normally,
In the interrupt process according to the flow of the main process, a pulse having a constant cycle is output as a WD signal to the WD monitoring circuit 2, and the WD monitoring circuit 2 outputs a normal determination signal.

Next, the operation of the present invention for some runaway examples of microcomputers will be described with respect to the first embodiment.
As a runaway example 1, in the main process shown in FIG.
A case where one processing block becomes an infinite loop and the interrupt processing of FIG. 4 is normally processed every 1 msec will be described.

When the processing block MB2 in the main processing is in an infinite loop, the interrupt processing is operating normally, but the abnormality determination flag F set in the main processing is always 0, and the main processing is performed in the interrupt processing. The abnormality determination flag F set at this time is read, and a WD signal having a constant Lo level corresponding to the abnormality determination flag F is output from the WD signal output terminal of the microcomputer 1 to invert the WD signal. Therefore, the WD monitoring circuit 2 determines that there is an abnormality and outputs an abnormality determination signal.

Next, a case where the main process shown in FIG. 3 as the runaway example 2 is normally processed and one of the interrupt blocks of the interrupt process of FIG. 4 becomes an infinite loop will be described.

When the interrupt block 1 in the interrupt process becomes an infinite loop, the interrupt process is prohibited at the beginning of the interrupt process, so that the main process cannot be resumed and every 1 msec thereafter. Even if an interrupt processing request is received, interrupt processing is not performed because interrupts are disabled. From this, the WD signal is not newly output during the infinite loop, and the output state performed by the interrupt process immediately before the infinite loop occurs is held.
The signal becomes Hi or Lo level constant, the WD monitoring circuit 2 determines that there is an abnormality, and outputs an abnormality determination signal.

Next, as a runaway example 3, the main processing shown in FIG. 3 is normally processed, and the abnormality determination flag F set in the main processing in step S21 of the interrupt processing of FIG. 4 is read. A case where the process of outputting the signal of the level corresponding to the abnormality determination flag F from the WD signal output terminal of the microcomputer 1 becomes an infinite loop will be described.

In this case as well, since the interrupt prohibition process is performed at the beginning of the interrupt process as in Runaway Example 2 above,
Cannot return to main processing. Further, the WD signal output process is repeated in an indefinite cycle, but since the state of the abnormality determination flag F set in the main process does not change, W
The D signal becomes Hi or Lo level constant, and the WD monitoring circuit 2
Determines that there is an abnormality and outputs an abnormality determination signal.

Next, as a runaway example 4, a case will be described in which the main processing shown in FIG. 3 is normally processed, but the interrupt processing shown in FIG. 4 is no longer performed.

In this case, even if the main process operates in a normal cycle, the WD signal is not newly output, and the output state performed by the interrupt process immediately before the occurrence of the above abnormality is held, so that the WD signal becomes Hi or Lo level becomes constant and WD
The monitoring circuit 2 determines that there is an abnormality and outputs an abnormality determination signal.

Next, as a runaway example 5, a case will be described in which the main processing shown in FIG. 3 is normally processed, but an abnormal jump is made to the main processing during the interrupt processing shown in FIG.

In this case, since the main process is performed in a state where the interrupt is disabled in the interrupt process, the next interrupt process is not accepted, the WD signal becomes Hi or Lo level constant, and the WD monitoring circuit 2 is abnormal. Judges and outputs an abnormality determination signal.

Next, as a runaway example 6, a case will be described in which the main processing shown in FIG. 3 is normally processed, but the interrupt processing shown in FIG. 4 executed every 1 msec is executed with an abnormal frequency.

In this case, even if one interrupt process ends and the main process returns, the next interrupt request is accepted, so there is no time to perform the main process, and the WD signal is Hi as in the runaway example 3 described above. Alternatively, the Lo level becomes constant, and the WD monitoring circuit 2 determines that there is an abnormality and outputs an abnormality determination signal.

Next, a second embodiment showing the method of the present invention when the main process is a program processed in synchronization with the interrupt process will be described with reference to FIGS. 5 and 6.

5 and 6 are flow charts showing the second embodiment of the method of the present invention, and FIG. 5 is a flow chart showing the main processing of the program of the microcomputer.
FIG. 6 is a flowchart showing the interrupt processing of the program of the microcomputer. The main processing cycle operates at 8 msec, and the interrupt processing with the interrupt cycle of 1 msec is performed in synchronization with the main processing by using the 3-bit counter. It shows a program to be executed, which is a synchronous interrupt process.
Here, the same flows as those in the first embodiment are indicated by the same reference numerals, and only differences from the first embodiment will be described here.

5 is different from FIG. 3 in the case where a predetermined time relationship can be defined between the main process and the interrupt process, that is, in the processing time of the program, the first part of the main process, for example, When it is clear that the fourth interrupt is not processed earlier than the processing block MB1 and the processing block MB2, in the processing block MB1 and the processing block MB2, the abnormality determination flag F is set to 0 in steps S1a and S2a, and the processing is executed. Block MB3
In step S3a, the abnormality determination flag F is set to 1.

Further, similarly, the abnormality determination flag F is set to 1 at the beginning of the processing blocks after the processing block MB3, and step S30 is added to replace the time waiting block TB in FIG. 3 with steps S31 and step S31. The purpose is to execute the time waiting block TB1 consisting of S32.

At the beginning of the flow of the main processing in FIG. 5, step S30 is carried out. At step S30, it is checked whether or not the numerical value of the 3-bit counter is 000, and 000
If YES (YES), the process proceeds to step S1a of the processing block MB1. If the counter value is not 000 in step S30 (NO), step S30 is repeated.

When the processing of the processing block MBn is completed, the process proceeds to the time waiting block TB1. Waiting block TB1
Consists of step S31 and step S32. If the numerical value of the counter is 111 in step S31 (YES), the process proceeds to step S32, in which the abnormality determination flag F is set to 0, S30
Return to If the numerical value of the counter is not 111 in step S31 (NO), step S31 is repeated.

Next, the interrupt processing of FIG. 6 will be described.
In FIG. 6, first, interrupt is prohibited in step S20, the process proceeds to step S40, the 3-bit counter is incremented in step S40, and the process proceeds to step S41.

Next, in step S41, it is checked whether or not the numerical value of the 3-bit counter is 000, and if it is 000 (Y
ES), and proceeds to step S42. Next in step S42
Then, the abnormality determination flag F set at this time set in the main process is read, and a signal of a level corresponding to the abnormality determination flag F is output from the WD signal output terminal of the microcomputer 1.

Next, in step S43, the process of the predetermined interrupt block 1a is performed, and the process proceeds to step S24.

When the value of the 3-bit counter is not 000 in step S41 (NO), step S4
In step S44, it is checked whether or not the numerical value of the 3-bit counter is 001, and if it is 001 (YE
S), the process proceeds to step S45. The predetermined interrupt block 2a is processed in step S45, and the process proceeds to step S24.

When the numerical value of the 3-bit counter is not 001 in step S44 (NO), step S4
In step S46, it is checked whether or not the numerical value of the 3-bit counter is 010, and if it is 010 (YE
S), the process proceeds to step S47. The predetermined interrupt block 3a is processed in step S47, and the process proceeds to step S24.

Similarly, if the numerical value of the 3-bit counter is not 010 in step S46 (NO), the process proceeds to step S48, and it is checked in step S48 whether the numerical value of the 3-bit counter is 011 or not. If (YES), the process proceeds to step S49. The predetermined interrupt block 4a is processed in step S49, and then step S2
Go to 4.

If the numerical value of the 3-bit counter is not 011 in step S48 (NO), step S5
In step S50, it is checked whether or not the numerical value of the 3-bit counter is 100, and if it is 100 (YE
S), the process proceeds to step S51, and in step S51, the abnormality determination flag F set in the main process at this time
Is read and a signal of a level corresponding to the abnormality determination flag F is output from the WD signal output terminal of the microcomputer 1. As described above, since it is clear that the fourth interrupt is not processed earlier than the processing block MB1 and the processing block MB2, the WD signal output in step S51 is the same as the WD signal output in step S42. Output WD signals of opposite levels.

Then, the process proceeds to step S52 and step S5.
In step 2, the predetermined interrupt block 5a is processed, and the process proceeds to step S24.

When the numerical value of the 3-bit counter is not 100 in step S50 (NO), step S5
In step S53, it is checked whether or not the numerical value of the 3-bit counter is 101, and if it is 101 (YE
S), and proceeds to step S54. The predetermined interrupt block 6a is processed in step S54, and the process proceeds to step S24.

Similarly, when the numerical value of the 3-bit counter is not 101 in step S53 (NO), the process proceeds to step S55, and it is checked in step S55 whether the numerical value of the 3-bit counter is 110 or not. If (YES), the process proceeds to step S56. The predetermined interrupt block 7a is processed in step S56, and then step S2
Go to 4.

If the value of the 3-bit counter is not 110 in step S55 (NO), step S5
7, the predetermined interrupt block 8a in step S57.
Processing is performed, and the process proceeds to step S24.

In the second embodiment, if the processing block time is not fixed and the main processing time is fluid during development, the abnormality determination flag F is set to 1 in the main block MB1. , Waiting block TB1
When the abnormality determination flag F is set to 0, the WD signal can be output from the microcomputer 1 as a normal pulse without being affected by changes in each process of the main process.

In the second embodiment, the operation of the microcomputer against runaway is the same as in the first embodiment, and the description thereof is omitted here.

In the first and second embodiments, the WD
Although it suffices to detect only the non-pulse state as the monitoring circuit 2, the method of the present invention in the case where the WD monitoring circuit 2 capable of monitoring the time of the Hi and Lo levels of the pulsed WD signal can be installed will be described. A third embodiment will be described with reference to FIG.

FIG. 7 is a flow chart showing the third embodiment of the method of the present invention, and FIG. 7 is a flow chart showing the main processing of the program of the microcomputer, and an interrupt is made in each processing block of the main processing. A sub-block for prohibiting processing is set, and such processing is necessary, for example, when a variable used in interrupt processing is manipulated in the main processing, and processing methods known in various documents are set. Is. The flowchart showing the interrupt processing is the same as the flowchart shown in FIG. 4 of the first embodiment, and only the differences from the first embodiment will be described here.

In FIG. 7, the difference from the flowchart shown in FIG. 3 is that subblocks for prohibiting interrupts are set in each processing block, and processing block MB2A is used as an example. Processing block MB2
This will be explained in comparison with.

In the processing block MB2A, first in step S2A, the abnormality determination flag F is set in the same manner as in step S2a in the processing block MB2 in FIG. Then set it to 0.

Further, steps S2B to S2H in the processing block MB2A in FIG. 7 correspond to step S2b in FIG. 3, that is, the interrupt is prohibited in the processing 2 in step S2b, and the processing is performed in step S2.
The sub-block SB2A is formed from C to step S2G.

Then, the process proceeds to step S2B and step S2.
The predetermined process A is performed in 2B, the process proceeds to step S2C of the sub-block SB2A, and the process of inhibiting the interrupt is performed in step S2C.

Next, in step S2D, step S2
In 2D, the abnormality determination flag F is set to conflict with the flag set in step S2A. That is, in this embodiment, the abnormality determination flag F is set to 1 and the process proceeds to step S2E.

In step S2E, a predetermined process B is performed, and the process proceeds to step S2F. In step S2F, the abnormality determination flag F is set to the same state as in step S2A, that is,
Here, it is set to 0, and the process proceeds to step S2G.

In step S2G, the process of releasing the interrupt prohibition process and permitting the interrupt is performed, and the sub-block SB is executed.
After the processing of 2A is completed, the process proceeds to step S2H, a predetermined process C is performed in step S2H, one processing block ends, and the flow proceeds to the next processing block. The processing block having such a configuration is the processing block MB1A.
The process starts from the processing block MBnA and proceeds to the time waiting block TBA.

The time-waiting block TBA is composed of step S80. In step S80, it is checked whether or not a predetermined period of one cycle in the main process has elapsed, and the predetermined period of 1
If the period of time has elapsed (YES), the process returns to the process block MB1A at the beginning of the main process, and step S8 is performed.
If the predetermined one cycle time has not elapsed (NO) at 0, step S80 is repeated.

Here, the interrupt prohibition function in the sub-block of each processing block in FIG. 7 does not work normally,
When jumping to the interrupt processing in the interrupt prohibited section in the sub-block, the WD signal is inverted, and compared with the normal case, the pulse of the WD signal has a predetermined Hi level.
Level time or Lo level time becomes short and this is WD
When the WD monitoring circuit 2 detects the abnormality by the monitoring circuit 2 and outputs an abnormality determination signal, the runaway can be detected in the interrupt prohibited section in the sub-block.

The present invention is not limited to the above-mentioned first embodiment, second embodiment and third embodiment, and it is needless to say that various modifications can be considered.
Needless to say, it should be defined by the scope of the claims.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing a microcomputer system to which a method for outputting an abnormal signal of a microcomputer of the present invention is applied, which mainly includes a microcomputer and a WD signal monitoring circuit.

FIG. 2 is a diagram showing a circuit example of a WD signal monitoring circuit.

FIG. 3 is a flowchart showing main processing of a program of a microcomputer in the first embodiment of the method of the present invention.

FIG. 4 is a flowchart showing interrupt processing of a program of a microcomputer in the first embodiment of the method of the present invention.

FIG. 5 is a flowchart showing a main process of a microcomputer program in the second embodiment of the method of the present invention.

FIG. 6 is a flowchart showing interrupt processing of a program of a microcomputer in the second embodiment of the method of the present invention.

FIG. 7 is a flow chart showing main processing of a program of a microcomputer in the third embodiment of the method of the present invention.

[Explanation of symbols]

 1 Microcomputer 2 WD signal monitoring circuit F Abnormality judgment flag

Claims (6)

[Claims] 1. A microcomputer that interrupts a normal processing routine and executes the interrupt processing routine when an interrupt instruction is issued sets an abnormality determination flag for each predetermined block of a normal processing program, and The processing block resets the abnormality determination flag, reads the abnormality determination flag when the interrupt processing program is executed, and outputs the abnormality determination signal at the level corresponding to the abnormality determination flag, and outputs the signal. An abnormality signal output method for a microcomputer, wherein the presence or absence of abnormality is determined from the state of the level of the abnormality determination signal. 2. The method according to claim 1, wherein at the beginning of the interrupt processing program, the abnormality determination flag is read after the processing for inhibiting the interrupt, and the level corresponding to the abnormality determination flag is read. An abnormality signal output method for a microcomputer, characterized in that it outputs an abnormality determination signal. 3. The method according to claim 1, further comprising setting a sub-block in each of the processing blocks for prohibiting interrupts and performing processing, wherein the abnormality determination flag is set in the interrupt prohibition section. A method for outputting an abnormal signal of a microcomputer, characterized in that the setting is made in a state in which the setting conflicts with the setting. 4. The method according to claim 2, further comprising: in the case of performing a timed interrupt process in which the interrupt process interrupts at a predetermined cycle asynchronously with the main process program, the first half of the main process program is executed. The respective abnormality determination flags are set to be set or reset at the beginning of each processing block, and the above abnormality determination flags are set at the beginning of each processing block in the latter half of the main processing program. A micro that is characterized by setting a state that conflicts with the abnormality determination flag set in the processing block, canceling interrupt prohibition at the end of the interrupt processing program, and performing interrupt enable processing to return to main processing. Computer abnormal signal output method. 5. The method according to claim 1, further comprising: synchronous processing with a program for main processing other than interrupt processing, interrupting at a predetermined cycle, and performing synchronous interrupt processing, each processing in the program for main processing Set the above abnormality determination flags at the beginning of the block to set or reset respectively, and in the interrupt processing program, perform the processing of adding the counter after the processing of inhibiting the interrupt at the beginning, and execute the interrupt processing program. At the end of the above, the interrupt prohibition process is released, and the interrupt permission process for returning to the main process is performed. When the counter reaches at least one predetermined numerical value in the interrupt process program, the abnormality determination flag at that time is read and Outputs the abnormality judgment signal of the level corresponding to the abnormality judgment flag, and the above abnormality judgment signals alternate. So that the level is
An abnormality signal output method for a microcomputer, characterized in that the abnormality determination flag is set. 6. The method according to claim 3, further comprising setting the abnormality determination flag to be set or reset at the beginning of each processing block in the main processing program, and setting the abnormality determination flag in each processing block. The interrupt prohibition section is set to, and at the beginning of each interrupt prohibition section, the abnormality determination flag is set to a state that conflicts with the state set at the beginning of each processing block, and at the end of the interruption prohibition section, Set the abnormality determination flag to the same state as the state set at the beginning of each processing block, and in the interrupt processing program, after the process of prohibiting the interrupt at the beginning, set the same level as each abnormality determination flag. A special feature is that it outputs an error judgment signal, cancels the interrupt prohibition at the end of the interrupt processing program, and performs the interrupt permission processing to return to the main processing. A method of outputting an abnormal signal from a microcomputer.