JPH0870227A - Signal conditioner - Google Patents

Abstract

PURPOSE: To reduce number of wires connecting to an external device in the signal conditioner whose parameter such as gain or offset is set externally and whose output is of a serial digital form. CONSTITUTION: A clock signal presence discrimination section 4 informs the presence of a clock signal to a CPU 1 through an interrupt input section 2. The CPU processes the information and selects a selector 7 through an output section 3 based on the presence of the clock signal. When no clock signal is provided, an external input line is connected to a parameter data input output section 8 through an input buffer 5 and the selector 7. An output from the parameter data input output section 8 is given to an output line through the selector 7 and further an output buffer 6. When the clock signal is provided, the input line from the outside is given to a data sample command processing section 9 through the input buffer 5 and the selector 7. Data from a data output section 12 are given to the output line through the selector 7 and the output buffer 6.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal conditioner which takes in a plurality of analog signals, converts them into digital signals, and outputs them as serial data, and more particularly to a signal conditioner capable of externally setting parameters such as gain and offset.

[0002]

2. Description of the Related Art Conventionally, a signal conditioner of this type has both a parameter setting line (signal line) and a data output line, as in the circuit of Japanese Patent Laid-Open No. 56-107613. .

[0003]

In the conventional signal conditioner having both the parameter setting line and the data output line, the number of connecting lines with external devices is large and the configuration is complicated. Therefore, an object of the present invention is to provide a signal conditioner in which parameters such as gain and offset can be set from the outside and the number of wirings to an external device is small.

[0004]

In order to solve the above problems, the present invention provides the following means.

Mode determining means connected to the clock signal line and determining the operation mode when there is a clock signal input to the clock signal line and determining the setting mode when there is no clock signal input to the clock signal line And a parameter data input / output means for storing the input parameters such as gain and offset, and outputting the parameters, and a signal for performing amplification, offset change and other processing on the input analog signal according to the parameters. Processing means, command processing means for receiving a data sample command signal and other command signals for signal processing performed by the signal processing means, converting the signal into a signal compatible with the signal processing means, and supplying the signal to the signal processing means;
An input buffer for receiving a signal from an input line, an output buffer for receiving a signal to be sent to an output line, and one of the parameter data input / output unit or the command processing unit according to the mode determined by the mode determination unit. And a selector for connecting the output of the input buffer and connecting one of the output of the parameter data input / output means and the output of the signal processing means to the output buffer. The selector selects the parameter data input / output unit when the mode determined by the mode determination unit is the setting mode, and selects the parameter data input / output unit when the mode determined by the mode determination unit is the operation mode. A signal conditioner characterized by selecting a command processing means and a signal processing means.

The signal conditioner described above, wherein the signal input to the input line is parameter data or a data sample command.

The signal conditioner as described above or above, wherein the signal output from the output line is parameter data or an output signal of the signal processing means.

The signal processing means receives a plurality of analog signals and samples the plurality of analog signals at the timing of the data sample command; and an A / D converter that converts the output of the multiplexer into a digital signal. The signal conditioner as described in the above item 1 or 2, which comprises a data output unit that connects the output of the A / D converter to the selector.

A CPU which sets parameters such as gain and offset from the outside and controls the whole in a signal conditioner whose output is a serial digital format,
An interrupt input unit for notifying the CPU of an interrupt signal, an output unit for outputting data from the CPU, a clock signal presence / absence determination unit for determining the presence / absence of a clock signal, an input buffer for receiving a signal from an external device, and output of external device data Output buffer, selector for switching lines, parameter data input / output section for inputting / outputting parameter data such as gain and offset, data sample command processing section for processing commands for sampling analog signal data, multiplexer for switching analog signal, analog signal A signal conditioner comprising: an A / D converter for converting digital data into digital data; and a data output section for converting the output of the A / D converter into serial digital format data.

[0010]

In the present invention, whether the operation mode or the setting mode is determined by the presence or absence of the clock signal. Then, the input and output of the selector are selected according to the operation mode or the setting mode. In the operation mode, since a data command signal such as a data sample command is input to the input line, the input line is connected to the command processing means. In the setting mode, parameter data such as gain and offset is input to the input line, so the input line is connected to the parameter data input / output means. As described above, in the present invention, since the input lines are shared between the operation mode and the setting mode, the number of input lines is smaller than that in the conventional signal conditioner. The same applies to the output line.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be specifically described with reference to the drawings. FIG. 1 is a block circuit diagram showing one embodiment of the present invention. The clock signal presence / absence determining unit 4 determines whether a clock signal is input from the clock input line 201. The interrupt input unit 2 includes a clock signal presence / absence determining unit 4
The information on the presence or absence of the clock signal, which is the result of the determination from
Send to U1. CPU1 which has received the clock signal presence / absence information
Is the selector 7 through the output unit 3 depending on the presence or absence of a clock.
Switch. The connection of the selector 7 differs depending on whether or not there is a clock, and the operation of the embodiment of FIG. 1 in each case is as follows.

When there is no clock, the input line 301 from the outside is connected to the parameter data input section 8 through the input buffer 5 and the selector 7. The output from the parameter data input / output unit 8 is connected to the output line 401 through the selector 7 and the output buffer 6.

When there is a clock, the input line 301 from the outside passes through the input buffer 5, and further the selector 7
After passing through, the data sample command processing unit 9 is connected. In addition, the data from the data output unit 12 is the selector 7
Through the output buffer 6 and the output line 40
Connect to 1. When the data sample command processing unit 9 receives the data sample command signal from the selector 7,
The multiplexer 10 and the A / D converter 11 are controlled according to the data sample command signal. The multiplexer 10 receives the sample signal from the data sample command processing unit 9 and receives the analog input lines 101 to 104.
The analog signals from are sampled sequentially and sent to the A / D converter 11.

When there is no clock, the mode for setting parameters such as gain and offset of this signal conditioner is set, and the parameter data is input line 30.
1 is input, and when reading parameter data, it is output from the output line 401. When there is a clock, the signal conditioner sequentially takes in analog measurement data (data input from the analog input lines 101 to 104) by the multiplexer 10,
The A / D converter 11 converts the signal into a digital signal and outputs it from the data output section 12 in the operation mode. The data sample command signal is input from the input line 301 and the data is output from the output line 401. A clock signal from the outside is input from the clock input line 201.

In this embodiment, since the input line 301 and the output line 401 are shared in the setting mode and the operation mode, the number of wirings with an external device can be reduced as compared with the conventional signal conditioner.

[0016]

As described in detail above with reference to the embodiments, by adopting the present invention, by switching between the operation mode for outputting data and the setting mode for setting parameters depending on the presence or absence of a clock signal, both Since the same wiring is used in this mode, it is possible to reduce the number of wirings connected to the external device.

[Brief description of drawings]

FIG. 1 is a block circuit diagram showing an embodiment of the present invention.

[Explanation of symbols]

 1: CPU 2: Interrupt input unit 3: Output unit 4: Clock signal presence / absence determination unit 5: Input buffer 6: Output buffer 7: Selector 8: Parameter data input / output unit 9: Data sample command processing unit 10: Multiplexer 11: A / D converter 12: Data output unit 101: CH1 analog input line 102: CH2 analog input line 103: CH3 analog input line 104: CH4 analog input line 201: Clock input line 301: Input line 401: Output line A: Bus line

Claims (5)

[Claims] 1. A mode that is connected to a clock signal line and determines a clock signal input to the clock signal line as an operation mode, and determines a clock signal line not input to the clock signal line as a setting mode. Judgment means, parameter data input / output means for storing parameters such as input gain and offset, and outputting the parameters, and amplification, offset change and other processing according to the parameters to the input analog signal. Command processing means for performing, and a command processing means for receiving a data sample command signal and other command signals for signal processing performed by the signal processing means, converting the signal into a signal suitable for the signal processing means and supplying the signal to the signal processing means. And an input buffer that receives the signal from the input line and a signal that is sent to the output line An output buffer for receiving, in accordance with the determined mode in said mode determination means,
One of the parameter data input / output means or the command processing means is selected to connect the output of the input buffer, and one of the output of the parameter data input / output means or the output of the signal processing means is selected. And a selector connected to the output buffer, wherein the selector selects the parameter data input / output unit when the mode determined by the mode determination unit is the setting mode, A signal conditioner characterized by selecting the command processing means and the signal processing means when the mode judged by the judging means is the operation mode. 2. The signal conditioner according to claim 1, wherein the signal input to the input line is parameter data or a data sample command. 3. The signal conditioner according to claim 1, wherein the signal output from the output line is parameter data or an output signal of the signal processing means. 4. A multiplexer, wherein the signal processing means receives a plurality of analog signals and samples the plurality of analog signals at the timing of the data sample command, and an A / D converter for converting an output of the multiplexer into a digital signal. And a data output section for connecting the output of the A / D converter to the selector, the signal conditioner according to claim 1, 2, or 3. 5. A CPU, C for controlling the whole in a signal conditioner of which output is serial digital format by setting parameters such as gain and offset from the outside.
An interrupt input unit that notifies an interrupt signal to the PU, an output unit that outputs data from the CPU, a clock signal presence / absence determination unit that determines the presence / absence of a clock signal, an input buffer that receives a signal from an external device, data to the external device , An output buffer that outputs a line, a selector that switches lines, a parameter data input / output unit that inputs and outputs parameter data such as gain and offset, a data sample command processing unit that processes a command that samples analog signal data, a multiplexer that switches an analog signal, A signal conditioner comprising an A / D converter for converting an analog signal into digital data, and a data output section for converting an A / D converter output into serial digital format data.