JPH087559B2 - Video signal generation circuit - Google Patents

Description

The present invention relates to a video signal generation circuit for displaying a video signal and a computer image on a TV screen in a superimpose manner, and more particularly to a computer image display circuit. For improving the horizontal and vertical driving signals to the horizontal and vertical synchronizing signals of the video signal.

<Prior Art> Generally, in a video signal generation circuit that displays a video signal and a computer image on a TV screen in a superimpose manner, horizontal and vertical drive signals for displaying the computer image are the horizontal and vertical drive signals of the video signal. If it is not synchronized with each vertical synchronizing signal, the display screen of the computer image is disturbed, so that it is necessary to synchronize the horizontal and vertical drive signals of the computer with the video signal.

Conventionally, there is a video signal generating circuit having a circuit for such synchronization as shown in FIG.
In the figure, 1 is a video signal to a horizontal synchronization signal HSYNC.
A sync separation circuit 2 for separating and extracting a vertical sync signal VSYNC and a vertical sync signal VSYNC is an oscillator for generating a clock pulse having a constant oscillation frequency, and the oscillation frequency is a horizontal and vertical drive signal HD generated from a CRT controller 5 described later. , VD is preset so that the frequency of VD is slightly higher than the frequencies of the horizontal and horizontal synchronizing signals HSYNC and VSYNC of the video signal.
Reference numeral 3 denotes an image memory for storing image data created by a computer (CPU), and 4 denotes an image based on the computer image signal and the video signal stored in the image memory 3.
CRT display, 5 is a CRT controller for generating horizontal and vertical drive signals HD and VD for displaying the image data stored in the image memory 3 on the CRT display, 6 is a switch between a video signal and a computer image signal A switching circuit 7'for outputting the horizontal and vertical driving signals HD and VD output from the CRT controller 5 to the horizontal and vertical synchronizing signals HSYNC and VSYNC of the video signal. . Then, the synchronizing circuit 7'includes horizontal and vertical synchronizing signals HSYNC and VSYNC which are synchronously separated by the synchronous separating circuit 1, clock pulses CLKs from the oscillator 2, and horizontal and vertical driving signals HD output from the CRT controller 5. While VD is input respectively, clock pulse CL of oscillator 2 is generated based on these input signals.
Clock pulse CLKc that processed Ks is CRT controller 5
Is output as the operation signal.

FIG. 4 is a circuit configuration diagram showing the details of the synchronization circuit 7 '. The synchronization circuit 7'includes a horizontal synchronization circuit (horizontal D flip-flop in this example) 8h for outputting a horizontal synchronization control signal Ph based on the horizontal synchronization signal HSYNC and the horizontal drive signal HD. Sync signal VS
A vertical synchronization circuit (vertical D flip-flop in this example) 8v that outputs a control signal Pv for vertical synchronization based on YNC and the vertical drive signal VD, and outputs from both synchronization circuits 8h and 8v. A first AND gate 10 for inputting both control signals Ph and Pv to generate a control signal Phv for horizontal and vertical synchronization, and an oscillator 2 based on a control signal Phv output from the first AND gate 10. Gate circuit (second AND gate in this example) 11 for opening and closing the gate for clock pulse CLKs, and both D flip-flops
It is composed of an inverter that inverts the levels of horizontal and vertical drive signals HD and VD applied to the clock input terminals of 8h and 8v.

Next, the cycle adjusting operation of the cycle adjusting circuit 7'shown in FIG. 4, particularly the operation when synchronizing the horizontal drive signal HD with the horizontal drive signal HSYNC, will be described with reference to the timing chart shown in FIG. .

At the present time, during the image display period in which the computer image data is read from the image memory 3, the control signal Pv which is the inverted output of the vertical D flip-flop 8v is at the high level, and therefore the first AND gate 10 Is open.

On the other hand, in this state, when the horizontal drive signal HD is not synchronized with the horizontal sync signal HSYNC due to the influence of disturbance or the like, as shown by the reference numeral in FIG.
The down edge of HSYNC precedes the down edge of the horizontal drive signal HD. In this case, since the horizontal D flip-flop 8h has already been cleared by the down edge of the horizontal synchronization signal HSYNC, even if the horizontal drive signal HD is next applied as a clock pulse, the inverted output of the horizontal D flip-flop 8h (= The level of Ph) does not change and remains at the high level. Therefore, the output Phv of the first AND gate 10 also becomes high level, and the clock pulse CLKs from the oscillator 2 is applied to the CRT controller 5 via the second AND gate 11. With this clock pulse CLKc,
The horizontal drive signal HD is generated from the CRT controller 5, and as described above, the pulse cycle of this horizontal drive signal HD
Since T ₁ is preset so as to be slightly shorter than the pulse period T ₀ of the horizontal synchronizing signal HSYNC of the video signal,
As shown in the timing after the symbols in the figure, the phase of the horizontal drive signal HD gradually approaches the horizontal sync signal HSYNC, and the down edge of the horizontal drive signal HD is the horizontal sync signal.
It comes before the down edge of HSYNC. Then, in the horizontal D flip-flop 8h, the level of the control signal Ph, which is the inverted output of the horizontal D flip-flop 8h, changes to the low level because the horizontal drive signal HD is added as a clock pulse in the clear release state. Then, the horizontal D flip-flop 8h outputs the horizontal synchronization signal HSYNC.
The inverted output becomes high level because it is cleared by the down edge of. That is, the output Phv of the first AND gate 10 is at the low level only during the period indicated by ΔT ″, Δt ′, Δt in FIG. 5, so that the clock pulse CLKc is supplied to the CRT controller 5 only during the Δt ″, Δt ′, Δt. Is stopped from joining. If the clock pulse CLKc is not input, the CRT controller 5 stops its operation only during that period, and as a result, the stop period Δt ″, Δt ′, Δ
Horizontal drive signal HD generated by CRT controller 5 for t
The output timing of (1) is substantially extended, and the horizontal drive signal HD is finally synchronized with the horizontal synchronization signal HSYNC (timing after the reference numeral in FIG. 5). And in the steady state after synchronization once,
T ₀ = T ₁ + Δt.

By the way, in the conventional CRT controller 5, as shown in FIG. 6A, the period T ₃₁ ′ of the high level of the vertical drive signal VD is variable and the period T ₂₁ of the high level of the vertical synchronizing signal VSYNC is T _{21 ′.} While there are some models that can be adjusted so that they are much shorter, the vertical sync signal VD
There is a model in which the high-level pulse period T ₃₁ ″ is fixed and the period T ₃₁ ″ is close to the high-level period T ₂₁ of the vertical synchronization signal VSYNC.

In the former model, when the vertical drive signal VD is not synchronized with the vertical drive signal VSYNC due to the influence of disturbance, the down edge of the vertical drive signal VSYNC precedes the down edge of the vertical drive signal VD. In this case, the level of the inverted output (= Pv) of the vertical D flip-flop 8v is maintained at the high level, just as in the case of the horizontal synchronization. Therefore, the output of the horizontal D flip-flop 8h is at the high level. Then, the clock pulse CLKc is applied to the CRT controller 5 via the second AND gate 11 every time. With this clock pulse CLKc,
The vertical drive signal VD is generated from the CRT controller 5, but as described above, the pulse period of the vertical drive signal VD is preset to be slightly shorter than the pulse period T ₂ of the vertical synchronizing signal VSYNC of the video signal. Therefore, the phase of the vertical drive signal VD gradually approaches the vertical sync signal VSYNC, and the down edge of the vertical drive signal VD comes before the down edge of the vertical sync signal VSYNC.
Then, as shown in FIG. 6A, when the down edge of the vertical drive signal VD precedes the down edge of the vertical synchronizing signal VSYNC, the vertical D flip-flop 8v
Since the output Pv of the inverting output terminal of is at a low level for the period indicated by ΔT ₂ ′ in FIG. 6A, the addition of the clock pulse CLKc to the CRT controller 5 is stopped for the period of ΔT ₂ ′. . In response, CRT controller 5
Stops the operation, resulting in clock pulse CL
The output timing of the vertical drive signal VD generated by the CRT controller 5 is substantially extended only during the Kc stop period ΔT ₂ ′, and thereafter, the vertical drive signal VD is synchronized with the vertical synchronization signal VSYNC. .

<Problems to be Solved by the Invention> However, the high-level pulse period of the vertical synchronization signal VD
T ₃₁ ″ is fixed, and the difference between the period T ₃₁ ″ and the high level period T ₂₁ of the vertical synchronizing signal VSYNC (= T ₂₁ −T
_{In the} latter model in which ₃₁ ″) is shorter than one cycle T ₀ of the horizontal drive signal HSYNC, the following problems occur.

That is, as shown in FIG. 6, when the horizontal cycle signal HSYNC and the horizontal drive signal VD happen to be synchronized from the rising edge of the vertical drive signal VD, the vertical drive signal VD
After the horizontal drive signal HD arrives just before the down edge of
By the time the next horizontal drive signal HD arrives, first the down edge of the vertical drive signal VD is followed by the vertical sync signal VSYN.
When the down edge of C comes, the vertical D flip-flop 8
The output Pv of the inverted output terminal of v is ΔT ₂ ″ in FIG. 6 (b).
Only a low level period denoted by, therefore, control signal Phv output from the first AND gate 10 also becomes similarly low level for a period of [Delta] T ₂ "clock pulses CLKc
Is stopped from joining the CRT controller 5. This phenomenon means that the clock pulse CLKC input to the CRT controller 5 is stopped twice between the arrival of one horizontal drive signal HD and the arrival of the next horizontal drive signal HD. Therefore, the output timing of the horizontal drive signal HD generated by the CRT controller 5 is extended more than one cycle (= T ₁ + Δt) when the cycles are matched. As a result, as described above, a state in which the down edge of the horizontal synchronizing signal HSYNC precedes the down edge of the horizontal drive signal HD as shown by the reference numeral in FIG. 5 is outputted from the first AND gate 10. Control signal Phv
No low level occurs and the horizontal drive signal HD is not synchronized with the horizontal sync signal HSYNC. Horizontal drive signal HD
Since the pulse cycle T ₁ of the video signal is slightly shorter than the pulse cycle T ₀ of the horizontal sync signal HSYNC of the video signal,
Although the horizontal drive signal HD becomes synchronized with HSYNC,
In FIG. 6, the state of being out of synchronization continues during the period indicated by the symbol Tc, and the display screen is disturbed. As shown in FIG. 6A, if the period ΔT ₂ ′ from the down edge of the vertical drive signal VD to the down edge of the vertical sync signal VSYNC is longer than one cycle T ₁ of the horizontal sync signal HSYNC, Vertical drive signal V
The section from the horizontal drive signal HD that arrives immediately before the down edge of D to the down edge of the vertical drive signal VD, and the section from immediately after the down edge of the vertical sync signal VSYNC to the horizontal drive signal VD that occurs next time. Sum is horizontal sync signal HSYN
Since one cycle of C is T ₀ (= T ₁ + Δt), the horizontal drive signal HD is not out of synchronization.

Further, as shown in FIG. 6 (c), the vertical drive signal VD
Is out of sync and the down edge of the vertical sync signal VSYNC precedes the down edge of the vertical drive signal VD, the low level period ΔT ₂ ′ as shown in FIG. Since it does not exist and the level of the inverted output (= Pv) of the vertical D flip-flop 8v is maintained at the high level, the clock pulse CLKc is output every time the output of the horizontal D flip-flop 8h becomes the high level. Is added to the CRT controller 5 via the second AND gate 11. Then, the vertical drive signal VD is output from the CRT controller 5 by the clock pulse CLKc, but since the vertical drive signal VD is generated by dividing the horizontal drive signal HD, it is once converted into the horizontal synchronization signal HSYNC. When the horizontal drive signal HD is synchronized, the vertical drive drive signal VD is generated every time the horizontal drive signal HD is generated by a predetermined number of pulses. Therefore, the down edge of the vertical drive signal VD does not come earlier than the down edge of the vertical synchronization signal VSYNC, and thereafter, the state shown in FIG. 6 (c) is continued and the cycle of the vertical drive signal VD is deviated. Will remain.

<Means for Solving the Problems> The present invention has been made in view of such circumstances, and it is impossible to vary the high-level pulse period of the vertical synchronizing signal, and moreover, the vertical driving signal Even in a model in which the difference between the high level period and the high level period of the vertical sync signal is shorter than one cycle of the horizontal drive signal, the horizontal and vertical sync signals can be synchronized with the horizontal and vertical drive signals. To do so.

Therefore, the present invention provides a horizontal synchronization circuit that outputs a control signal for horizontal synchronization based on a horizontal synchronization signal and a horizontal drive signal, and a vertical synchronization circuit based on a vertical synchronization signal and a vertical drive signal. A vertical synchronization circuit that outputs a control signal, an AND gate that inputs the control signals output from both synchronization circuits together to generate a control signal for horizontal and vertical synchronization, and an output from this AND gate The following configuration is adopted in the video signal generation circuit provided with the synchronization circuit having the gate circuit for opening and closing the gate for the clock pulse from the oscillator based on the control signal.

That is, in the present invention, an OR gate is provided between the horizontal synchronization circuit and the AND gate, and one input portion of this OR gate is connected to the horizontal synchronization circuit output portion,
The other input part of the OR gate is used as a vertical synchronizing signal input part, and the output part of the OR gate is connected to one input part of the AND gate.

<Operation> In the above configuration, since the vertical synchronizing signal VSYNC is applied to the first AND gate via the OR gate during the high level period of the vertical synchronizing signal VSYNC, even if the output of the horizontal synchronizing circuit changes, The output of the first AND gate does not change and the high level is maintained. That is, the output of the synchronization circuit is masked by the output of the OR gate. Therefore, in the high level state of the vertical drive signal VD
Since the clock pulse is not intermittently input to the CRT controller and is not stopped midway, the high level period of the vertical drive signal VD is higher than that of the vertical sync signal VSYNC by 1 of the horizontal sync signal HSYNC. It becomes shorter than the cycle by T ₀ or more. As a result, the input of the clock pulse to the CRT controller is stopped for a period ΔT ₂ from the arrival of the down edge of the vertical drive signal VD to the arrival of the down edge of the vertical synchronization signal VSYNC. Therefore, the horizontal drive signal becomes synchronized with the horizontal synchronization signal, and the horizontal drive signal also becomes synchronized with the vertical synchronization signal.

<Embodiment> FIG. 1 is a block diagram of a synchronizing circuit portion of a video signal generating circuit, and the portions corresponding to the conventional example shown in FIG.

In the synchronizing circuit 7 in this embodiment, the horizontal synchronizing circuit (horizontal D flip-flop) 8b and the first
An OR gate 13 is provided between the AND gate 10 and one input part of this OR gate 13 is connected to the inverting output terminal of the horizontal synchronization circuit 8h, and the other input part of the OR gate 13 is an input part of the vertical synchronization signal VSYNC. The output part of the OR gate 13 is connected to one input part of the first AND gate 10, and the other structure is similar to that of the conventional example shown in FIG.

In the above configuration, as shown in the timing chart of FIG. 2, when the vertical synchronizing signal VSYNC is the vertical blanking period T ₂₁ in the high level, the output signal from the inverting output terminal of the D flip-flop 8v vertical Pv is at the high level until the down edge of the vertical drive signal VD arrives, and therefore the first AND gate 10 is open. Moreover, the high level vertical synchronizing signal VSYNC is applied to the first AND gate 10 via the OR gate 13. Therefore, until the down edge of the vertical drive signal VD arrives, even if the output signal Ph of the horizontal D flip-flop 8h changes, the output Phv of the first AND gate 10 does not change and remains high level. To be done. That is, the output Ph of the horizontal D flip-flop 8h is masked by the vertical synchronizing signal VSYNC applied to the OR gate 13. Therefore, the clock pulse CLKc is not continuously input to the CRT controller 5 and is not stopped halfway until the down edge of the vertical drive signal VD arrives. That is, since the period ΔT for synchronizing the horizontal drive signal HD is omitted during the vertical blanking period T ₂₁ , the high level period T ₃₁ of the vertical drive signal VD during the period T ₂₁ is vertical synchronization. Signal VSYNC
It becomes shorter than the high level period T ₂₁ by one cycle T ₀ or more of the horizontal synchronizing signal HSYNC. That is, T ₂₁ −T ₃₁ = ΔT ₂ > T ₀ .
Further, the high-level period T ₂₁ of the vertical synchronizing signal VSYNC, on the relationship between the period ΔT for synchronization in is omitted, although the horizontal drive signal HD not synchronized with the horizontal synchronizing signal HSYNC, the period T ₂₁ Since it is a vertical blanking period, it contributes to the display of an image, so there is no problem.

Then, when the down edge of the vertical drive signal VD arrives, the signal Pv from the inverting output terminal of the vertical D flip-flop 8v becomes low level, so the first AND gate 10
Output of the first AND gate 10 becomes high level when the down edge of the vertical synchronizing signal VSYNC subsequently comes and the signal Pv from the inverting output terminal of the vertical D flip-flop 8v becomes high level. Also goes high. Therefore, the period ΔT ₂ from the down edge of the vertical drive signal VD to the down edge of the vertical sync signal VSYNC
At (> T ₀ ), the input of the clock pulse to the CRT controller 5 is stopped. Therefore, the horizontal driving signal HD in the image display period T _22, except for the vertical blanking period T ₂₁ is a horizontal synchronizing signal HSYNC
Will be synchronized with. Moreover, since the control signal Phv output from the first AND gate 10 has a low level period ΔT ₂ of one cycle T ₀ or more of the horizontal synchronizing signal HSYNC, the vertical driving signal VD is the vertical synchronizing signal VSYNC. Even if the synchronization is lost from, the phase of the vertical drive signal VD gradually approaches the vertical sync signal VSYNC, the down edge of the vertical drive signal VD leads the down edge of the vertical sync signal VSYNC, and finally Horizontal drive signal VD is vertical sync signal VSYN
It will be synchronized with C.

<Advantages of the Invention> According to the present invention, the high-level pulse period of the vertical synchronization signal cannot be varied, and moreover, the difference between the high-level period of the vertical drive signal and the high-level period of the vertical synchronization signal is high. Even in a model in which the horizontal drive signal is shorter than one cycle, excellent effects such as the fact that the horizontal and vertical drive signals can be reliably synchronized with the horizontal and vertical drive signals are exhibited.

[Brief description of drawings]

1 and 2 show an embodiment of the present invention. FIG. 1 is a block diagram of a synchronization circuit portion of a video signal generation circuit, and FIG. 2 is a description of a synchronization operation by the circuit of FIG. It is a timing chart for doing. FIGS. 3 to 6 show a conventional example. FIG. 3 is a block diagram showing the overall configuration of a video signal generating circuit, FIG. 4 is a configuration diagram of a synchronizing circuit portion, and FIG. 5 is a horizontal synchronizing signal. FIG. 6 (a) is a timing chart for explaining the operation when the horizontal drive signal is synchronized with the vertical drive signal when the vertical drive signal is set to be sufficiently shorter than the high level period of the vertical sync signal. 6B is a timing chart of the synchronization state, FIG. 6B is a timing chart of the synchronization state when the high level period of the vertical synchronization signal is close to the high level period of the vertical synchronization signal, and FIG. 6C is the vertical synchronization. 7 is a timing chart in an asynchronous state when the high level period of the vertical synchronization signal is close to the high level period of the signal. 1 ... Synchronous separation circuit, 2 ... Oscillator, 3 ... Image memory, 4 ... CRT display, 5 ... CRT controller,
7 ... Synchronization circuit, 8h ... Horizontal synchronization circuit (horizontal D flip-flop), 8v ... Vertical synchronization circuit (vertical D flip-flop), 10 ... First AND gate, 11 ... Gate circuit (second AND gate), 13
…… Or gate.

Claims (1)

[Claims] 1. A sync separation circuit for separating a horizontal sync signal and a vertical sync signal from a video signal and taking them out, an oscillator for generating a clock pulse having a constant oscillation frequency, and an image memory for storing image data produced by a computer. And a CRT display for displaying a computer image stored in this image memory and an image based on a video signal, and CRT image data based on a clock pulse from the oscillator.
A CRT controller that generates horizontal and vertical drive signals for display on a display, and synchronization for adjusting the horizontal and vertical drive signals output from the CRT controller to the horizontal and vertical sync signals of the video signal. A synchronization circuit, wherein the synchronization circuit outputs a horizontal synchronization control signal based on a horizontal synchronization signal and a horizontal drive signal, and a horizontal synchronization circuit based on the vertical synchronization signal and the vertical drive signal. And a vertical synchronization circuit that outputs a control signal for vertical synchronization, and an AND gate that inputs the control signals output from the synchronization circuits to generate a control signal for horizontal and vertical synchronization. , A gate that opens and closes a gate for a clock pulse from the oscillator based on a control signal output from the AND gate. In the video signal generation circuit having a video circuit, an OR gate is provided between the horizontal synchronization circuit and the AND gate, one input part of the OR gate is connected to the output of the horizontal synchronization circuit, and the other of the OR gates is connected. A video signal generation circuit characterized in that an input section is used as a vertical synchronization signal input section, and an output section of an OR gate is connected to one input section of the AND gate.