JPH087593A - Semiconductor integrated circuit device and method of manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] Burn-in defects can be repaired, and the repair rate is improved to improve the yield and keep the manufacturing cost low. A first redundancy means for functionally replacing a defective memory cell in a normal memory cell array generated in a wafer process, and a functional redundant replacement of a defective memory cell in a normal memory cell array generated during a burn-in test. And the second redundant means is used to perform the first laser trimming using the first redundant means after the wafer process, and the second laser trimming is performed using the second redundant means after the burn-in test. . [Effects] Burn-in defects can be relieved, the processing and material costs are not wasted as the relief rate is improved, and the manufacturing cost can be kept low.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a redundancy function, and more particularly to a semiconductor integrated circuit device and a semiconductor integrated circuit device which replace a defective bit in a burn-in test with a spare bit by the redundancy function after a burn-in test. The present invention relates to a manufacturing method of.

[0002]

2. Description of the Related Art In recent years, in a semiconductor integrated circuit device, a normal memory cell and a spare memory cell are provided in advance in the same integrated circuit device, and when a defect occurs in the normal memory cell, the defective memory Those having a redundant function of replacing a cell with a spare memory cell for use have been developed. FIG. 36 shows, for example, JP-A-59.
72 is a block diagram showing a memory configuration of a semiconductor integrated circuit device having a conventional redundant function shown in FIG. As shown, two decoders 102 and 103 are electrically connected to the address buffer 101 to which the address signal is supplied. The output from the address buffer 101 is supplied to the two decoders 102 and 103 in parallel. The decoder 102 is a regular memory cell array 1
The memory cell in the memory cell 04 is selected, and one or more memory cells are selected by supplying the decoder output to the regular memory cell array 104, and then the data is stored in the selected memory cell. Be read or read. The other decoder 1
Reference numeral 03 is for selecting a memory cell in the spare memory cell array 105 when a defective memory cell occurs in the normal memory cell array 104, and the decoder output is supplied to the spare memory cell array 105. Selects that memory cell. The decoding operation of the decoder 102 is controlled by the output of the other decoder 103.

In the decoder 103, when a defective memory exists in the normal memory cell array 104, when the address signal corresponding to the defective cell is supplied to the address buffer 101, the decoder 103 stores in the spare memory cell array 105. It is programmed to select a memory cell. Note that this program selectively fuses a fuse made of aluminum or polycrystalline silicon provided inside the decoder 103 by laser irradiation, or selectively selects polycrystalline silicon in a high resistance state in the initial state. Laser annealing to reduce the resistance (this step is generally called a laser trimming step). Therefore, if a defective cell exists in the normal memory cell array 104, the memory cell in the spare memory cell array 105 is selected by the output of the decoder 103, and the decoding operation of the decoder 102 is stopped by the output of the decoder 103. As a result, the defective cell in the normal memory cell array 104 has been replaced with the good memory cell in the spare memory cell array 105. In that sense, the memory cell can be substantially a good product. .

Conventionally, a laser trimming process for replacing a defective memory cell of a semiconductor integrated circuit device with a redundancy function as described above with a spare memory cell has been performed before a burn-in test. The burn-in test is a test in which a semiconductor integrated circuit device (hereinafter referred to as an IC chip) is operated for a predetermined time by applying temperature and electrical stress. The purpose is to prevent early failures. FIG.
FIG. 7 shows a series of flow of the conventional IC chip test process from the completion of the wafer process (WP) (a state in which an IC is formed on the wafer). In the figure, step S
1 is the completion of the wafer process (WP), and step S2
Is a laser trimming process which is a process of judging whether the IC on the wafer is good or bad, and replacing the defective defective memory cell with a spare memory cell if the defective product is defective. The laser trimming process will be briefly described. First, a test pin (not shown) is applied to each IC chip on the wafer, a very simple operation is performed on the IC chip, and a test is performed to determine whether the memory cells of the IC chip are good or bad (step S2a). If defective, spare memory cell 105 (see FIG. 3) is formed by laser trimming as described above.
6)) (step S2b), and then, similarly to step S2a, a test pin is applied to the IC chip to confirm whether it is good or bad (step 2c). Step S3 is a step of applying a protective film for protecting the IC chip such as a passivation layer from dust and moisture, and step S4 is a wafer test (WT) step of performing a test in a wafer state. In the wafer test process of step S4, in order to perform the process of step S5, nothing is done to the non-defective product, and ink is definitively applied to the defective product. Step S5 is an assembly process, in which the IC chip judged as non-defective in the process of Step S4 is cut,
Mold with resin and process the leads to make them ready for shipping. Step S6 is a test for discriminating, for each access item, the IC chip that has completed the process of step S5. This test measures the access speed of each IC chip, discards those with an access speed that does not meet the product design standards as defective, and discards the others with multiple access such as fast, normal, and slow. It is to be sorted into items. Step S7 is a step of performing a burn-in test, and step S8 is a step (post-test) of performing an operation test of each IC chip in a low temperature state and a high temperature state for each access item selected in step S6.

In the above test process flow,
After the completion of the wafer process (step S1), in the process of step S2, those judged to be defective are discarded, and those judged to be non-defective proceed to the process of step S3 to apply a protective film. In the step S4, the wafer with the protective film is tested, and the defective IC in the wafer is tested.
Ink is attached to the chip to indicate "bad". Good IC
The chip proceeds to step S5, is molded with resin, and is lead processed. The processed one is step S
Acceptance test is performed at 6, and each access item is sorted, and if there is no corresponding access, it is discarded. Next, a burn-in test is performed in step S7, and a low-temperature / high-temperature selection test is performed in the post-test of step S8 to discard defectives and ship good products.

[0006]

In the conventional test flow, since the laser trimming step is performed only once before the burn-in test, a defective memory for a defective one in the burn-in test (step S7). There was no remedy for the cell, and the previous processing and material costs for that product were wasted. Further, there is a problem that the production efficiency is poor due to the low repair rate of the IC chip, and the cost is increased accordingly.

Further, in the conventional semiconductor integrated circuit device, for example, as shown in FIG. 38 which is an enlarged view of FIG. 36, of the normal rows 102a connecting the normal memory cells 104 and the decoder 102, If there is a normal row 102aa having a defective bit,
The spare memory cell 10 is formed by the laser trimming process.
Since one of the redundant rows 103a connected to No. 5 is replaced with the redundant row 103aa, in the burn-in test (step S7), the replaced redundant row 103aa as shown in the waveform at the burn-in test in FIG.
Is subjected to stress such as voltage at the time of burn-in test, but the unused redundant row 103a not used for replacement is used.
No stress is applied to the (unsubstituted redundant row) during the burn-in test. The purpose of the burn-in test is to apply stress to accelerate the occurrence of failures and eliminate early failures. However, the unused redundant row 103a and the unused spare memory cells 105 are not stressed during the burn-in test. Since the initial failure has not been removed since it does not take place, even if the IC chip judged to be defective in the burn-in test is replaced by laser trimming after the burn-in test and replaced, the IC chip that has been rescued Had many early failures, and as a result, he was not rescued.

The present invention has been made in order to solve the above problems and has a redundancy function capable of performing a laser trimming process twice, and makes it possible to remedy a defect in a burn-in test. A semiconductor integrated circuit device capable of preventing loss of processing and material costs by performing molding and lead processing thereafter, improving yield by improving a relief rate of IC chips, and suppressing manufacturing cost low, and a semiconductor The purpose is to obtain a test method for an integrated circuit device.

[0009]

In view of the above object, the invention of claim 1 is a normal memory cell array having a plurality of memory cells, and a memory cell in the normal memory cell array electrically connected to the normal memory cell array. Address means for outputting an address signal for designating an address of the normal memory cell array and a first redundancy circuit for electrically connecting the address means in parallel to the normal memory cell array and replacing a defective memory cell in the normal memory cell array. Means, the first redundancy means and the address means are electrically connected, the address of the defective memory cell in the normal memory cell array is preprogrammed, and an address signal matching the address of the defective memory cell is input from the address means. When
First control means for controlling the defective memory cell to be functionally replaced with the first redundant means, and electrically connected to the address means in parallel with the normal memory cell array and the first redundant means, Second redundant means for replacing a defective memory cell in the memory cell array, and electrically connected to the second redundant means and the address means, the address of the defective memory cell in the normal memory cell array is programmed in advance, A semiconductor integrated circuit having a second control means for controlling the defective memory cell to be functionally replaced with the second redundant means when an address signal matching the address of the defective memory cell is input from the means. It is a device.

According to the second aspect of the present invention, the first redundancy means comprises a spare memory cell array having a plurality of spare memory cells for replacing defective memory cells in the normal memory cell array, and a second redundancy means. A semiconductor integrated circuit device can be obtained in which the redundancy means is composed of a spare memory cell array having a plurality of spare memory cells for replacing defective memory cells in the normal memory cell array.

According to the third aspect of the present invention, the first redundancy means comprises a spare memory cell array having a plurality of spare memory cells for replacing defective memory cells in the normal memory cell array, and a second redundancy means. The redundancy means is composed of a spare memory cell circuit having a plurality of spare memory cells for replacing defective memory cells in the normal memory cell array in bit units, and the second control means is electrically connected to the address means. And a switching control circuit in which an address of a defective memory cell in the normal memory cell array is programmed in advance, a first switching circuit electrically connected to the normal memory cell and the switching control circuit, and a spare memory cell circuit. A second switching circuit electrically connected to the control circuit, wherein the switching control circuit controls the first switching circuit and the second switching circuit. The semiconductor integrated circuit device can be obtained.

According to a fourth aspect of the present invention, a normal memory cell array having a plurality of memory cells, and an address signal electrically connected to the normal memory cell array and designating an address of a memory cell in the normal memory cell array are output. Address means and first redundancy means electrically connected to the address means in parallel to the normal memory cell array and for replacing a defective memory cell in the normal memory cell array; first redundancy means and address means; Is electrically connected to, the address of the defective memory cell in the normal memory cell array is programmed, and when an address signal matching the address of the defective memory cell is input from the address means,
First control means for controlling so that the defective memory cell is functionally replaced by the first redundancy means, and electrically connected to the address means in parallel with the normal memory cell array and the first redundancy means. A second redundancy means for replacing a defective memory cell in the normal memory cell array, and electrically connected to the second redundancy means for programming the address of the defective memory cell in the normal memory cell array, A semiconductor integrated circuit including second control means for controlling the defective memory cell to be functionally replaced with the second redundant means when an address signal matching the address of the defective memory cell is input. The step of preparing the device,
The first control means includes a first laser trimming step for programming an address of a defective memory cell in the normal memory cell array, a burn-in test step for burn-in test of the semiconductor integrated circuit device, and a burn-in test for memory cell array generated in the burn-in test. And a second laser trimming step of programming the address of the defective memory cell in the second control means.

According to the fifth aspect of the present invention, in the burn-in test step, a probe card having a plurality of probes for electrically contacting the semiconductor integrated circuit device and supplying a burn-in test signal is prepared. A burn-in test is performed by simultaneously supplying a burn-in test signal to a plurality of semiconductor integrated circuits by the probe of the card.

According to the invention of claim 6, a switching means for switching whether or not the burn-in test signal is supplied is prepared, and the burn-in test signal is supplied only to the semiconductor integrated circuit device selected in advance. Do the test.

According to the invention of claim 7, the probe is provided with a switching means for switching whether or not to supply the burn-in test signal.

According to the eighth aspect of the present invention, the semiconductor integrated circuit device is provided with a switching means for switching whether or not to supply the burn-in test signal.

According to the ninth aspect of the invention, in the burn-in test step, a plurality of semiconductor integrated circuit devices are electrically connected to a common wiring pattern, and a plurality of semiconductor integrated circuits are simultaneously burnt-in test via the wiring pattern. Supply signals to perform burn-in test.

According to the tenth aspect of the invention, the wiring pattern is made of polysilicon.

According to the eleventh aspect of the present invention, the switching means for switching whether or not to supply the burn-in test signal is provided between the semiconductor integrated circuit device and the wiring pattern.

According to the twelfth aspect of the invention, in the burn-in test process, the burn-in test is performed by applying the same load to the memory cells of the normal memory cell array, the first redundant means and the second redundant means.

According to the thirteenth aspect of the present invention, there is provided a step of storing information on laser trimming in the first laser trimming step, and whether or not the defective memory cell of the normal memory cell array can be relieved in the second laser trimming step. Laser trimming is performed based on that information.

According to the fourteenth aspect of the present invention, a dicing step of individually separating the plurality of semiconductor integrated circuit devices provided on the wafer from the wafer, and the semiconductor integrated circuit device is provided with an insulating layer having a lead frame on the surface. Placing on a tape and electrically connecting to a lead frame.

According to the invention of claim 15, the tape is provided with a window for exposing the surface of the semiconductor integrated circuit device to the outside.

According to the sixteenth aspect of the present invention, there is provided a step of providing on the semiconductor integrated circuit device an insulating cover tape having a window for exposing the surface of the semiconductor integrated circuit arranged on the tape to the outside. I have it.

[0025]

According to the first aspect of the present invention, the semiconductor integrated circuit device is provided with the first and second redundant means so that the laser trimming can be performed twice in total. Replace the defective memory cell in the normal memory cell array generated in the process step with the first redundancy means, and then perform the burn-in test,
The defective memory cell in the normal memory cell array generated in the burn-in test is replaced with the second redundant means in the second laser trimming.

According to the second aspect of the present invention, the address of the defective memory cell in the normal memory cell array is programmed in advance when an address signal matching the address of the defective memory cell is input from the address means. And the second control means functionally replaces the defective memory cell with the spare memory cell which is the first and second redundant means.

According to the third aspect of the present invention, the address of the defective memory cell in the normal memory cell array is programmed in advance when an address signal matching the address of the defective memory cell is input from the address means. And the second control means functionally replaces the defective memory cell with the spare memory cell which is the first redundant means, and replaces the spare memory cell of the spare memory cell circuit on a bit-by-bit basis.

According to the fourth aspect of the present invention, the first and second redundant means are provided in the semiconductor integrated circuit device so that the laser trimming can be performed a total of two times. Replacing the defective memory cell in the normal memory cell array generated in the wafer process step with the first redundancy means, and then performing a burn-in test, and performing a second laser trimming on the defective memory cell in the normal memory cell array generated in the burn-in test. At the second redundant means.

According to the fifth aspect of the present invention, a plurality of semiconductor integrated circuit devices are simultaneously burned in by using a probe card provided with a plurality of probes for supplying burn-in test signals to the semiconductor integrated circuit devices.

According to the present invention, the burn-in test signal is supplied only to the semiconductor integrated circuit device selected in advance by the switching means for switching whether or not the burn-in test signal is supplied. Testing.

According to the ninth aspect of the present invention, a plurality of semiconductor integrated circuit devices are connected to a common wiring pattern, and burn-in test signals are simultaneously supplied to the plurality of semiconductor integrated circuit devices via the wiring pattern.

According to the tenth aspect of the invention, since the wiring pattern is made of polysilicon, no dust is generated during dicing.

According to the eleventh aspect of the invention, the burn-in test is performed by supplying the burn-in test signal only to the semiconductor integrated circuit device selected in advance by the switching means for switching whether to supply the burn-in test signal. .

According to the twelfth aspect of the invention, the burn-in test is performed by applying a load equivalent to the load applied to the normal memory cell array to the first and second redundant means.

According to the thirteenth aspect of the present invention, in the second laser trimming step, laser trimming is performed by determining whether or not the defective memory cell of the normal memory cell array can be repaired based on the information of the first laser trimming step.

According to the fourteenth aspect of the present invention, the plurality of semiconductor integrated circuit devices formed on the wafer are individually cut, placed on an insulating tape and subjected to a burn-in test.

According to the fifteenth aspect of the invention, the surface of the semiconductor integrated circuit device provided on the insulating tape is exposed to the outside through the window provided in the tape.

According to the sixteenth aspect of the present invention, since the cover tape having the window for exposing the surface of the semiconductor integrated circuit device to the outside is provided, the surface of the semiconductor integrated circuit device is exposed to the outside. There is.

[0039]

【Example】

Example 1. A manufacturing process flow of one embodiment of the present invention will be described below with reference to FIG. In the figure, steps S1 and S
5 and S7 are the same as those in the conventional example of FIG. 37, and steps S2A and S2B are the same as step S2 in the conventional example, so a detailed description is omitted here. Step S
Reference numeral 10 is a test combining steps S6 and S8 of the conventional example, which is a test for selecting access items and performing a low temperature / high temperature selection test. In this embodiment, first, similarly to the conventional example, laser trimming is performed in step S2A after the wafer process step in step S1. Here, the semiconductor integrated circuit device of the present invention is provided with two redundant means so that the laser trimming can be performed twice in total, as shown in the configurations in Examples 14 and 15 to be described later. Has been. Step S2A
The defect to be relieved by is mainly caused by the wafer process, and is performed by using one of the two redundant means. next,
In this embodiment, a burn-in test is performed in step S7. If the burn-in test in step S7 determines that the result is good, the process goes to step S5 through the second laser trimming process in step S2B. If the burn-in test determines that the memory cell is defective (burn-in defect), the burn-in defective memory cell is relieved by the other redundant means of the above two redundant means in the step S2B. The rescued IC chip is then subjected to the post test of step S2B (step S2c).
Only when the result is determined to be good in step S5, the process proceeds to step S5. The molded and lead-processed and processed products in the step S5 go to the process of step S10, where the access item selection test and the low-temperature / high-temperature selection test are shipped, and the products can be shipped if they are non-defective. As described above, since the defective product (burn-in defect) in the burn-in test is also repaired by the process of step S2B, it is possible to reduce the assembly cost.

In this embodiment, the case of performing the burn-in in the wafer state has been described, but the present invention is not limited to this case, and the burn-in may be performed in a bare chip (a state in which the wafer state is cut into individual chips). FIG. 2 shows the flow of burn-in with bare chips. As shown in FIG. 2, after the first laser trimming (step S2A), each chip 9 is separated by dicing (see FIG. 30), and the carrier tape 70 (see FIG. 32).
After the upper bonding (step S11), a burn-in test is performed (step S7), and after completion, replacement with a redundant memory by laser trimming is performed again (step S2B). At this time, the redundant memory to be replaced by laser trimming in step S2B is applied with the same voltage as the normal memory at the time of burn-in test (step S7) through the conductive terminals connected to each chip by devising a circuit. It is advisable to do so (see Example 16).

As described above, according to the manufacturing process flow of the present invention, the laser trimming is performed again after the burn-in test so that the burn-in defect can be relieved. Therefore, the yield in the shipping test can be improved. In addition, since the mold and lead processing is performed after the burn-in defect is repaired, a burn-in test is performed after the mold and lead processing as in the conventional case, and the burn-in defect after the mold and lead processing cannot be repaired and is discarded as compared with the case of discarding. Since the manufacturing cost is not wasted, the cost can be reduced accordingly.

Example 2. In this embodiment, a step of applying a protective film is added to the manufacturing process of the first embodiment. FIG. 3 shows a flow of the manufacturing process of this embodiment. As shown in the figure, in this embodiment, before the dicing step (step S11), a protective film is applied on the surface of the IC chip on the wafer (step S12). In this case, a nitride film (SiN), a polyimide film or the like is suitable as the protective film. In this embodiment, since the protective film can prevent foreign matters such as dust from adhering to the surface of the IC chip, the dicing process (step S1)
The steps from 1) can be carried out even in a place with low cleanliness.

Example 3. In the second embodiment, the step of applying the protective film (step S12) is performed before the dicing step (step S11). However, in this embodiment, the burn-in test step (step S7) is performed.
Second laser trimming process (step S2)
B) This is done later. FIG. 4 shows the flow of the manufacturing process in this embodiment. In the second embodiment, since the laser trimming is performed after the protective film is applied, the trimming trace protective film is removed by trimming, and the trimming trace is small. Therefore, the IC chip is foreign matter such as dust. Sufficient to protect against water, but moisture can penetrate through the cracks. In this embodiment, since the protective film is applied after the laser trimming, the protective film can completely protect the IC chip from dust and moisture, and the moisture resistance and the reliability are improved.

Example 4. This embodiment corresponds to the above-mentioned embodiment 1.
When the burn-in test in the wafer state (see FIG. 1) is performed (step S7), the wafer 3 (FIG.
All the IC chips 9 (see FIG. 1) provided on the
2) is provided in the test device. In the conventional test apparatus, only one IC chip 9 on the wafer 3 can be tested at a time, which causes a problem of a long test time due to the recent increase in density of integrated circuits. FIG. 5 shows the test apparatus in this embodiment. As shown in FIG. 5, in this embodiment, the probe card 1 is used as the measuring means.
The probe 2 for electrically transmitting a signal from a tester (not shown) to the IC chip 9 for testing.
As many IC chips 9 as the number of IC chips 9 are provided. Therefore, by performing a burn-in test using the test apparatus according to this embodiment, signals can be simultaneously given to all the IC chips 9 on the wafer 3 via the respective probes 2, so that a large number of IC chips 9 can be provided at one time. Can be processed.

In this embodiment, the case where the probes 2 are provided for all the IC chips 9 on the wafer 3 has been described. You may make it provide the probe 2 with respect to 9. This embodiment can also be applied to the case of performing a burn-in test on the carrier tape 70 shown in FIGS.

Example 5. In this embodiment, a switching means is provided so that, during the burn-in test, whether or not to transmit a signal from a tester (not shown) can be switched for each individual IC chip 9. According to this embodiment, for example, only those which are judged as good in the laser trimming step (step S2A) performed before the burn-in test (step S7) of the above-described embodiment 1 shown in FIG. Can be sent, and no signal can be sent to those judged to be defective. The structure of the test apparatus in this embodiment is basically the same as that of the fourth embodiment. FIG. 6 shows the test apparatus in this embodiment. As shown in FIG. 6, all the IC chips 9 of the probes 2 are mounted on the probe card 1 as in the fourth embodiment, and each of the probes 2 is equipped with a switch 4 as a switching means. . Only the switch 4 attached to the probe 2 for the IC chip 9 selected in advance is switched so that the signal is transmitted to the IC chip 9. The switch 4 may be of any type,
Further, a method of switching by a program built in a tester (not shown) may be used. Also in this example,
The probes 2 provided on the probe card 1 are not necessarily required for all the IC chips 9 and may be provided for a part of the IC chips 9. As described above, in this embodiment, the switch 4 allows signals to be simultaneously transmitted only to the preselected IC chips 9 on the wafer 3, so that the preselected IC chips 9 can be processed at one time. At the same time, the current flowing through the wafer 3 can be reduced. Also, like this,
According to this embodiment, it is possible to distinguish the IC chips 9 on the wafer 3 by the switch 4 and perform a test other than the burn-in test. Incidentally, this embodiment is shown in FIG.
It is also applicable to the embodiment in which the burn-in test is performed on the carrier tape 70 of FIG.

Example 6. This embodiment shows another example of the switching means described in the fifth embodiment. In this embodiment, an IC selected in advance from a plurality of IC chips 9 on the wafer 3 is used as the switching means.
Pad 5 which is a signal input location of chip 9 (see FIG. 11)
Is provided on the surface of the pad 5 to increase the thickness of the pad. 7 and 8 show a test apparatus in this embodiment. FIG. 7 is the same as FIG. 5 showing the above-mentioned fourth embodiment. As shown in the enlarged view of FIG. 8, in this embodiment, only the pad 5 (the signal input location on the chip) provided on the surface of the IC chip 9 preselected from the IC chips 9 on the wafer 3 is used. The pad is thickened by applying a conductor 6 such as aluminum and solder to the surface. With such a structure, as shown in FIG. 8, since the conductor 5 is applied to the pad 5 of the IC chip 9 selected in advance and the thickness is increased, the probe 2 hits and the signal is transmitted. But on the other hand,
The probe 2 not selected does not receive the probe 2 due to the difference in thickness between the pad 5 covered with the conductor 6 and the pad 5 not covered with the conductor 6, and no signal is transmitted. In this way, no signal is transmitted to the IC chip 9 not selected, so that the current flowing through the entire wafer 3 can be reduced accordingly. In this way, not only the burn-in test but also other tests can be performed by distinguishing the IC chips 9 on the wafer 3. The shape of the probe 2 may be bent as shown in FIG. 7 according to the use conditions.
It may be straight as shown in.

Example 7. This embodiment shows still another embodiment of the switching means described in the fifth embodiment. In this embodiment, as the switching means,
Pad 5 which is a signal input location of IC chip 9 selected in advance from a plurality of IC chips 9 on wafer 3.
The insulating film 7 is provided on the surface of the pad 5 (see FIG. 11). This embodiment is shown in FIGS. 9 and 10. In this embodiment, as shown in FIG. 10, an IC previously selected from a large number of IC chips 9 on the wafer 3 is used.
Since the surface of the pad 5 of the chip 9 is covered with the insulating film 7, no signal is transmitted to the IC chip 9. At this time, the insulating film 7 is applied as thinly as possible. As shown in FIG. 9, the test apparatus of this embodiment has the same structure as that of the fourth embodiment (see FIG. 5), so that the probe cards 1 are mounted with the probes 2 for all the IC chips 9. I try to give a signal to all IC chips 9 at the same time.
Since the surface of the pad 5 is covered with the insulating film 7, no signal is transmitted and the current flowing through the entire wafer 3 is reduced. Further, the insulating film 7 need not cover the entire pad 5 of the IC chip 9, but may include only the pad 5 for power supply, for example. Thus, contrary to the sixth embodiment, the selected IC
Since no signal is transmitted to the chip 9 by the insulating film 7, the current flowing through the entire wafer 3 can be reduced accordingly. It should be noted that this embodiment can be applied to tests other than the burn-in test.

Example 8. This embodiment shows still another embodiment of the switching means described in the fifth embodiment. In this embodiment, as the switching means,
The pad 5 of the IC chip 9 selected in advance from the plurality of IC chips 9 on the wafer 3 is insulated by cutting a part of the wiring conductor 11 connected to the pad 5. FIG. 11 shows the IC chip 9 in this embodiment. As shown, a plurality of pads 5 are provided on the IC chip 9. Pad 5
It is electrically connected to the internal circuit 10 of the IC chip 9 via the wiring conductor 11. In this embodiment, when a plurality of IC chips 9 on the wafer 3 are simultaneously subjected to the burn-in test, the wiring connected to the pad 5 of the IC chip 9 which is abnormal from the plurality of IC chips 9 on the wafer 3 in advance. After cutting a part 11a of the conductor 11, a burn-in test is performed. Since the wiring conductor 11 which is a signal transmission path is cut off, the IC chip 9
No signal is transmitted to. As shown in FIG. 5, when the probes 2 for all the IC chips 9 are attached to the probe card 1, all the IC chips 9 corresponding to the probes 2 are attached.
However, since the signal is not transmitted to the IC chip 9 in which the wiring conductor 11 is cut, the current is reduced accordingly. It is not necessary to cut the wiring conductors for all the pads 5 provided on the IC chip 9, and for example, only the wiring conductors 11 of the power supply pads 5 may be cut. Further, in this manner, the IC chips 9 on the wafer may be distinguished and not only the burn-in test but also another test may be performed.

Example 9. This embodiment shows one embodiment of a method for applying the conductor 6 (see FIG. 8) or the insulator 7 (see FIG. 9) to the surface of the pad 5 in the above-described sixth and seventh embodiments. is there. In this embodiment, the IC chips 9 on the same wafer 3 are distinguished by whether the reticle 8 for one chip as shown in FIG. 13 is used or not for the IC chips 9 on the same wafer 3. , Conductor 6 or insulating film 7 is applied. When the reticle 8 is used for a part of the IC chips 9 and exposure is performed, the reticle 8
Since the IC chip 9 that uses the reticle 8 does not receive light, and the IC chip 9 that does not use the reticle 8 shines light,
By using it, the conductor 6 or the insulator 7 is connected to the IC chip 9
It is applied by light curing on the surface of. Conductor 6
The insulating film 7 and the insulating film 7 need not be applied to the entire surface of the IC chip 9, and may be applied only to the power supply pad. By using the reticle 8 to distinguish the IC chips 9 on the wafer 3 and applying the conductor 6 or the insulating film 7, only the selected IC chips 9 on the wafer 3 can be subjected to a test such as a burn-in test. It becomes easy to give a signal. Further, since the conductor 6 or the insulating film 7 is applied,
Even after dicing, it becomes easy to distinguish and select the IC chip 9.

Example 10. Conventionally, when performing a burn-in test in a wafer state, the number of wirings for transmitting a signal to each chip 9 becomes enormous, and the cost and difficulty of wiring alignment have been problems. In this embodiment, in the burn-in test in the wafer state (step S7) in the flow shown in the first embodiment (see FIG. 1), a signal is sent to a plurality of IC chips 9 on the wafer 3 using common wiring. It is the one. FIG. 14 shows the common wiring 16 in this embodiment. A signal for a burn-in test (step S7) output from a tester (not shown) or the like is given to the burn-in test input / output signal pad 15 via the probe 2 (see FIG. 8), from which the common wiring 16 is connected. Each IC through the wiring 18 that electrically connects the pad 5 of each IC chip 9 and the common wiring 16.
It is sent to the chip 9. By transmitting signals collectively to a plurality of IC chips 9 by using the common wiring 16 in this way, the number of wirings is reduced as compared with the case where all the IC chips 9 on the wafer 3 are individually wired. Alignment becomes easier. Further, as compared with the conventional case in which the probes 2 (see FIG. 8) are sequentially applied to all the IC chips 9 on the wafer 3, it is possible to measure a plurality of IC chips 9 at a time, so the test time is correspondingly increased. In addition to being able to shorten the length, the number of probes 2 can be greatly reduced, the cost can be reduced, and the alignment of the probes 2 can be facilitated. Also, the step of aligning the probe 2 with the pad 15 is facilitated.

Further, in this embodiment, the wiring 18 connecting the pad 5 of each IC chip 9 and the common wiring 16 is formed after the laser trimming step (step S2A), and the IC chip 9 determined to be defective in the laser trimming step.
No wiring 18 is provided to the IC chip so that the signal during the burn-in test is sent only to the IC chip 9 determined to be good. Therefore, in this embodiment, the result of the laser trimming can be reflected in the burn-in test, and the IC chip 9 determined to be defective by the laser trimming can be prevented from being subjected to the burn-in test.
The total current can be reduced.

Pad 5 of each IC chip 9 and common wiring 16
As a method of forming the wiring 18 for connecting to and from each other, a reticle may be used as shown in the ninth embodiment,
Alternatively, electron beam exposure (EB exposure) may be performed. Further, the common wiring 16 may be formed by a wafer process (step S1) or may be formed together with the wiring 18 after laser trimming (step S2A). When forming after laser trimming, similar to the case of the wiring 18, it is performed by a reticle or electron beam exposure (EB exposure). Further, the common wiring 16 and the wiring 18 are all provided in advance in the wafer process (step S1), and before the burn-in test (step S7), an IC chip determined to be defective in the laser trimming step (step S2A) is performed. You may use the method of cutting only the wiring 18 connected to 9 by blowing.

Further, in the past, for example, public game number 89-4
Since Al wiring is used as wiring as disclosed in H.237, Al chips are generated during dicing,
Often damages the surface of the tip 9,
Further, since the burn-in test is not related to the measurement of the operating speed of the IC chip 9, in this embodiment, the wirings such as the common wiring 16 are made of polysilicon although the resistance value is high, and the scraps at the time of dicing are removed. This prevents the IC chip 9 from being damaged and the yield from being lowered due to damage to the IC chip 9.

Further, in this embodiment, as shown in FIG. 15, the common wiring 16 is provided in the dicing line as shown by the broken line in FIG. 15 which is an area between the IC chips 9 and 9. As a result, the area taken by the wiring on the wafer 3 is increased and the yield is prevented from being affected. Each IC chip 9 is cut in chip units along the alternate long and short dash line 9a in the above dicing process. for that reason,
After being diced, the dicing line, which is the area between the IC chip 9 and the IC chip 9, is cut off from the IC chip 9. Therefore, a common wiring 16 which is a wiring necessary only for the burn-in test is provided at that portion. Since the common wiring 16 is not provided in the IC chip 9, the area of the IC chip 9 can be reduced and the IC
It is possible to prevent the yield of the chips 9 from decreasing.

Example 11. In this embodiment, in addition to the structure of the above-described tenth embodiment, as shown in FIG. 16, the IC chips 9 are rotated by 180 degrees every other row, so that the common wiring 16 is shared by adjacent rows. It is intended to be used for. According to this embodiment, since the common wirings 16 are commonly used in the adjacent columns, the number of the common wirings 16 can be halved. Therefore, even if the chip 9 has many bits, The number of dicing lines can be increased and the dicing line can be prevented from bulging.

Example 12 In this embodiment, in addition to the structure of the above-mentioned embodiment 10 or 11,
As shown in FIG. 7, the wiring 18 connecting the common wiring 16 and the pad 5 of each IC chip 9 is provided with a switching means by a switch 20. By connecting and disconnecting the electrical connection between the common wiring 16 and the IC chip 9 by using the switch 20, the IC chip 9 is connected to the common wiring 16 by
It is possible to easily switch between a state in which the IC chip 9 is connected to another IC chip 9 on the wafer 3 via and a state in which the IC chip 9 is independently separated. At this time, when a common signal is sent to a plurality of IC chips 9 such as a burn-in test, all the IC chips 9 are connected to the common wiring 16 by the switch 20, and laser trimming and wafer test are performed. As described above, when testing is performed for each chip, it is preferable to connect only the target IC chip 9 to the common wiring 16. In that case, the IC chip 9 can be measured according to the purpose by always contacting the input / output signal pad 15 without changing the place where the probe 2 (see FIG. 8) is applied.
It is also possible to apply the probe 2 only to the IC chip 9 with the switch 20 turned off. As described above, according to this embodiment, it is possible to easily switch whether or not to connect each IC chip 9 between the burn-in test and the test individually performed for each IC chip 9, and efficiently perform each. The test can be simplified according to the purpose of the test.

Example 13 This embodiment is the same as the first embodiment described above.
2 shows a modified example of No. 2. In this embodiment, instead of the switch 20 of the twelfth embodiment, a transfer gate 22 is used as the switching means as shown in FIG. In this embodiment, when the IC chip 9 is individually tested such as laser trimming or wafer test, the signal input to the probe pad 24 by the probe 2 (see FIG. 8) is When an unselected chip is set to an "L" signal, and when a signal is commonly sent to a plurality of IC chips 9 such as in a burn-in test, the probe pad 24 input is set to OPEN and those IC chips 9 are not connected. 9 is connected to the common wiring 16. Before each test, set the transfer gate to the operating state and
It is confirmed whether or not the chip 9 is connected, and it is confirmed whether or not the chip 9 is defective. By doing so, it is possible to prevent the generation of the IC chip 9 to which the voltage signal of the burn-in test is not applied. As described above, also in this embodiment, whether to connect each IC chip 9 can be easily switched between the burn-in test and the test individually performed for each chip, and the simplification of the test is improved. Can be made.

Example 14 The following embodiment shows the configuration of the redundant circuit of the present invention. FIG. 19 is a block diagram showing the configuration of the redundant circuit according to the embodiment of the present invention. As shown, three decoders 32, 33 and 36 are provided in the address buffer 31 to which the address signal is supplied.
Are electrically connected, and the output from the address buffer 31 is supplied in parallel to the three decoders 32, 33 and 36. The decoder 32 is a regular memory cell array 34
Memory cell in the memory cell is selected and one or more memory cells are selected by supplying the decoder output to the regular memory cell array 34, and then data is stored in the selected memory cell. Or it may be read. The other decoders 33 and 36 are provided independently of each other, and select the memory cells in the spare memory cell arrays 35 and 37, respectively, when a defective memory cell occurs in the normal memory cell array 34. belongs to. The memory cells are selected by supplying the decoder outputs of the decoders 33 and 36 to the spare memory cell arrays 35 and 37. The decoding operation of the decoder 32 is controlled by the outputs of the other decoders 33 and 36.

When a defective memory exists in the normal memory cell array 34, the decoders 33 and 36 receive the address signal corresponding to the defective cell from the address buffer 3.
When supplied to 1, it is programmed to select the memory cells of the spare memory cell arrays 35 and 37. It should be noted that the execution of this program is such that fuses made of aluminum or polycrystalline silicon provided inside the decoders 33 and 36 are selectively blown by laser irradiation or the like, or are in a high resistance state in the initial state. This is performed by selectively annealing the crystalline silicon to reduce the resistance. Therefore,
In this embodiment, since the laser trimming process can be performed twice, as shown in, for example, the first embodiment (see FIG. 1), a defective memory cell is formed in the normal memory cell array 34 due to a wafer process process or the like. If the cell exists, the decoder 33 selects the memory cell in the spare memory cell array 35 and stops the decoding operation of the decoder 32 as the first laser trimming step (step S2A). Programmed. As a result, the defective memory cell in the normal memory cell array 34 is functionally replaced with the non-defective memory cell in the spare memory cell array 35. In that sense, the defective memory cell can be substantially non-defective. .
Next, a burn-in test is performed (step S7)
However, if there is a defective memory cell in the normal memory cell array 34 in the burn-in test, the decoder 36 selects the memory cell in the spare memory cell array 37 as the second laser trimming step (step S2B), and the decoder 32 To stop the decoding operation,
The decoder 36 is programmed. Thus, in this embodiment, since the decoders 33 and 36 connected to the spare memory cell are independent of each other, the laser trimming process can be performed twice.

In the conventional semiconductor integrated circuit device with a redundancy function, the laser trimming process is performed only once as described above, so that it is naturally possible to receive the address information of the defective bit of the normal memory cell. Although only one memory cell is provided, in this embodiment, two spare memory cells are provided, so that the laser trimming process can be performed twice, and conventionally it is impossible to repair. Since the memory cell having the burn-in failure can be relieved by performing the second laser trimming, the yield can be improved, and the cost of the product which cannot be relieved in the past and is discarded can be avoided. Therefore, the manufacturing cost can be kept low accordingly. In this embodiment, the spare memory cell array 35 connected to the decoder 33 is used to repair the defective memory cell, but the spare memory cell array 3 connected to the decoder 36 is used.
You may use from the 7th. Further, in this embodiment, an example in which two spare memory cell arrays are provided is shown, but three spare memory cell arrays are provided depending on the required number of laser trimmings.
One or more may be provided.

Example 15. This embodiment shows another embodiment of the redundancy function of the present invention. Generally, a burn-in defect is often a bit defect (a defect of one bit at a time), and thus the method of replacing a memory cell array with a spare memory cell in a row unit (column unit) or a column unit (row unit) is inefficient. Therefore, in this embodiment, in the first laser trimming process, the defective memory cells are replaced with the memory cells of the spare memory cells 105 on a row-by-row or column-by-column basis, and the second laser after the burn-in test is performed. In the trimming process, the defective memory cell is replaced with the memory cell of the spare memory cell circuit 40 bit by bit. In this embodiment, as shown in FIG.
In addition to the conventional redundancy function shown in FIG. 6 in which one spare memory cell is provided, redundancy in bits is added to replace defective memory cells with spare memory cells in 1-bit units.

The structure shown in FIG. 20 will be briefly described. First, as in the conventional example of FIG.
04, a spare memory cell 105 is provided in parallel with the spare memory cell 104. If a defective memory cell exists in the normal memory cell 104, the spare memory cell is processed by the first laser trimming process (step S2A). 105 is replaced and repaired. In order to perform the second laser trimming process after the burn-in test, in this embodiment, as shown in the figure, the memory cells are electrically connected to the address buffer 101 and the input buffer 42 to replace the defective memory cells in bit units. A spare memory cell circuit 40 having a spare memory cell for switching, a switching circuit 44 connected to the normal memory cell 104 and the spare memory cell 105 through a sense amplifier 45, and a spare memory cell circuit 40.
The switching circuit 43 connected to the address buffer 10 and the address buffer 10.
1 and the input buffer 42, the switching circuit 44
And a switching control circuit 41 for controlling the operations of 43 are provided, and these constitute redundancy in bit units. The sense amplifier 45 does not necessarily have to be provided, and may be provided as needed. Also,
The input buffer 42 may also be provided separately from the address buffer 101 as shown in FIG.
They may be put together into one buffer. The switching circuits 44 and 43 are connected to the output buffer 46 via the data bus 47 as shown in the figure.

The operation will be described. The operation of the first laser trimming process is performed in the same manner as described above, and thus the description thereof is omitted here. However, in the laser trimming here, as described above, replacement of the memory cells is performed in row units (column units) or column units (row units).
In the second laser trimming step, if there is a defective memory cell due to the burn-in test in the normal memory cell 104, the switching control circuit 41 has a fuse (corresponding to each memory cell) provided therein. The address of the defective memory cell is programmed bit by bit by a method of melting (not shown) by laser irradiation or the like. As a result, the switching control circuit 41 controls the switching circuits 44 and 43, and the normal memory cell 10
Spare memory cell circuit 4 instead of the defective memory cell 4
0 memory cells are operated.

As described above, this embodiment also has a redundancy function for performing laser trimming a total of two times before and after the burn-in test, and the first time has row units (column units) or column units (row units). Since the second time is performed on a bit-by-bit basis, more defects due to a burn-in test with many bit defects can be efficiently relieved, yield can be increased, and manufacturing can be performed at low cost.

Example 16. In this embodiment, during the burn-in test, stress is applied to the unused redundant rows and unused spare memory cells during the burn-in test, and the laser after the burn-in test (step S7) is performed.
This is to reduce the occurrence of initial defects in the chip rescued by the trimming process (step S2B). Figure 21
FIG. 19 is a block diagram showing the configuration of the redundant function of this embodiment. However, since the configuration is almost the same as in FIG. In this embodiment, as shown in FIG. 21, the redundant row program circuit 39 is electrically connected to the decoders 32, 33, and 36, and the redundant row program circuit 39 is now in the burn-in mode. The signal B is input. The normal row 32aa of the normal row 32a in which the defect has occurred is the redundant row 33a or 36a.
And the laser trimming process (step S2A).

When the burn-in mode signal B for leaving the unused redundant row 33aa or 36aa in the inactive state is input, the redundant row program circuit 39 displays the replaced redundant row 33a in the waveform diagram of FIG. The redundant row 33aa or 36aa which has not been replaced and is not replaced is fixed to "L" and is not operated. In addition, unused redundant rows 33aa or 3
When the burn-in mode signal B for activating 6aa is input, the redundant row program circuit 39 operates as shown in FIG.
As shown in the waveform diagram, the unused redundant row 33aa or 36aa is operated in the same manner as the normal row 32a and the replaced redundant row 33a or 36a. Burn-in mode signal B activates unused redundant row 33aa or 36aa only during the burn-in test. That is, during the normal operation other than the burn-in test, the waveform operates as shown in FIG. 22, and during the burn-in test operates as the waveform shown in FIG.

In this embodiment, as described above, the stress at the burn-in test is applied to the unused redundant row 33aa or 36aa which has not been replaced, like the normal row 32a. 33a
The initial failure of a or 36aa can be removed, and even if the unused redundant row 33aa or 36aa is used for replacement in the laser trimming process after the burn-in test, the initial failure does not occur after manufacturing. .

Example 17 This embodiment shows one embodiment of the structure of the burn-in mode signal generating means for generating the burn-in mode signal B of the above-mentioned sixteenth embodiment. FIG. 24 shows the structure of the burn-in mode generation circuit 50 which is the burn-in mode signal generation means in this embodiment. The burn-in mode generation circuit 50 is provided in the chip, and as shown in the figure, the reference voltage generation circuit 51 that generates the reference voltage Vref is compared with the reference voltage Vref and the voltage Vcc applied to the chip to burn-in mode signal B. Is output to the redundant row program circuit 39. During the burn-in test, a voltage Vcc higher than a certain voltage which is higher than the voltage normally used is applied. Therefore, the burn-in mode generation circuit 50 uses the voltage Vcc applied to the chip.
c is the reference voltage V generated from the reference voltage generation circuit 51.
The comparison circuit 52 compares whether or not it is larger than ref, and discriminates between the burn-in test and other normal times, and the burn-in mode signal B is generated accordingly.
Therefore, the burn-in mode generation circuit 50 of this embodiment is
Can be said to constitute a burn-in voltage detection circuit that detects whether or not the voltage is during the burn-in test.

As described above, according to this embodiment, it is possible to easily determine whether or not the burn-in test is in progress, whereby the burn-in mode signal B can be easily switched. Further, since the burn-in mode generation circuit 50 is provided in the chip to generate the burn-in mode signal in the chip, it is not necessary to provide an extra pad, and no device for giving a signal to the pad is required. is there.

Example 18. This embodiment shows another embodiment of the structure of the burn-in mode signal generating means for generating the burn-in mode signal B of the above-mentioned sixteenth embodiment. FIG. 25 shows the structure of the burn-in mode signal generating means in this embodiment. The burn-in mode signal generating means in this embodiment, as shown in the figure, includes a burn-in mode signal pad 55 for supplying a burn-in mode signal B from the outside, and a burn-in mode signal transmitted from the burn-in mode signal pad 55. B
To the redundant row program circuit 39 by adjusting the transmission timing or the like and transmitting the signal.
6 is comprised. Regarding the method of applying the burn-in mode signal B to the burn-in mode signal pad 55, for example, as shown in FIG. 26, the burn-in mode signal B may be applied via the probe 2 provided outside.

When the burn-in mode signal B as shown in the seventeenth embodiment (see FIG. 24) is generated inside the chip, the burn-in mode generation circuit 5 is used.
Although there is a possibility that the circuit 50 malfunctions due to manufacturing variation of 0 or the like, in this embodiment, since the burn-in mode signal B is given from the outside of the IC chip 9 by the probe 2, the burn-in mode signal B is surely set to the normal time. You can switch between the burn-in test and.

Example 19 This embodiment shows a modification of the eighteenth embodiment. In this embodiment, as shown in FIG. 27, the burn-in mode signal pad 55 is provided outside the IC chip 9 and is commonly used by a plurality of IC chips 9. As shown
Each IC chip 9 is provided with a pad 5, and the pad 5 is electrically connected to a redundant row program circuit 39 (see FIG. 25) provided in the IC chip 9.
Further, the common wiring 1 is provided on the dicing line of the wafer 3.
6 are provided and commonly connected to the pads 5 of the plurality of IC chips 9. Further, one end of the common wiring 16 is connected to a burn-in mode signal pad 55 provided on the wafer 3. Therefore, in this embodiment, one burn-in mode signal pad 55 is shared by a plurality of IC chips 9, and when the burn-in mode signal B is supplied to the burn-in mode pad 55 from the probe 2, a plurality of IC chips 9 are burned. The signal is simultaneously given to the IC chip 9. Incidentally, in this embodiment as well, the burn-in mode signal buffer 56 (see FIG. 25) may be provided as required, as shown in the above-mentioned eighteenth embodiment.

Also in this embodiment, the burn-in mode signal B is applied from the outside of the IC chip 9 by the probe 2 similarly to the eighteenth embodiment. Can be switched with, and the number of probes is small compared to the case where the probes 2 are applied to all the IC chips 9,
The alignment of the probe 2 becomes easy, and the probe card 1 (see FIG. 5) becomes inexpensive. Furthermore, since signals can be supplied to a plurality of chips 9 at the same time, the burn-in test can be performed quickly. Furthermore, in this embodiment, since the burn-in mode pad 55 is provided in the IC chip 9, it is not necessary to provide a dicing line and the number of IC chips 9 on the wafer 3 can be increased, so that the yield can be improved. Can be improved.

Example 20. This embodiment shows another embodiment in which the spare memory cell array is subjected to stress during the burn-in test as in the normal memory cell array. FIG. 28 is a block diagram showing the configuration of this embodiment. Since the basic structure is similar to that of FIG. 19, description of the same parts will be omitted. Normal rows (bit lines) 32aa and 32ab are connected to the memory cells of the normal memory cell array 34. Redundant rows (bit lines) 33aa and 33ab are connected to the memory cells of the spare memory cell array 35, and redundant rows 36aa and 36ab are similarly connected to the memory cells of the other spare memory cell array 37. The normal row 32aa connected to the memory cells of the normal memory cell array 34 and the redundant rows 33aa and 36aa connected to the memory cells of the spare memory cell arrays 35 and 37 are connected by a fuse 61. A normal row 32ab connected to the memory cells of the normal memory cell array 34 and redundant rows 33ab and 36ab connected to the memory cells of the spare memory cell arrays 35 and 37 are connected by a fuse 62.

At the first laser trimming step (step S2A), if there is no defective memory cell in the normal memory cell array 34, the burn-in test step (step S7) is performed. Then fuses 61 and 6
2, normal rows 32aa and 32ab and redundant rows 33aa, 33ab, 36aa, and 36a.
b is connected to the auxiliary memory cell array 35.
The stress equivalent to that of the normal memory cell is also applied to and 37. After the burn-in test is completed, redundant rows 33aa, 33ab, 36aa of the spare memory cell arrays 35 and 37,
Also, the fuses 61 and 62 connected to 36ab are cut off. Then, in the second laser trimming process (step S2B), the regular memory cell array 34 is
When there is a defective memory cell therein, the decoder 33 is programmed so that the decoder 33 selects the memory cell of the spare memory cell array 35 when the address signal corresponding to the defective memory cell is supplied. In the subsequent process, the mold and the lead are processed and the shipping test is performed as described above. Although the example in which the decoder 33 corresponding to the spare memory cell array 35 is used first is shown, the invention is not limited to this case, and the decoder 36 corresponding to the spare memory cell array 37 may be used first. good.

In the first laser trimming step (step S2A), the normal memory cell array 34 is also used.
If there is a defective bit therein, the fuses 61 and 62 connected to the redundant rows 33aa and 33ab of the spare memory cell array 35 are blown, and the decoder 33 is selected so that the decoder 33 selects the memory cell of the spare memory cell array 35. Program and remedy bad bits. Next, a burn-in test (step S7) is performed. Therefore, the redundant row 36 connected to the spare memory cell array 37
Since aa and 36ab are connected to normal rows 32aa and 32ab by fuses 61 and 62, the same stress as that of normal memory cell 34 is applied to spare memory cell array 37. When the burn-in test is completed, the redundant row 36aa of the spare memory cell array 37 is
And fuses 61 and 62 connected to 36ab. Then, in the second laser trimming step, if there is a defective memory cell in the normal memory cell array 34, the decoder 36 causes the memory cell of the spare memory cell array 37 when the address signal corresponding to the defective memory cell is supplied. Decoder 36 to select
To program. After that, the assembly and the shipping test are performed as in the conventional example. Although an example in which the decoder 33 corresponding to the spare memory cell array 35 is used is shown above, the present invention is not limited to this case, and the spare memory cell array 37 may be used.
The decoder 36 corresponding to the above may be used first.

The normal rows 32aa and 32ab connected to the normal memory cell array 34 as described above.
And redundant rows 33aa, 33ab, 36aa and 36 connected to the spare memory cell arrays 35 and 37.
Since ab and ab are connected via fuses 61 and 62, stress is applied to the memory cells of spare memory cell arrays 35 and 37 in the same manner as the memory cells of normal memory cell array 34 during the burn-in test.
It is possible to prevent the occurrence of initial defects.

Example 21. In this embodiment, the laser blow information in the first laser trimming step (step S2A), that is, the address of the defective memory cell in the rescued normal memory cell 34 (see FIG. 19) and the redundant row used for the rescue Information is recorded and the second laser trimming process (step S2
The information is used in the case of B).
This is because, for example, in the conventional semiconductor integrated circuit device shown in FIG. 36, only one redundant row 103a is provided as shown in FIG. 40, and the first laser trimming process before burn-in (step S2A). Consider a case where the defect a at the time of the laser trimming pre-test (step S2a) exists at the position shown in the figure, and only one redundant row 103a is used in the laser blow (step S2b). At this time, when a defect b occurs as shown in the figure during the laser trimming pretest (step S2a) of the second laser trimming (step S2B) after burn-in, the normal row 102a having the defect b is connected. The existing memory cell cannot be relieved because only one redundant row 103a has already been used in the first laser trimming step. However, since the conventional semiconductor integrated circuit device does not have the laser blow information in the first laser trimming process (step S2A) at the time of the second laser trimming process (step S2B), the case shown in FIG. It is judged as possible, and the same redundant row 1
Laser trimming is performed using 03a. Therefore, in the conventional configuration, the rescue rate of the second laser blow is poor, and unnecessary laser blow is often performed.

In this embodiment, as shown in FIG. 29, a step of recording blow information (step S15) is provided in the flow of the manufacturing process, and the blow information of the first laser trimming step is stored and stored. It is used as information for determining whether or not repair is possible in the second laser trimming process. Regarding the method of recording blow information, for example, a laser trimming pretest (step S2
A) and a tester (not shown) used in the post test (step S2c) may be provided with a storage unit such as a memory, and each IC chip 9 may be stored therein.

The blow information is recorded in each IC chip 9
It is necessary to store the data for each IC chip 9, but if the burn-in test is performed after dicing and the second laser trimming is performed in the chip state (see FIGS. 2 to 4), the correspondence between each IC chip 9 and the blow information becomes a problem. Therefore, as shown in FIG.
As shown in 0, each IC chip 9 may be marked with a symbol 65 in the wafer process (step S1) so that the position of the IC chip 9 on the wafer 3 can be recognized even after dicing. This symbol 65 can be easily imprinted by using, for example, a master mask. By reading this symbol 65, each IC chip 9 can be associated with blow information.

Further, the IC on the wafer 3 after dicing
If the position of the chip 9 is recognizable, it becomes easy to analyze defects caused by manufacturing variations in the wafer process. The manufacturing variation in the wafer process is considerably large even within the wafer surface, and if the distribution of defects in the wafer surface and the distribution of manufacturing variations are correlated, the cause of the defects can be easily identified.

Example 22. In the following examples, a case will be described in which the burn-in test is performed after being provided on the carrier tape after the dicing step (step S11) as shown in the flow charts of FIGS. As shown in FIG. 30, each IC chip 9 is separated into chips by the dicing process (step S11), and is arranged on the carrier tape 70 in the longitudinal direction at a predetermined interval as shown in FIG. It When placed, IC chip 9
33, as shown in FIG. 33 and FIG.
The lead frame 78 is pressure-bonded onto the carrier tape 70 so as to correspond to the position of the pad 76 of the C chip 9 and is connected by a solder paste 80 or the like. The IC chip 9 thus die-bonded can be subjected to tests such as a burn-in test (step S7) and a laser trimming pre-test (step S2a) via a terminal (not shown) connected to the lead frame 78.

As shown in FIGS. 32 and 33, the alignment holes 7 are formed on both sides of the tape carrier 70.
2a and 72b are provided. Carrier tape 70
Is due to the alignment holes 72a and 72b,
As shown in FIG. 31, it is wound on a reel 74, or mechanically fed by a feeding device (not shown) and fixed at a predetermined position. The alignment holes 72a and 72b have different shapes as shown in the partially enlarged view of FIG. 33. Since the convex portion is provided, the carrier tape 70 is not set upside down on the reel 74 and the supply device.

A laser trimming pre-test (step S2a) and burn-in test (step S7)
The defective IC chip 9 determined to be defective in the test such as the above is cut together with the carrier tape 70 along the two broken lines AA and BB in FIG. 32 and separated from other good IC chips 9. Here, the alignment holes 72a and 72b provided in the carrier tape 70.
Are arranged at the same pitch a as the arrangement interval of the IC chips 9, so if the carrier tape 70 is connected after the defective IC chip 9 is cut off, the alignment holes 72a are formed.
The pitches of 72 and 72b are the same as the original pitch a, and a large number of IC chips 9 can be processed at the same time in the molding process and the test process after cutting the defective chip, as in the case where the defective chip is not cut.

Further, in this embodiment, as shown in FIGS. 32 to 34, since the window 82 is provided in the carrier tape 70, the surface of the IC chip 9 is exposed to the outside through the window 82, and the laser Laser trimming after trimming pre-test and burn-in test (step S2b)
Is also possible.

Since the present embodiment is configured as described above, an input signal can be supplied through the lead frame 78 during a test such as a laser trimming pretest and a burn-in test, so that the pad 76 of the IC chip 9 can be directly supplied. It is not necessary to supply an input signal using the probe 2 (see FIG. 8) or the like to facilitate the test process, and since the window on the surface of the IC chip 9 is opened by the window 82, a burn-in test is performed. Laser trimming (step S2B) and shipping test (step S1)
0) etc. can be tested. Further, in the carrier tape 70, since the alignment holes 72a and 72b are provided at the same intervals as the arrangement intervals of the IC chips 9, even after the defective IC chip 9 is separated together with the carrier tape 70, the same as before the separation. It is possible to improve the efficiency of multiple simultaneous processing steps such as molding and testing.

Example 23. In Example 22 above,
Although an example in which the window 82 is provided on the carrier tape 70 has been shown, this embodiment shows the IC chip 9 as shown in FIG.
The window 86 is provided in the cover tape 84 provided on the carrier tape 70 so as to cover the. As shown, in this embodiment, the cover tape 84
And a window 86 for exposing the surface of the IC chip 9 to the outside.
Are provided in advance, and at the same time as the dicing and bonding steps (step S11) of the test flow shown in FIG. This cover tape 84 is
Apart from the protective film provided in step S12 of FIG. 3, it is provided to mechanically protect the pad 76 and the lead frame 78 provided on the IC chip 9.

In this embodiment, through window 86,
Since the burn-in mode signal pad 55 provided on the IC chip 9 is exposed to the outside, the burn-in mode signal pad 55 is changed from the window 86 to the burn-in mode signal pad 55 during the burn-in test.
The test can be performed by directly applying the probe 2 which supplies the burn-in mode signal. In this example,
Since the burn-in mode signal is applied from the outside of the IC chip 9 by the probe 2, it is possible to reliably switch the burn-in mode signal between the normal time and the burn-in test, as in the eighteenth and nineteenth embodiments. Further, as in the case of the above-mentioned twenty-second embodiment, since the surface of the IC chip 9 is opened by the window 86, laser trimming after the burn-in test and shipping test (step S10) can be performed.

[0090]

According to the first aspect of the present invention, the first and second redundant means are provided in the semiconductor integrated circuit device so that the laser trimming can be performed twice in total. Replacing a defective memory cell in the normal memory cell array generated in the wafer process step with the first redundancy means, and then performing a burn-in test, and performing a second laser trimming on the defective memory cell in the normal memory cell array generated in the burn-in test. Since it is replaced with the second redundant means in, the burn-in failure can be relieved, the yield is improved, and
With the improvement of the relief rate, waste of processing and material costs will be eliminated,
The cost can be reduced accordingly.

According to the second aspect of the present invention, by laser trimming, the defective memory cell of the normal memory cell array can be functionally easily replaced with the spare memory cell which is the first and second redundant means.

According to the third aspect of the present invention, since defective memory cells in the normal memory cell array are replaced in bit units with spare memory cells in the spare memory cell circuit, burn-in failures, which are often bit failures, can be efficiently performed. Can be replaced well.

According to the invention of claim 4, the laser trimming can be performed twice before and after the burn-in test. Therefore, the burn-in defect which could not be conventionally repaired can be repaired, and the yield is improved. With the improvement of the repair rate, processing and material costs are not wasted, and the cost can be reduced accordingly.

According to the invention of claim 5, a plurality of semiconductor integrated circuit devices are simultaneously burn-in tested by using a probe card provided with a plurality of probes for supplying burn-in test signals to the semiconductor integrated circuit devices. , Test time can be shortened.

According to the present invention, the burn-in test signal is supplied only to the semiconductor integrated circuit device selected in advance by the switching means for switching whether or not to supply the burn-in test signal. Since the test is performed, the current during the test can be reduced.

According to the invention of claim 9, a plurality of semiconductor integrated circuit devices are connected to a common wiring pattern, and a burn-in test signal is simultaneously supplied to the plurality of semiconductor integrated circuit devices through the wiring pattern. Therefore, the test time can be shortened and the test process becomes easy.

According to the tenth aspect of the invention, since the wiring pattern is made of polysilicon, no dust is generated during dicing, so that the semiconductor integrated circuit device can be prevented from being scratched by the dust and the yield is improved. be able to.

According to the invention of claim 11, the burn-in test is performed by supplying the burn-in test signal only to the semiconductor integrated circuit device selected in advance by the switching means for switching whether or not to supply the burn-in test signal. Therefore, the current can be reduced and
It can be switched according to the purpose of each test.

According to the twelfth aspect of the present invention, since the burn-in test is performed by applying a load equivalent to the load applied to the normal memory cell array to the first and second redundant means, the initial stage of the first and second redundant means. The defects can be removed, and the occurrence of initial defects after replacement can be prevented in advance.

According to the thirteenth aspect of the present invention, in the second laser trimming step, whether or not the defective memory cell of the normal memory cell array can be repaired is judged by the information of the first laser trimming step, and the laser trimming is performed. , Without unnecessary laser trimming,
In addition, it is possible to easily analyze defects.

According to the fourteenth aspect of the present invention, since the plurality of semiconductor integrated circuit devices provided on the wafer are individually cut and arranged on the insulating tape for the burn-in test, only defective products can be obtained. Can be easily separated and discarded together with the tape, and a number of good products can be processed at the same time.

According to the fifteenth aspect of the present invention, since the surface of the semiconductor integrated circuit device provided on the insulating tape is exposed to the outside through the window provided in the tape, the laser after the burn-in test is performed. Trimming and shipping tests can be easily done through the window.

According to the sixteenth aspect of the present invention, since the cover tape having the window for exposing the surface of the semiconductor integrated circuit device to the outside is provided, the surface of the semiconductor integrated circuit device is exposed to the outside. Therefore, the laser trimming after the burn-in test and the shipping test can be easily performed through the window through the window, and the cover tape can protect the lead frame and the pad from mechanical damage.

[Brief description of drawings]

FIG. 1 is a flowchart showing a flow of manufacturing process of a first embodiment.

FIG. 2 is a flowchart showing a modified example of the manufacturing process flow of the first embodiment.

FIG. 3 is a flowchart showing a flow of manufacturing process of Example 2.

FIG. 4 is a flowchart showing a flow of manufacturing process of Example 3;

FIG. 5 is a side view showing a probe card according to a fourth embodiment.

FIG. 6 is a schematic diagram showing a configuration of a probe card according to a fifth embodiment.

FIG. 7 is a side view showing a probe card according to a sixth embodiment.

FIG. 8 is a side view showing a switching unit for switching whether or not to supply a signal, which is provided in the semiconductor integrated circuit device according to the sixth embodiment.

FIG. 9 is a side view showing a probe card according to a seventh embodiment.

FIG. 10 is a side view showing switching means for switching whether or not to supply a signal, which is provided in the semiconductor integrated circuit device according to the seventh embodiment.

FIG. 11 is a side view showing a switching unit for switching whether or not to supply a signal, which is provided in the semiconductor integrated circuit device according to the eighth embodiment.

12 is a top view showing a wafer in a state where the switching means shown in FIGS. 8 and 10 is provided in a semiconductor integrated circuit device.

FIG. 13 is a top view showing a reticle used when the switching means shown in FIGS. 8 and 10 is provided in a semiconductor integrated circuit device.

FIG. 14 is a top view showing a common wiring according to a tenth embodiment.

FIG. 15 is a top view showing a common wiring according to a tenth embodiment.

FIG. 16 is a top view showing common wiring in the eleventh embodiment.

FIG. 17 is a top view showing a switching unit according to a twelfth embodiment.

FIG. 18 is a top view showing a switching unit according to a thirteenth embodiment.

FIG. 19 is a block diagram showing the configuration of the redundant function of the present invention in the fourteenth embodiment.

FIG. 20 is a block diagram showing the configuration of the redundancy function of the present invention in the fifteenth embodiment.

FIG. 21 is a block diagram showing the configuration of the redundant function of the present invention in the sixteenth embodiment.

FIG. 22 is a waveform chart at the time of normal operation in the sixteenth embodiment.

FIG. 23 is a waveform chart at the burn-in test in the sixteenth embodiment.

FIG. 24 is a block diagram showing a burn-in mode signal generating means in the seventeenth embodiment.

FIG. 25 is a block diagram showing a burn-in mode signal generating means in the eighteenth embodiment.

FIG. 26 is a top view showing a state in which a probe is supplying a signal to the burn-in mode signal generating means in the eighteenth embodiment.

FIG. 27 is a top view showing a modification of the eighteenth embodiment of the nineteenth embodiment.

FIG. 28 is a block diagram showing the configuration of the redundant function of the present invention in the twentieth embodiment.

FIG. 29 is a flowchart showing the flow of manufacturing process in Example 21.

FIG. 30 is a top view showing a dicing process.

FIG. 31 is a side view showing a state in which the semiconductor integrated circuit device of Example 22 is arranged on a carrier tape.

FIG. 32 is a top view showing a state in which the semiconductor integrated circuit device of Example 22 is arranged on a carrier tape.

FIG. 33 is a partial enlarged view showing a state in which the semiconductor integrated circuit device in Example 22 is arranged on the carrier tape.

FIG. 34 is a cross-sectional view showing a state in which the semiconductor integrated circuit device of Example 22 is arranged on a carrier tape.

FIG. 35 is a top view showing a window provided in a cover tape in Example 23.

FIG. 36 is a block diagram showing a configuration of a conventional redundant function.

FIG. 37 is a flowchart showing the flow of a conventional manufacturing process.

FIG. 38 is a partially enlarged block diagram showing a configuration of a conventional redundant function.

FIG. 39 is a waveform diagram at the time of a conventional burn-in test.

FIG. 40 is a partially enlarged block diagram showing another configuration example of the conventional redundancy function.

[Explanation of symbols]

1 probe card, 2 probes, 3 wafers, 9
IC chip, 16 common wiring, 34 regular memory cell array, 35, 105 spare memory cell array (first redundant means), 37 spare memory cell array (second redundant means), 40 spare memory cell circuit (second redundant means) , 6
1,62 fuse, 70 carrier tape, 82,8
6 windows, 84 cover tape.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/82 27/04 21/822 (72) Inventor Satoshi Kondo 4-chome, Mizuhara Itami-shi Mitsubishi (72) Inventor Yoshiko Higashi, 4-chome, Mizuhara, Itami City Mitsubishi Electric Co., Ltd. Kita Itami Works

Claims (16)

[Claims] 1. A normal memory cell array having a plurality of memory cells, and address means electrically connected to the normal memory cell array and outputting an address signal for designating an address of a memory cell in the normal memory cell array. First redundant means electrically connected to the address means in parallel with the normal memory cell array for replacing a defective memory cell in the normal memory cell array, the first redundant means and the address means Electrically connected to the defective memory cell, the address of the defective memory cell in the normal memory cell array is pre-programmed, and when the address signal matching the address of the defective memory cell is input from the address means, the defective memory cell is The first control means for controlling so that the above is functionally replaced with the above-mentioned first redundant means. A second redundant means electrically connected to the address means in parallel with the normal memory cell array and the first redundant means, respectively, for replacing a defective memory cell in the normal memory cell array, Electrically connected to the second redundancy means and the address means, the address of the defective memory cell in the normal memory cell array is preprogrammed, and an address signal matching the address of the defective memory cell is output from the address means. A semiconductor integrated circuit device comprising: a second control means for controlling the defective memory cell so that the defective memory cell is functionally replaced with the second redundant means when input. 2. The first redundant means comprises a spare memory cell array having a plurality of spare memory cells for replacing defective memory cells in the normal memory cell array, and the second redundant means comprises: 2. The semiconductor integrated circuit device according to claim 1, comprising a spare memory cell array having a plurality of spare memory cells for replacing defective memory cells in the normal memory cell array. 3. The first redundant means comprises a spare memory cell array having a plurality of spare memory cells for replacing defective memory cells in the normal memory cell array, and the second redundant means comprises: A spare memory cell circuit having a plurality of spare memory cells for replacing defective memory cells in the normal memory cell array on a bit-by-bit basis, wherein the second control means is electrically connected to the address means. A switching control circuit in which an address of the defective memory cell in the normal memory cell array is programmed in advance; a first switching circuit electrically connected to the normal memory cell and the switching control circuit; A second switching circuit electrically connected to the cell circuit and the switching control circuit, wherein the switching control circuit is the first switching circuit. 2. The semiconductor integrated circuit device according to claim 1, wherein said switching circuit and said second switching circuit are controlled. 4. A normal memory cell array having a plurality of memory cells, and address means electrically connected to the normal memory cell array and outputting an address signal for designating an address of a memory cell in the normal memory cell array. First redundant means electrically connected in parallel to the normal memory cell array to the address means for replacing a defective memory cell in the normal memory cell array, the first redundant means and the address Means for programming the address of the defective memory cell in the normal memory cell array and inputting an address signal matching the address of the defective memory cell from the address means, the defective memory First control means for controlling the cell to be functionally replaced with the first redundant means Second redundant means electrically connected to the address means in parallel with the normal memory cell array and the first redundant means for replacing a defective memory cell in the normal memory cell array, When electrically connected to the second redundancy means, programming the address of the defective memory cell in the normal memory cell array, and inputting an address signal matching the address of the defective memory cell from the address means, A step of preparing a semiconductor integrated circuit device comprising a second control means for controlling the defective memory cell to be functionally replaced with the second redundant means; and in the first control means, A first laser trimming step of programming an address of a defective memory cell in the normal memory cell array; and burning the semiconductor integrated circuit device. And a second laser trimming step of programming the address of the defective memory cell in the memory cell array generated in the burn-in test in the second control means. Method of manufacturing circuit device. 5. A probe card having a plurality of probes for electrically contacting a semiconductor integrated circuit device and supplying a burn-in test signal in the burn-in test step is prepared, and the probe card of the probe card is used. 5. The burn-in test is performed by simultaneously supplying the burn-in test signal to a plurality of semiconductor integrated circuits.
A method for manufacturing the semiconductor integrated circuit device described. 6. In the burn-in test step, a switching means for switching whether or not to supply the burn-in test signal is prepared, and the burn-in test signal is supplied only to a semiconductor integrated circuit device selected in advance. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein a burn-in test is performed. 7. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the switching means is provided on the probe. 8. The method of manufacturing a semiconductor integrated circuit device according to claim 6, wherein the switching means is provided in the semiconductor integrated circuit device. 9. In the burn-in test step, a plurality of semiconductor integrated circuit devices are electrically connected to a common wiring pattern, and the burn-in test signal is simultaneously supplied to the plurality of semiconductor integrated circuits via the wiring pattern. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein a burn-in test is performed. 10. The method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein the wiring pattern is made of polysilicon. 11. The semiconductor device according to claim 9, further comprising switching means provided between the semiconductor integrated circuit device and the wiring pattern for switching whether or not to supply the burn-in test signal. Manufacturing method of integrated circuit device. 12. The burn-in test is performed by applying an equal load to the memory cells of the normal memory cell array, the first redundant means and the second redundant means in the burn-in test step. Item 5. A method for manufacturing a semiconductor integrated circuit device according to item 4. 13. A step of storing information on laser trimming in the first laser trimming step, wherein whether or not to repair a defective memory cell of the normal memory cell array is judged by the information in the second laser trimming step. The method of manufacturing a semiconductor integrated circuit device according to claim 4, wherein laser trimming is performed. 14. A dicing step of individually separating a plurality of the semiconductor integrated circuit devices formed on a wafer from the wafer, and the semiconductor integrated circuit devices are arranged on an insulating tape having a lead frame on a surface thereof. 5. The method of manufacturing a semiconductor integrated circuit device according to claim 4, further comprising the step of electrically connecting to the lead frame. 15. The method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein a window for exposing the surface of the semiconductor integrated circuit device to the outside is provided in the tape. 16. A step of providing an insulating cover tape having a window for exposing the surface of the semiconductor integrated circuit arranged on the tape to the outside is provided on the semiconductor integrated circuit device. The method of manufacturing a semiconductor integrated circuit device according to claim 14, wherein