JPH087596A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To make a defective group a non-selection state apparently and permanently by fixing either of a specific pair of bit of a complementary column address signal or a complementary row address signal to the prescribed logic, and making one bit correspondent to a defective row or a column group. CONSTITUTION:The one and the other of a complementary row address signal of 3 bits from a row address buffer 11 accesses respectively a memory cell array 13 and a redundant row 16 through a row decoder 12 and a redundant row decoder 16. MSB and the like of the one of this complementary row address signal is fixed to the prescribed logic by a logic fixing means 21, by making this bit correspondent to a defective row, this defective group is made permanently a non-selection state, and the defective group is apparently eliminated. A defective group is eliminated in the same way for a column. Consequently, one semiconductor memory is reproduced by combining a residual normal group and a semiconductor memory of an opposite group to the normal group.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a defect repair technique for a semiconductor memory, and more particularly to a novel and economical method for reproducing one semiconductor memory by using a normal portion of two semiconductor memories judged to be defective. Regarding technology.

[0002]

2. Description of the Related Art Generally, in a circuit portion including a large number of repetitions such as a memory cell array, a circuit having the same configuration (hereinafter referred to as "redundant circuit") is prepared in advance, and an address of the defective portion is programmed to actually perform the operation. A defect remedy is adopted in which the redundant circuit is replaced and used in place of the defective portion when the address of 1 matches the defective address.

[0003]

However, in such a general prior art, since the defective portion is replaced with the redundant circuit, the maximum number of repairable defects is determined by the size and number of the redundant circuit. For example, in the case of a memory cell array including more than the maximum number of defects and the defective portions are concentrated in a partial area of the memory cell array, in other words, when most of the memory cell array is normal. However, there was a problem that the entire chip had to be discarded as a defective product.

FIG. 10 is a diagram for explaining the problem. FIG. 10A shows the case of being processed as a non-defective product, and FIG. 10B shows the case of being processed as a defective product. For simplification, the redundant circuit (redundant memory cell array 1) is of a scale capable of repairing one column (or row; hereinafter referred to as “column”) of the memory cell array 2. In the figure, when the number of columns including a defect (marked with X) is the same as the scale of the redundant circuit 1 (one in this example), the defect can be repaired by simply replacing this column with the redundant circuit 1. However, when the number of columns including a defect exceeds the scale of the redundant circuit 1 (for example, two or two or more), only the column corresponding to the scale of the redundant circuit 1 (one column in this example) can be repaired, Since other defective columns cannot be repaired, it is unwilling to process them as defective products.

A quick countermeasure against such a problem is to increase the size of the redundant circuit 1. However, since the number of defects in the memory cell array 2 is not always large, the unnecessary increase in the size of the redundant circuit 1 is costly. However, it is not a fundamental solution.

[0006]

[Object] Therefore, an object of the present invention is to provide an economical and novel technique capable of reproducing a single semiconductor memory by combining normal portions of respective memory cell arrays of the two semiconductor memories.

[0007]

According to the first aspect of the present invention,
A column address buffer that takes in a column address signal and outputs a complementary column address signal, a row address buffer that takes in a row address signal and outputs a complementary row address signal, and a column address buffer that decodes the complementary column address signal In a semiconductor memory having a column decoder for selecting a column and a row decoder for decoding the complementary row address signal to select one row of a memory cell array, each complementary column address signal or complementary row address signal is complemented. It is characterized in that a logic fixing means capable of fixing the logic of one bit of a specific complementary bit pair having the maximum weight value among the bit pairs to a predetermined logic is provided.

According to a second aspect of the present invention, in the first aspect of the present invention, among the complementary bit pairs of the complementary column address signal or the complementary row address signal, a specific complementary bit pair having the maximum weight value is selected. It is characterized in that a logic exchanging means capable of exchanging the logic of each bit is provided.

[0009]

The designation (address designation) of the intersection of a specific column and a specific row of the memory cell array is performed by a combination of the column address signal and the row address signal. The specific column is determined by the value of the column address signal, and the specific row is determined by the value of the row address signal.

[0010] Here, a column; for convenience the number of (or row represented by the following column), assuming that eight from C ₀ to C _7, to identify a single These include 8 = 2 ^Since it is ³ , the number of bits of the column address signal is at least 3
Become a bit. Most significant bit (MSB: Most Signifi
cant Bit) is the code B ₀ , the next bit is the code B ₁ ,
The least significant bit (LSB: Least Significant Bi
If t) is represented by the symbol B ₂ , then B ₀ (and its antiphase signal) is ½ (C _{0 to} C ₃ or C) of 8 columns.
_{4 to} C ₇ ), and B ₁ (and its opposite phase signal) is further half of it, ie 1/4 (C ₀ and C
₁ , C ₂ and C ₃ , C ₄ and C ₅ or C ₆ and C ₇ ), and B ₂ (and its antiphase signal) is further half of it, ie 1/8 (C ₀ , C 7). ₁ , C ₂ , C ₃ ,
C _4, is used to specify the C _5, C ₆ or C _7).

Now, for example, if there is a defect in C ₄ of the column, this C ₄ is included in a half group of 8 columns (for convenience, G _A1 ). In other words, since the remaining half group (conveniently G _B1 ) is normal, another semiconductor memory having a defect in this group (conveniently G _B2 ) and G _B1 (in other words, G _A1 and the same group). For convenience, if a semiconductor memory having normal G _A2 ) can be combined, one normal semiconductor memory can be reproduced by using normal groups (G _B1 , G _A2 ).

To this end, the address signal may be shared between the two semiconductor memories, and the address bit (B ₀ or its reverse phase signal) for specifying the defective group of each semiconductor memory should be fixed to a predetermined logic. Good. The predetermined logic is, of course, a logic for deselecting the defective group, and is a high-level or low-level logic determined by the specifications of each semiconductor memory.

Therefore, according to the first aspect of the present invention, one bit of the specific complementary bit pair having the maximum weight value among the complementary bit pairs of the complementary column address signal or the complementary row address signal (in the above example, Since the logic of B ₀ or its negative-phase signal) can be fixed to a predetermined logic, by associating the one bit with the defective group (G _{A1 in the} above example), this defective group is permanently unselected. Can be put into a state, and the defective group can be apparently removed from the configuration. As a result, it is possible to combine the remaining normal group (G _{B1 in the} above example) with another semiconductor memory in which the opposite group (G _{A2 in the} above example) is normal. It becomes possible to reproduce one semiconductor memory by combining.

By the way, the invention according to claim 1 is different.
It is intended for combinations of groups, and the same
I am not thinking about combining groups. But always
It cannot be said that it is not only a combination of different groups
Therefore, it is insufficient in terms of flexibility of combination. Contract
In the invention described in claim 2, the identification having the maximum weight value is specified.
One bit of the complementary bit pair of
Of each bit of the same complementary bit pair.
The logic of the network is exchangeable. According to this, normal
The group is, for example, G in the above example_B1If it was
By conversion, this G_B1Virtual G_A1Treat as
You can Thus, for example, G_B1(Virtually
G_A1) And G _B2Like the same group,
It is possible to combine players and increase the flexibility of playback.
You can

[0015]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 7 are views showing a first embodiment of a semiconductor memory according to the present invention. In FIG. 1, 11 is a row
A row address buffer for fetching an address signal, 12 is a memory cell array 13 for decoding the row address signal
A row decoder for selecting a row of the memory cell array, a column address buffer 14 for capturing a column address signal, and a memory cell array 1 for decoding the column address signal.
It is a column decoder that selects 3 columns. here,
16 is a redundant row decoder, 17 is a redundant column decoder,
18 is a redundant row and 19 is a redundant column. These redundant row decoder 16, redundant column decoder 17, redundant row 18 and redundant column 19 are integrated into a redundant circuit 20.
Is composed.

The intention of the present invention is to combine the normal parts of the memory cell arrays 13 of the two semiconductor memories to reproduce one semiconductor memory. In this respect, the redundant circuit 20 is It is not a mandatory requirement. This is because even if the defect is not repaired by the redundant circuit 20, most of the memory cell array 13 can be used if the defects are concentrated in a part of the memory cell array 13 or a biased region.

Incidentally, the operation of the redundant circuit 20 is as follows. The output (complementary column address signal) of the column address buffer 14 is input to the column decoder 15 and the redundant column decoder 17. When the input address matches the defective column address programmed in the redundant column decoder 17, the redundant column 19 is selected, and at the same time, the column decoder 15 is deactivated by a predetermined signal (NED _C ) and the defective column The replacement is done. The same applies to the row relief. The row address buffer 11
Is output from the row decoder 12 (complementary row address signal).
Is input to the redundant row decoder 16. When the input address matches the defective row address programmed in the redundant row decoder 16, the redundant row 18 is selected, and at the same time, the row decoder 12 is deactivated by a predetermined signal (NED _R ) and the defective row is selected. The replacement is done.

Here, the feature of the present embodiment is that a row side logic operation circuit 21 for operating the logic of the most significant bit of the output (complementary row address signal) of the row address buffer 11,
A column-side logic operation circuit 22 for operating the logic of the most significant bit of the output (complementary column address signal) of the column address buffer 14 is provided. However, these 2
It is the best mode that the two logic operation circuits 21 and 22 have both of them, but either one may be provided. For example, when the normal portion of the memory cell array 13 is divided in row units, the row-side logical operation circuit 21 may be provided, or in the case of column units, the column-side logical operation circuit 22 may be provided. .

FIG. 2 shows the address configuration of A _{0 to} A ₂ (where A ₀ : MSB, A ₂ : LS) for simplification of description.
Row address buffer 1 with 3 bits in B)
1 is a main part configuration diagram including a logic operation circuit 21 on a row side and a row decode 12. FIG. The configuration of the corresponding portion on the column side is almost the same as this, and the row may be appropriately read as the column.

The row address buffer 11 outputs the bits A _{0 to} A ₂ of the row address signal in phase, and also outputs the anti-phase signals A _{0X to} A _{2X of the} bits A _{0 to} A ₂ (subscript X is an anti-phase). Inverting buffer gates 11 _{0 to} 11 ₂ for generating In short, the row address buffer 11 has A ₀ and A _0X , A ₁ and A _1X , A
_It outputs a complementary row address signal composed of three complementary bit pairs such as ₂ and A _2X .

The row decoder 12 has 2 ³ = 8 AND gates 12 ₀ to 1 ₀ which can be expressed by a 3-bit address signal.
Has a 2 _7, each of the AND gates 12 _0-1
The 2 _7, the combination of bit complementary address signal is input. The bit A ₀ logically operated (or not logically operated) by the logical operation circuit 21 (represented by A ₀ ′ with a dash for convenience) is input to the _four AND gates 12 _{7 to} 12 ₄ in the upper half. , Logic operation circuit 2
A bit A _0X (or, for convenience, represented by A _0X ′ with a dash) logically manipulated (or not logically manipulated) by ₁ is input to the four AND gates 12 _{3 to} 12 ₀ in the lower half and bit A ₁ is the first, third, fifth and seventh AND gates 12 ₁ , 12 ₃ , 12 ₅ , 1 from the bottom
Is input to the 2 _7, bit A _1X 0 th from the bottom, second,
4th and 6th AND gates 12 ₀ , 12 ₂ and 12
₄ and 12 ₆ , bit A ₂ is the second from the bottom, 3
Th, 6 th and 7 th AND gate 12 _2, 1
The bit A _2X is input to 2 ₃ , 12 ₆ and 12 ₇ , and the bit A _2X is the 0th, 1st, 4th and 5th AND gates 12 from the bottom.
It is input to ₀ , 12 ₁ , 12 ₄ , 12 ₅ , and after all,
Three signals of different combinations are input to the AND gates 12 _{0 to} 12 ₇ .

Outputs of the AND gates 12 _{0 to} 12 ₇ are provided with eight rows R ₀ to R _{0 of} a memory cell array (not shown).
R ₇ are connected to each other, and one row connected to any one AND gate in which all three input signals are at high level is activated (selected). FIG. 3 is a specific configuration diagram of the logic operation circuit 21 on the row side. The logic operation circuit 21 operates the logic of each bit of a specific complementary bit pair (here, complementary bit pair of A ₀ and A _0X ) having the maximum weight value among the complementary bit pairs of the complementary row address signal. It is composed of two circuits 21a and 21b having the same configuration. The first circuit 21a for operating the logic of the bit A ₀ will be described as a representative example. The program section 30a for outputting the _first program signal P ₁ which becomes a high level by a program such as fuse cutting, and the first program signal P Three-stage inverter gates 31a, 32a, 33a for transmitting ₁ while inverting each stage
When, and a transfer gate 34a and nMOS35a that turned on and off in response to the logic of the output of the second inverter gate 32a (P ₁ and phase signals). In the second circuit 21b, the same circuit elements as those of the first circuit 21a are designated by the same reference numerals (identified by the subscript b).

The transfer gates 34a / 34b are turned on when the program signals P ₁ / P ₂ are at a low level (in a non-programmed state), and pass the bits A ₀ / A _0X by the same logic (A ₀ → A). ₀ ′ / A _0X → A _0X ′), but when the program signal P ₁ / P ₂ is at high level (in the program state), it is turned off and the bit A
_It completely blocks the passage of ₀ / A _0X . On the other hand, nMOS35
a / 35b is turned off when the program signals P ₁ / P ₂ are at a low level (in a non-programmed state) and has no effect, but the program signals P ₁ / P ₂ are at a high level. At this time (in the program state), it is turned on and the logic of the bit A ₀ ′ / A _0X ′ is fixed to the ground potential (low level).

Therefore, the first circuit 21a and the second circuit 21b have a specific complementary bit pair (here, A ₀ and A _0X of the maximum weight value) of the complementary bit pairs of the complementary row address signal. Each bit of a bit pair)
It can be passed as it is or fixed at a low level according to the state of the program signals P ₁ / P ₂ , and corresponds to the logic fixing means described in the gist of the present invention.

Incidentally, FIG. 4 shows the program units 30a and 30.
It is a configuration diagram common to b and is configured by connecting a pMOS 40, a first fuse 41, a second fuse 42 and an nMOS 43 in series between a power supply V _CC and a ground potential. pMOS40 the gate of nMOS43 is connected to the ground potential, the first when the fuse 41 is cut program signal P ₁ / P ₂ is a ground potential (low level), the when cutting the second fuse 42 program signal P ₁ / P ₂ becomes the power supply potential (high level). In this embodiment, cutting the second fuse 42 is called "programming".

In the configuration as described above, the first circuit 2
It is assumed that neither 1a nor the second circuit 21b is in the programmed state. In this case, A ₀ → A ₀ ′ and A _0X → A
_0X ', and each complementary bit pair of the complementary row address signal is input to the row decoder 12 with the same logic. Now, assuming that the combination of the row address signals A ₀ , A ₁ , and A ₂ is [000 ₍₂₎ ] (0 in decimal notation), the logic of each complementary bit pair is as shown in Table 1 below.

[0027] Of these bits, the three high-level bits (A
_The AND gate input by _0X , A _1X , A _2X ) is shown in FIG.
Is the 0th AND gate ₁₂₀ . Therefore, the selected row in this case is the 0th R ₀ .

Here, the MSB of the row address signal
Let's try inverting only (A ₀ ). In this case, the combination of the row address signals A ₀ , A ₁ , and A ₂ is [100 ₍₂₎ ]
(4 in decimal notation) and the logic of each complementary bit pair is
The results are shown in Table 2 below. Of these bits, the three high-level bits (A
₀ , A _1X , A _2X ) is the AND gate input in FIG.
Is the fourth AND gate 12 ₄ . Therefore, the selected row in this case is the fourth R ₄ .

In the comparison between these two cases, the selected row is changed from the 0th (R ₀ ) to the 4th (R ₄ ) only by inverting the logic of the MSB of the row address signal. Is recognized. That is, the MS of the row address signal
B (A ₀ ) is for designating one of the groups 0 to 3 and the groups 4 to 7, and the other bits (A ₁ , A ₂ ) are designated for them. It is for indicating the position of the row in the group.

Here, one of the two circuits 21a and 21b in the logic operation circuit 21, for example, the first circuit 21a is set to the program state (only the first program signal P _{1 is set} to the high level). . 3, the transfer gate 34a of the first circuit 21a is turned off in response to P ₁ at a high level, similarly, NMOS35a of the first circuit 21a is turned on in response to the P ₁ of the high level.
Therefore, passage of one bit (A _{0 in} this example) of the complementary bit pair (A ₀ , A _0X ) having the maximum weight value through the transfer gate 34a is blocked, and at the same time, the logic operation circuit 21 is turned on by the nMOS 35a in the ON state. One output (A ₀ ′) of is fixed to the low level.

Therefore, when the above two address signal examples ([000 ₍₂₎ ] and [100 ₍₂₎ ]) are applied, the results are as shown in Tables 3 and 4 below. (Below margin) However, * indicates that the signal is fixed at a low level by the program signal P ₁ .

In Table 3, since the three bits A _0X , A _1X and A _2X are at high level, 0 is the same as in Table 1 above.
The third row R ₀ is selected, but in Table 4, A _1X and A _2X
Only the two bits are high level. Since none of the eight AND gates 12 _{0 to} 12 ₇ of the row decoder 12 selects a row unless three high-level signals are prepared, in the case of Table 4, none of the rows is non-selected. In the selected state, after all, the addressing is not performed on the memory cell array even though the address is explicitly designated.

The above example is the case where the first program signal P _{1 is set} to the high level. In this case, as long as the MSB (A ₀ ) of the row address signal is at the low level, the 0th to 3rd bits will be generated depending on the combination of the other bits (A ₁ , A ₂ ).
One of the rows up to the first row can be selected, but when the MSB of the row address signal is at high level, all rows cannot be selected regardless of the combination of other bits. In short, in this case (P ₁ = high level), 0
Only the 3rd to 3rd rows can be selected, and the remaining 4
Rows from the 7th row to the 7th row are completely in a selection prohibited state.

On the other hand, the second program signal P₂Haile
If the bell is selected, the row address signal
MSB (A₀Other bits as long as) is high
(A ₁, A₂4th to 7th, depending on the combination of
One of the rows up to
Combination of other bits when MSB is low level
All rows will not be selectable regardless of the situation. Essential
In this case (P ₂= High level) is the fourth
From the 7th to the 7th row can be selected, and the remaining 0th row
The rows from the third row to the third row are completely in the selection prohibited state.

FIG. 5 is a diagram conceptually showing such a selection section, and a frame surrounded by a solid line is an image of the storage space of the semiconductor memory. The frame is divided into upper and lower parts by broken lines,
The lower half is an area including 0th to 3rd rows (hereinafter referred to as "area A"), and the upper half is an area including 4th to 7th rows (hereinafter referred to as "area B"). First
When the program signal P ₁ of _{1 is set} to the high level, the area B is prohibited from being selected, while when the second program signal P _{2 is set} to the high level, the area A is prohibited to be selected.

Now, as shown in FIG. 6, defects are formed in different areas.
Assume two semiconductor memories of the same type including Figure 6
In the first semiconductor memory 50, the area A is defective.
Therefore, the region B of the second semiconductor memory 51 is defective. say
In other words, in the first semiconductor memory 50, the area B is normal.
Therefore, the area A of the second semiconductor memory 51 is normal. First
For semiconductor memory 50 of No. 1, select defective area A
In order to prohibit, the second program signal P₂Haile
Make it a bell. On the other hand, regarding the second semiconductor memory 51
In order to prohibit the selection of the defective area B,
Gram signal P₁To high level. And these
By combining the two semiconductor memories 50 and 51,
Common row signal, for example, the row address signal
[000 ₍₂₎ ], The second semiconductor memory 5
The 0th row in area A of 1 is selected or
The dress signal is [100₍₂₎ ], The first half
Whether the fourth row in region B of the conductor memory 50 is selected
We offer recycled products that look exactly like normal products.
Can be served.

FIG. 7 shows an example of a recycled product package. In FIG. 7A, the first semiconductor memory 50 and the second semiconductor memory 51 are stacked and the respective leads 50a and 51a are stacked.
This is a simple example of commonizing by soldering. It is preferable in that it requires no special measures, but it looks bad and is clearly a recycled product.Therefore, it has to be used only in-house, and a large amount of recycled semiconductor memory costs You can't really expect the effect of going down. On the other hand, FIG. 7B shows an example in which the first semiconductor memory and the second semiconductor memory are combined at the chip stage and then packaged. Since it can be sold outside the company, the effect of reducing the cost of the entire semiconductor memory can be expected. By the way, Figure 7
The example of (b) is a stacked package (abbreviation: SCP).
This is an application of a known packaging technology called. In this technique, the lead frames 62 and 63 are attached to the pads of the two chips 60 and 61 whose back surfaces are attached (or adhered) to each other, and then sealed with the package 64, thereby increasing the scale of the integrated circuit. Is one of the technologies that contribute to

8 to 9 are views showing a second embodiment of the semiconductor memory according to the present invention, which is an improved example of the first embodiment. In the first embodiment, as shown in FIG. 6, different regions can be combined to reproduce one semiconductor memory, but the same regions cannot be combined.

Therefore, in the second embodiment, the above-mentioned first embodiment is carried out.
To eliminate the drawbacks of the example, as shown in FIG.
Each complementary signal of the response signal (or complementary or RAM address signal).
Particular complementary bit with the highest weight value of the
(In the example, the same A as in the first embodiment is used. ₀, A_0X) Of each bit
A logic exchange circuit (logic exchange means) 70 capable of exchanging logic is provided.
I am trying to get it.

The logic exchange circuit 70 is provided between the row address buffer 11 and the row side logical operation circuit 21 of the first embodiment (or the column address buffer 14 on the column side).
Between the column and the logic operation circuit 22 on the column side).
The configuration is such that a program section 71 that outputs a _third program signal P ₃ that becomes a high level by a program such as fuse cutting, and a three-stage inverter gate that transmits the third program signal P ₃ while inverting each stage. 72,
73 and 74, and a pair of transfer gates 75 and 76 that complementarily turn on / off (if one is on, the other is off) in response to the logic of the output of the second-stage inverter gate 73 (signal in phase with P ₃ ). Similarly, a pair of transfer gates 77 and 78 that complementarily turn on / off in response to the logic of the signal in phase with P ₃ are provided.

When the program signal P ₃ is at low level (in the non-programmed state), the transfer gate 7
5, 78 are turned on, transfer gates 76, 77 are turned off, and bits A ₀ and A _0X pass through as they are. In this case, the first circuit 21a of the logic operation circuit 21 in FIG. 3 has the bit A ₀ and the second circuit 21b has the bit A _0X.
Is input, the same operation as in the first embodiment is performed.

On the other hand, when the program signal P ₃ becomes high level (in the programmed state), the transfer gates 75 and 78 are turned off, the transfer gates 76 and 77 are turned on, and the bits A ₀ and A _0X exchange destinations. Is output. In this case, contrary to the first embodiment, the bit A _0X is input to the first circuit 21a and the bit A ₀ is input to the second circuit 21b of the logic operation circuit 21 of FIG. .

Now, as shown in FIG. 9, two semiconductor memories of the same type including defects in the same region are assumed. In FIG. 9, the region B of both the first semiconductor memory 80 and the second semiconductor memory 81 is defective. In other words, the area A of both the first semiconductor memory 80 and the second semiconductor memory 81 is normal. For example, when the third program signal P ₃ of the first semiconductor memory 80 is set to the high level, the complementary bit pair (A ₀ , A
The logic of _0X ) is exchanged, whereby the arrangement of the areas A and B is virtually interchanged.

Therefore, for example, when the row address signal is set to [000 ₍₂₎ ], the 0th row in the area A of the second semiconductor memory 81 is selected or the row address signal is set to [100 _{(2 2)} ], the fourth row of B (A in the physical area) of the virtual area of the first semiconductor memory 80 is selected. Therefore, even if the same areas are combined, the appearance is normal. We will be able to offer recycled products that are completely the same as other products.

[0045]

According to the first aspect of the present invention, the logic of one bit of a specific complementary bit pair having the maximum weight value among the complementary bit pairs of the complementary column address signal or the complementary row address signal is determined. Since it can be fixed to a predetermined logic, by associating one of the bits with a defective row or column group, this defective group can be made permanently in a non-selected state. Can be removed from the composition. as a result,
The remaining normal group and the group opposite to this group can be combined with another normal semiconductor memory, and two semiconductor memories can be combined to reproduce one semiconductor memory.

According to the second aspect of the invention, in addition to the effect of the first aspect of the invention, even groups belonging to the same address area can be combined without any trouble, and the limitation of the combination can be removed to reproduce. The flexibility of can be increased.

[Brief description of drawings]

FIG. 1 is a block diagram of a main part of a semiconductor memory according to a first embodiment.

FIG. 2 is a configuration diagram including a row address buffer, a logic operation circuit, and a row decoder of the first embodiment.

FIG. 3 is a configuration diagram of a logic operation circuit according to a first embodiment.

FIG. 4 is a configuration diagram of a program unit according to the first embodiment.

FIG. 5 is a diagram conceptually showing selection categories in the first embodiment.

FIG. 6 is a reproduction image diagram of the first embodiment.

FIG. 7 is an external view or a structural diagram of the recycled product of the first embodiment.

FIG. 8 is a configuration diagram of a logic switching circuit according to a second embodiment.

FIG. 9 is a reproduction image diagram of the second embodiment.

FIG. 10 is a diagram illustrating a conventional problem.

[Explanation of symbols]

A _{0 to} A ₂ : column (or row) address signal A ₀ , A _0X , A ₁ , A _1X , A ₂ , A _2X : complementary column (or row) address signal 11: row address buffer 12: row decoder 13: Memory cell array 14: Column address buffer 15: Column decoder 21a: First circuit (logic fixing means) 21b: Second circuit (logic fixing means) 70: Logic exchange circuit (logic exchange means)

Claims (2)

[Claims] 1. A column address buffer which takes in a column address signal and outputs a complementary column address signal, a row address buffer which takes in a row address signal and outputs a complementary row address signal, and decodes the complementary column address signal. A semiconductor memory comprising: a column decoder for selecting one column of a memory cell array; and a row decoder for decoding the complementary row address signal to select one row of the memory cell array. A semiconductor memory comprising logic fixing means capable of fixing the logic of one bit of a specific complementary bit pair having the maximum weight value among the complementary bit pairs of an address signal to a predetermined logic. 2. A logic exchange means capable of exchanging the logic of each bit of a specific complementary bit pair having the maximum weight value among the complementary bit pairs of the complementary column address signal or the complementary row address signal. The semiconductor memory according to claim 1, wherein: