JPH0876730A - Image display device - Google Patents

Abstract

(57) [Abstract] [Purpose] The image data is read from the storage device that stores the image data transmitted to the receiving side through the communication line by the facsimile communication method, etc., and the reduced image of each page is displayed on the display device. Regarding the image display device that displays the original image on the display device only for the page for which you want to check the details in detail, the operation efficiency is improved, and the price is reduced by reducing the capacity of the image memory.
Aim for simplification of software. [Structure] A plurality of reduced image memories 21 to 23 for storing reduced image data for displaying a reduced image obtained by reducing an original image for one page and original image data for one page One original image memory 24 for storing
Is provided, and writing of the reduced image data to any one of the reduced image memories and reading of the reduced image data from the other one or two reduced image memories are performed.
Try to do it in parallel.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image display device suitable for use in an image communication system in which image data is transmitted.

[0002]

2. Description of the Related Art Conventionally, as an image communication system, for example, a facsimile communication system is known. On the receiving side in this facsimile communication system, image data transmitted from the transmitting side is recorded and converted to obtain image data. The original image is printed on the recording paper for each page.

However, it is not necessary to record and convert all the image data transmitted to the receiving side and print the original image on the recording paper, and it may be sufficient to print only the necessary pages.

Here, the image data transmitted to the receiving side is stored in a storage device such as a hard disk device, the stored image data is read out at an appropriate time, and the reduced image of each page is displayed on the CRT ( Display the image on a display device such as a cathode ray tube and check the original image only on the page for which you want to check the contents in detail.
It is convenient and it is possible to reduce the consumption of the recording paper by displaying it on a display device such as RT so that only the original image of the required page can be printed on the recording paper.

Therefore, the present inventor reads the image data from the storage device in which the image data transmitted to the receiving side is accumulated, displays the reduced image of each page on a display device such as a CRT, and confirms the contents in detail. Only the page you want to do, C the original image
As an image display device that can be displayed on a display device such as an RT, a device whose main part is shown in FIG. 16 has been developed.

In FIG. 16, 1 is an image memory for storing image data to be supplied to a display device such as a CRT,
Reference numerals 1a, 1b, and 1c are areas each having a capacity for storing original image data for one page.

2 is a CPU (central processing unit)
It is an image input device that inputs image data from a storage device (not shown) in which the image data transmitted to the receiving side is stored under the control of nit).

Reference numeral 3 is an address bus forming a transmission path of an address signal output from the image input apparatus 2, and 4 is a data bus forming a transmission path of image data output from the image input apparatus 2.

A display control device 5 is controlled by the CPU, supplies a display control signal to a display device such as a CRT, and controls the display of an image based on the image data stored in the image memory 1, and 6 is a display device. The address bus serves as a transmission path for an address signal output from the control device 5.

Further, 7 is controlled by a selection control signal supplied from the CPU, and selects an address signal output from the image input device 2 to the address bus 3 or an address signal output from the display control device 5 to the address bus 6. A selection circuit for supplying the image memory 1 to the image memory 1.

Reference numeral 8 is controlled by a selection control signal supplied from the CPU, and supplies image data output from the image input device 2 to the data bus 4 to the image memory 1 or outputs image data output from the image memory 1. It is a selection circuit that supplies the display device.

In this image display device, first, the image memory 1 is set to the write mode, and the original image data of the first page is written from the image input device 2 to the address bus 6 in the area 1a of the image memory 1. Address signal for output to the selection circuit 7, and the selection circuit 7 selects the address signal output from the image input device 2 to the address bus 3 and supplies it to the image memory 1.

In this case, the image input device 2 causes the data bus 4 to output the original image data of the first page, and the selection circuit 8 outputs the original image data to the data bus 4 from the image input device 2. The original image data of the first page is selected, supplied to the image memory 1, and the original image data of the first page is written in the area 1a of the image memory 1.

Next, the image memory 1 is set to the read mode, and an address signal for reading the reduced image data of the first page from the area 1a of the image memory 1 is sent from the display controller 5 to the address bus 6. The output signal is selected, and the selection circuit 7 is caused to select the address signal output from the display control device 5 to the address bus 6, and this is supplied to the image memory 1.

Further, in this case, for the selection circuit 8,
The reduced image data of the first page output from the area 1a of the image memory 1 is selected and supplied to the display device to display the reduced image of the first page on the display screen.

Next, the image memory 1 is set to the write mode, and the image input device 2 outputs an address signal for writing the original image data of the second page to the area 1b of the image memory 1 to the address bus 3. Then, the selection circuit 7 is caused to select the address signal output from the image input device 2 to the address bus 3, and this is supplied to the image memory 1.

In this case, the image input device 2 causes the data bus 4 to output the original image data of the second page, and the selection circuit 8 outputs the original image data to the data bus 4 from the image input device 2. The original image data of the second page is selected and supplied to the image memory 1, and the original image data of the second page is written in the area 1b of the image memory 1.

Next, the image memory 1 is set to the read mode, and the reduced image of the first page and the second page from the areas 1a and 1b of the image memory 1 to the address bus 6 from the display control device 5, respectively. An address signal for reading data is output, and the selection circuit 7 is caused to select the address signal output from the display control device 5 to the address bus 6, and this is supplied to the image memory 1.

Further, in this case, for the selection circuit 8,
The reduced image data of the first and second pages output from the areas 1a and 1b of the image memory 1 is selected and supplied to the display device, and the reduced images of the first and second pages are displayed on the display screen. Let

Next, the image memory 1 is set to the write mode, and the address signal for writing the original image data of the third page to the area 1c of the image memory 1 is output from the image input device 2 to the address bus 3. Then, the selection circuit 7 is caused to select the address signal output from the image input device 2 to the address bus 3, and this is supplied to the image memory 1.

In this case, the image input device 2 outputs the original image data of the third page to the data bus 4, and the selection circuit 8 is output from the image input device 2 to the data bus 4. The original image data of the third page is selected and supplied to the image memory 1, and the original image data of the third page is written in the area of the image memory 1.

Next, the image memory 1 is set to the read mode, and the display controller 5 sends the address bus 6 from the areas 1a, 1b and 1c of the image memory 1 to the first and second pages, respectively. An address signal for outputting the reduced image data of the third page is output, and the selection circuit 7 is caused to select the address signal output from the display control device 5 to the address bus 6, which is then stored in the image memory 1. Supply.

Further, in this case, for the selection circuit 8,
1 output from the areas 1a, 1b, 1c of the image memory 1
The reduced image data of the first page, the second page, and the third page are selected and supplied to the display device, and the reduced images of the first page, the second page, and the third page are displayed on the display screen.

Here, if it is desired to check the contents of the second page in detail after checking the reduced images of the first page, the second page, and the third page displayed on the display screen of the display device, From the control unit 5 to the address bus 6,
The selection circuit 7 outputs the address signal necessary for reading the original image data of the second page from the area 1b of the image memory 1.
In response to the above, the address signal output from the display control device 5 is selected and supplied to the image memory 1.

Further, in this case, for the selection circuit 8,
The original image data of the second page output from the area 1b of the image memory 1 is selected and supplied to the display device to display the original image of the second page on the display screen.

[0026]

As described above, according to this image display device, the image data is read from the storage device in which the image data transmitted to the receiving side is stored, and the reduced image of each page is displayed on the CRT or the like. It is possible to display the original image only on the page for which the content is to be displayed on the display device of which the user wants to check the contents in detail, but since only one image memory 1 is provided
Since the image input device 2 and the display control device 5 can only be operated alternately, there is a problem that the operation efficiency is low.

Also, in this image display device, the image memory 1 stores the original image data for the same number of pages as the maximum number of reduced images to be simultaneously displayed on the display screen, for example, simultaneously displayed on the display screen. When the maximum number of reduced images to be set is 3, it is necessary to provide the areas 1a to 1c for storing the original image data for 3 pages. Therefore, the capacity of the image memory 1 becomes very large, and the price can be reduced. There was a problem that it could not be planned.

Further, in this image display device, the output of the reduced image data from the image memory 1 is controlled by the display control device 5.
Since it relies on the function of, it is necessary to change the setting of the software significantly and complicated depending on whether the original image is displayed or the reduced image is displayed, and the software becomes complicated accordingly. There was a point.

In view of the above point, the present invention reads the image data from the storage device that stores the image data transmitted to the receiving side through the communication line by the facsimile communication system or the like, and displays the reduced image of each page. An image display device that displays the original image on the display device only on the page that is displayed on the device and the details of which are to be confirmed in detail.
An object of the present invention is to provide an image display device capable of reducing the price by reducing the capacity of the image memory and simplifying the software.

[0030]

An image display device according to the present invention is provided with an image memory for storing image data of an image to be displayed on a display screen. This image memory is equivalent to one page. A plurality of reduced image memories for storing reduced image data for displaying a reduced image obtained by reducing the original image and one original image memory for storing original image data for one page are provided. Is to do.

[0031]

In the present invention, the reduced image data of a plurality of pages can be displayed on the display screen by reading the reduced image data from the plurality of reduced image memories.
For a page whose contents are to be checked in detail, the original image data can be displayed by storing the original image data in the original image memory and reading the data.

By writing the reduced image data to any one of the reduced image memories and reading the reduced image data from the other one or a plurality of reduced image memories in parallel, The operation efficiency can be improved.

Further, since it is sufficient to provide the same number of reduced image memories as the maximum number of reduced images to be simultaneously displayed on the display screen and one original image memory, the capacity of the image memory can be reduced. Therefore, the price can be reduced.

When displaying a reduced image, the reduced image data is supplied from the reduced image memory to the display device,
When displaying the original image, it is sufficient to supply the original image data from the original image memory to the display device. Therefore, depending on whether the reduced image is displayed or the original image is displayed, a large and complicated software is required. The above setting need not be changed, and the software can be simplified accordingly.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, referring to FIGS. 1 to 15, an example of an image display device in which the present invention can be used as a part of a facsimile machine will be described with respect to the first and second embodiments of the present invention. And explain.

First Embodiment FIG. 1 to FIG. 8 FIG. 1 is a circuit diagram showing an essential part of the first embodiment of the present invention.
In FIG. 1, 20 is an image memory for storing image data to be supplied to a display device such as a CRT, and 21 to 23 are reductions necessary for displaying a reduced image obtained by reducing an original image for one page. A reduced image memory for storing image data, and 24 is an original image memory for storing original image data for one page. The reduced image memories 21 to 23 and the original image memory 24 are independent memories.

Further, 25 is an image input device which is controlled by the CPU and inputs image data from a storage device (not shown) in which the image data transmitted to the receiving side via the communication line is accumulated, and 26 is an image An address bus serving as a transmission path for an address signal output from the input device 25, and a data bus 27 serving as a transmission path for data output from the image input device 25.

A display control device 28 is controlled by the CPU, supplies a display control signal to a display device such as a CRT, and controls the display of an image based on the image data stored in the image memory 20 on the display device. Reference numeral 29 is an address bus which forms a transmission path of an address signal output from the display control device 28.

Further, 30 and 31 are selection circuits, and 32
Numerals 39 to 39 are three-state buffers whose active and inactive states are controlled by buffer enable signals IN1 to IN8 supplied from the CPUs, 40 to 47, respectively.
Is also a three-state buffer whose active and inactive states are controlled by buffer enable signals IN1 to IN8 supplied from the CPU.

2 to 7 are circuit diagrams for explaining an example of the operation of the first embodiment. In the first embodiment, for example, first, the reduced image memory 21 is used.
Is set to the write mode, and as shown in FIG. 2, the buffer enable signal IN2 = H level and the buffer enable signals IN1 and IN3 to IN8 = L level.

That is, the three-state buffer 33,
41 = active state, three-state buffers 32, 3
4-39, 40, 42-47 = inactive state, three-state buffer 32, 34-39, 40, 42-
The output state of 47 is a high impedance state (HiZ).

In this case, the image input device 25 causes the address bus 26 to output an address signal necessary for writing the reduced image data of the first page into the reduced image memory 21, and the address signal is three-stated. -Supply to the reduced image memory 21 via the buffer 33.

In this case, the image input device 25 outputs the reduced image data of the first page to the data bus 27, and the reduced image data of the first page is three-dimensionally output.
Reduced image memory 21 via state buffer 41
To write the reduced image data of the first page to the reduced image memory 21. In this case, nothing is displayed on the display screen 49 as shown in FIG. 8A.

Next, the reduced image memory 21 is set in the read mode and the reduced image memory 22 is set in the write mode, and the buffer enable signals IN1 and I are set as shown in FIG.
N4 = H level, buffer enable signals IN2, I
N3, IN5 to IN8 = L level.

That is, the three-state buffer 32,
35, 40, 43 = active state, three-state buffers 33, 34, 36-39, 41, 42, 44-47
= Inactive state, three-state buffer 33,
The output state of 34, 36 to 39, 41, 42, 44 to 47 is set to a high impedance state.

In this case, the display control device 28 causes the address bus 29 to output an address signal necessary for reading the reduced image data of the first page from the reduced image memory 21, and this address signal is three-dimensionally output. It is supplied to the reduced image memory 21 via the state buffer 32.

Then, the reduced image data of the first page output from the reduced image memory 21 is three-stated.
It is supplied to the display device via the buffer 40, and the reduced image 50 of the first page is displayed on the display screen 49 as shown in FIG. 8B.

In parallel with this operation, the image input device 25 causes the address bus 26 to output an address signal necessary for writing the reduced image data of the second page into the reduced image memory 22. The address signal is supplied to the reduced image memory 22 via the three-state buffer 35.

Further, in this case, the image input device 25 outputs the reduced image data of the second page to the data bus 27, and the reduced image data of the second page is three-dimensionally output.
Reduced image memory 22 via state buffer 43
And writes the reduced image data of the second page to the reduced image memory 22.

Next, with the reduced image memory 21 set in the read mode, the reduced image memory 22 is set in the read mode and the reduced image memory 23 is set in the write mode, and the buffer enable is set as shown in FIG. Signals IN1 and I
N3, IN6 = H level, buffer enable signal I
N2, IN4, IN5, IN7, IN8 = L level.

That is, the three-state buffer 32,
34, 37, 40, 42, 45 = active state, three-state buffers 33, 35, 36, 38, 39, 4
1, 43, 44, 46, 47 = inactive state, three-state buffers 33, 35, 36, 38, 39,
The output state of 41, 43, 44, 46, 47 is set to a high impedance state.

In this case, from the display control device 28 to the address bus 29, from the reduced image memories 21 and 22,
An address signal necessary for reading the reduced image data of the first and second pages is output, and this address signal is supplied to the reduced image memories 21 and 22 via the three-state buffers 32 and 34. To do.

Then, the reduced image data of the first and second pages output from the reduced image memories 21 and 22 are supplied to the display device via the three-state buffers 40 and 42, as shown in FIG. 8C. On the display screen 49
The reduced images 50 and 51 of the second page are displayed.

In parallel with this operation, the image input device 25 causes the address bus 26 to output an address signal necessary for writing the reduced image data of the third page into the reduced image memory 23. The address signal is supplied to the reduced image memory 23 via the three-state buffer 37.

In this case, the image input device 25 outputs the reduced image data of the third page to the data bus 27, and the reduced image data of the third page is three-dimensionally output.
Reduced image memory 23 via state buffer 45
And writes the reduced image data of the third page to the reduced image memory 23.

Next, the reduced image memory 23 is set to the read mode while the reduced image memories 21 and 22 are set to the read mode, and the buffer enable signals IN1, IN3 and IN5 =, as shown in FIG. H level, buffer enable signals IN2, IN4, IN6 to IN8 =
Set to L level.

That is, the three-state buffer 32,
34, 36, 40, 42, 44 = active state, three-state buffers 33, 35, 37 to 39, 41, 4
3, 45-47 = inactive state, three state
Buffers 33, 35, 37-39, 41, 43, 45-
The output state of 47 is a high impedance state.

In this case, the reduced image memories 21, 22, 23 are sent from the display control device 28 to the address bus 29.
Output the address signals necessary for reading the reduced image data of the first page, the second page, and the third page, respectively, and reduce the address signals via the three-state buffers 32, 34, 36. Image memory 21,
22 and 23 are supplied.

Then, the reduced image memories 21, 22, 2
The reduced image data of the first page, the second page, and the third page output from the three-state buffer 40,
It supplies to the display device via 42 and 44, and as shown in FIG. 8D, the reduced images 50, 51 and 52 of the first page, the second page and the third page are displayed on the display screen 49.

Next, the reduced images 50, 5 of the first, second, and third pages displayed on the display screen 49.
If there is an original image to be displayed among 1, 52, the selecting operation is performed.

Here, for example, when it is selected to display the original image of the second page, the original image memory 24 is displayed.
Is set to the write mode, and the buffer enable signal IN8 = H level and the buffer enable signals IN1 to IN7 = L level are set as shown in FIG.

That is, the three-state buffer 39,
47 = active state, three-state buffers 32-3
8, 40-46 = inactive state, three state
The output states of the buffers 32 to 38 and 40 to 46 are set to the high impedance state.

In this case, the image input device 25 causes the address bus 26 to output an address signal necessary for writing the original image data of the second page into the original image memory 24, and this address signal is three-stated. The data is supplied to the original image memory 24 via the buffer 39.

Further, in this case, the image input device 25 causes the data bus 27 to output the original image data of the second page, and the original image data of the second page is transmitted via the three-state buffer 47 to the original image data. The image data is supplied to the image memory 24, and the original image data of the second page is written in the original image memory 24.

Next, the original image memory 24 is set to the read mode, and as shown in FIG. 7, the buffer enable signal IN7 = H level, the buffer enable signal IN1.
~ IN6, IN8 = L level.

That is, the three-state buffer 38,
46 = active state, three-state buffers 32-3
7, 39, 40-45, 47 = inactive state, three-state buffers 32-37, 39, 40-45,
The output state of 47 is a high impedance state.

In this case, the display control device 28 causes the address bus 29 to output an address signal necessary for reading the original image data of the second page from the original image memory 24, and the address signal is three-dimensionally output. It is supplied to the original image memory 24 via the state buffer 38.

Then, the original image data of the second page output from the original image memory 24 is supplied to the display device via the three-state buffer 46, and as shown in FIG. The original image 53 of the page is displayed.

The case where the reduced images of the first to third pages are displayed and then the original image of the second page is displayed has been described above. However, the original image of the first page and the third page are displayed. It is needless to say that the original image can be displayed, and the display of the fourth and subsequent pages can be similarly performed.

In this way, in the first embodiment, the image data is read from the storage device in which the image data transmitted to the receiving side through the communication line is stored, and the reduced image of each page is displayed on the display device. The original image can be displayed only on the page which is displayed on the screen 49 and whose contents are to be confirmed in detail.

Here, in the first embodiment, the image input device 25 and the display control device 28 are simultaneously operated,
The reduced image data can be read and the reduced image data can be written at the same time, so that the operation efficiency can be improved.

Further, as the image memory 20, the display screen 4
9, the same number of reduced image memories as the maximum number of reduced images to be displayed simultaneously, for example, when the maximum number of reduced images to be simultaneously displayed on the display screen 49 is 3, three reduced image memories 21 and 22 are displayed. , 23 and one original image memory 24
Since it is sufficient to provide and, the capacity of the image memory 20 can be reduced, and the cost can be reduced.

When a reduced image is displayed, the reduced image data is supplied from the reduced image memories 21, 22, 23 to the display device, and when the original image is displayed, the original image memory 24 is used. Since it is sufficient to supply the image data to the display device, it is not necessary to change the setting on the software significantly or complicated depending on whether the reduced image is displayed or the original image is displayed. It can be simplified.

Second Embodiment FIG. 9 to FIG. 15 FIG. 9 is a circuit diagram showing a main part of the second embodiment of the present invention.
In the second embodiment, an address thinning circuit 55 is provided between the address bus 26 and the three-state buffers 33, 35 and 37, and the data bus 27 and the three-state buffers 41, 43 and 45 are connected. A data thinning circuit 56 is provided between them, and the rest is configured similarly to the first embodiment shown in FIG.

The address thinning circuit 55 thins out a predetermined address signal from the address signal to be supplied to the original image memory 24 to reduce the reduced image memories 21, 22, 23.
It outputs an address signal to be supplied to.

Further, the data thinning circuit 56 thins out the original image data at the address designated by the predetermined address signal from the original image data to be supplied to the original image memory 24, and stores it in the reduced image memories 21, 22, 23. The reduced image data to be supplied is output.

10 to 14 are circuit diagrams for explaining an example of the operation of the second embodiment. In the second embodiment, for example, first, the reduced image memory 21 and Set the original image memory 24 to the write mode,
As shown in FIG. 10, the buffer enable signal IN
2, IN8 = H level, buffer enable signal IN
1, IN3 to IN7 = L level.

That is, the three-state buffer 33,
39, 41, 47 = active state, three-state buffers 32, 34-38, 40, 42-46 = inactive state, three-state buffers 32, 34-38,
The output states of 40 and 42 to 46 are set to the high impedance state.

In this case, the image input device 25 causes the address bus 26 to output an address signal necessary for writing the original image data of the first page into the original image memory 24, and the address signal is set to three-state. The data is supplied to the original image memory 24 via the buffer 39.

Further, in this case, the original image data of the first page is output from the image input device 25 to the data bus 27, and the original image data of the first page is output via the three-state buffer 47. The image data is supplied to the image memory 24, and the original image data of the first page is written in the original image memory 24.

In this case, the address signal output from the image input device 25 to the address bus 26 is thinned out by the address thinning circuit 55 and supplied to the reduced image memory 21 via the three-state buffer 33. It

Further, 1 output from the image input device 25
The original image data of the page is thinned out by the data thinning circuit 56 to form reduced image data of the first page, which is supplied to the reduced image memory 21 via the three-state buffer 41 and supplied to the reduced image memory 21. The reduced image data is written in the reduced image memory 21. In this case, in FIG.
As shown in 5A, nothing is displayed on the display screen 49.

Next, the reduced image memory 21 is set to the read mode, and as shown in FIG. 11, the buffer enable signal IN1 = H level, the buffer enable signal I
N2 to IN8 = L level.

That is, the three-state buffer 32,
40 = active state, three-state buffers 33 to 3
9, 41-47 = inactive state, 33-39, 41-
The output state of 47 is a high impedance state.

In this case, the display control device 28 causes the address bus 29 to output an address signal necessary for reading the reduced image data of the first page from the reduced image memory 21, and the address signal is three-dimensionally output. It is supplied to the reduced image memory 21 via the state buffer 32.

Then, the reduced image data of the first page output from the reduced image memory 21 is three-stated.
It is supplied to the display device via the buffer 40, and the reduced image 50 of the first page is displayed on the display screen 49 as shown in FIG. 15B.
Is displayed.

Here, the original image of the first page is displayed on the screen 4
When it is not necessary to display the image on the screen 9, the reduced image memory 21 and the original image memory 24 are set to the write mode while the reduced image memory 21 is set to the read mode.

Then, as shown in FIG.
Enable signals IN1, IN4, IN8 = H level, buffer enable signals IN2, IN3, IN5-IN
7 = L level.

That is, the three-state buffer 32,
35, 39, 40, 43, 47 = active state, three-state buffers 33, 34, 36-38, 41, 4
2, 44-46 = inactive state, 33, 34, 36-
The output state of 38, 41, 42, 44 to 46 is set to the high impedance state.

In this case, the display controller 28 causes the address bus 29 to output an address signal necessary for reading the reduced image data of the first page from the reduced image memory 21, and the address signal is three-dimensionally output. It is supplied to the reduced image memory 21 via the state buffer 32.

Then, the reduced image data of the first page output from the reduced image memory 21 is three-stated.
It is supplied to the display device via the buffer 40, and the reduced image 50 of the first page is displayed on the display screen 49 as shown in FIG. 15B.
Is displayed continuously.

In parallel with this operation, the image input device 25 causes the address bus 26 to output an address signal required for writing the original image data of the second page into the original image memory 24. The address signal is sent through the three-state buffer 39 to the original image memory 24.
Supply to.

In this case, the original image data of the second page is output from the image input device 25 to the data bus 27, and the original image data of the second page is output via the three-state buffer 47. The image data is supplied to the image memory 24, and the original image data of the second page is written in the original image memory 24.

In this case, the address signal output from the image input device 25 is thinned out by the address thinning circuit 55 and supplied to the reduced image memory 22 via the three-state buffer 35.

In addition, 2 output from the image input device 25
The original image data of the page is thinned out by the data thinning circuit 56 to be reduced image data of the second page, supplied to the reduced image memory 22 via the three-state buffer 43, and supplied to the reduced image memory 22. The reduced image data of is written in the reduced image memory 22.

Next, with the reduced image memory 21 set in the read mode, the reduced image memory 22 is set in the read mode, and as shown in FIG. 13, the buffer enable signals IN1, IN3 = H level, buffer -Enable signals IN2 and IN4 to IN8 = L level.

That is, the three-state buffer 32,
34, 40, 42 = active state, three-state buffer 33, 35-39, 41, 43-47 = inactive state, three-state buffer 33, 35-39,
The output state of 41, 43 to 47 is set to a high impedance state.

In this case, from the display control device 28 to the address bus 29, from the reduced image memories 21 and 22,
An address signal necessary for reading the reduced image data of the first and second pages is output, and this address signal is supplied to the reduced image memories 21 and 22 via the three-state buffers 32 and 34. To do.

Then, the reduced image data of the first and second pages output from the reduced image memories 21 and 22 are supplied to the display device via the three-state buffers 40 and 42, and as shown in FIG. 15C. On the display screen 49,
The reduced images 50 and 51 of the first and second pages are displayed.

If the user wants to display the original image of the second page after checking the display screen 49 shown in FIG. 15C,
The original image memory 24 is set to the read mode, and as shown in FIG. 14, the buffer enable signal IN7 = H level and the buffer enable signals IN1 to IN6, IN8.
= L level.

That is, the three-state buffer 38,
46 = active state, three-state buffers 32-3
7, 39, 40-45, 47 = inactive state, three-state buffers 32-37, 39, 40-45,
The output state of 47 is a high impedance state.

In this case, the display control device 28 causes the address bus 29 to output an address signal necessary for reading the original image data of the second page from the original image memory 24, and the address signal is three-dimensionally output. It is supplied to the original image memory 24 via the state buffer 38.

Then, the original image data of the second page output from the original image memory 24 is supplied to the display device via the three-state buffer 46, and as shown in FIG. The original image 53 of the page is displayed.

Hereinafter, the reduced image memory 21 and the original image memory 24 are set to the write mode, the reduced image of the third page is written in the reduced image memory 21, and the third image of the third page is written in the original image memory 24. The original image is written, and the reduced image 5 of the third page is displayed on the display screen 49 as shown in FIG. 15E.
2 is displayed, and if necessary, the original image on the third page is displayed. The same can be applied to the display of the fourth and subsequent pages.

As described above, in the second embodiment, the image data is read from the storage device in which the image data transmitted to the receiving side via the communication line is accumulated, and the reduced image of each page is displayed on the display device. It is possible to display the original image only on the page displayed on the display screen 49 of FIG.

However, in the second embodiment, unlike the case of the first embodiment, the original image data of the last displayed reduced image among the reduced images displayed on the display screen 49 is the original image data. The original image data stored in the memory 24 is supplied to the display device when necessary.

According to the second embodiment, as in the case of the first embodiment, the image input device 25 and the display control device 28 are simultaneously operated to read out reduced image data.
Since the reduced image data can be written at the same time, the operation efficiency can be improved.

As the image memory 20, as in the case of the first embodiment, the same number of reduced image memories as the maximum number of reduced images to be simultaneously displayed on the display screen 49, for example, reduced images to be simultaneously displayed on the display screen 49. When the maximum number of images is three, three reduced image memories 21, 22, 23
Since it suffices to provide one original image memory 24, the capacity of the image memory 20 can be reduced, and the cost can be reduced.

Further, as in the case of the first embodiment, when displaying a reduced image, the reduced image memories 21, 22,
When the reduced image data is supplied from 23 to the display device and the original image is displayed, it is sufficient to supply the original image data from the original image memory 24 to the display device. Therefore, the reduced image is displayed or the original image is displayed. Depending on the display, it is possible to simplify the software by not requiring a large and complicated software setting change.

Further, in particular, according to the second embodiment, unlike the first embodiment, the reduced image memories 21, 2 are provided.
Since the address decimating circuit 55 and the data decimating circuit 56 are provided to generate the address signal and the image data to be supplied to Nos. 2 and 23 by hardware, the software is more than the case of the first embodiment. Can be simplified.

In the first or second embodiment, the reduced image memories 21, 22 and 23 are used as original image memories, and the original image memory 24 is used as reduced image memory. Is also possible.

[0112]

As described above, according to the present invention, the image memory includes a plurality of reduced image memories for storing reduced image data for displaying a reduced image obtained by reducing an original image for one page. And the original image memory for storing the original image data for one page are provided, the operation efficiency is improved, the price is reduced by reducing the capacity of the image memory, and the software is simplified. can do.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a main part of a first embodiment of the present invention.

FIG. 2 is a circuit diagram for explaining an example of the operation of the first exemplary embodiment of the present invention.

FIG. 3 is a circuit diagram for explaining an example of the operation of the first exemplary embodiment of the present invention.

FIG. 4 is a circuit diagram for explaining an example of the operation of the first exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram for explaining an example of the operation of the first exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram for explaining an example of the operation of the first exemplary embodiment of the present invention.

FIG. 7 is a circuit diagram for explaining an example of the operation of the first exemplary embodiment of the present invention.

FIG. 8 is a diagram showing a state of a display screen in the case of an example of the operation of the first exemplary embodiment of the present invention.

FIG. 9 is a circuit diagram showing a main part of a second embodiment of the present invention.

FIG. 10 is a circuit diagram for explaining an example of the operation of the second exemplary embodiment of the present invention.

FIG. 11 is a circuit diagram for explaining an example of the operation of the second exemplary embodiment of the present invention.

FIG. 12 is a circuit diagram for explaining an example of the operation of the second exemplary embodiment of the present invention.

FIG. 13 is a circuit diagram for explaining an example of the operation of the second exemplary embodiment of the present invention.

FIG. 14 is a circuit diagram for explaining an example of the operation of the second exemplary embodiment of the present invention.

FIG. 15 is a diagram showing a state of a display screen in the case of an example of the operation of the second exemplary embodiment of the present invention.

FIG. 16 is a circuit diagram showing an example of an image display device.

[Explanation of symbols]

 (FIG. 1) 32-47 three-state buffer IN1-IN8 buffer enable signal

Claims (4)

[Claims] 1. An image display device comprising an image memory for storing image data of an image to be displayed on a display screen, wherein the image memory displays a reduced image obtained by reducing an original image for one page. Image display characterized by comprising a plurality of reduced image memories for storing reduced image data for display and one original image memory for storing original image data for one page apparatus. 2. A reduced image data write operation to any one reduced image memory among the plurality of reduced image memories, and reduced image data from another one or a plurality of reduced image memories. 2. The image display device according to claim 1, further comprising a predetermined circuit which enables the reading operation and the reading operation in parallel to be performed in parallel. 3. The predetermined circuit, for each of the reduced image memory and the original image memory, inputs a write address signal and image data, and a read address signal and image. The image display device according to claim 2, further comprising a selection circuit that enables a selection operation with respect to output of data. 4. An address thinning circuit for thinning a predetermined address signal from an address signal to be supplied to the original image memory and outputting an address signal to be supplied to the reduced image memory, and the original image memory. A data thinning circuit for thinning out original image data corresponding to an address designated by the predetermined address signal from the original image data to be supplied and outputting reduced image data to be supplied to the reduced image memory is provided, and the same page For the image data, the writing operation of the original image data to the original image memory and the writing operation of the reduced image data to the selected reduced image memory among the plurality of reduced image memories are performed in parallel. The image display device according to claim 1, 2 or 3, wherein the image display device is capable of performing the above-mentioned operation.