JPH087677B2 - Micro-program branch control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding control of a microprogram that performs a process related to execution of an instruction having a sub-operation code, the same microprogram related to the processing of an instruction having a sub-operation code is duplicated in the control storage. For the purpose of effectively using the control storage by eliminating the existence inside, there is provided an area for storing the information for instructing the branch corresponding to each microprogram step of the control storage, and the sub operation code is different. Structured by providing means for processing a part of control related to execution of instructions by a common microprogram, and means for branching to an address on the control storage corresponding to the sub-operation code of the instruction when the information is detected To do.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to control of a microprogram of an information processing apparatus configured to perform processing related to execution of instructions by a microprogram, and particularly, to the control of the microprogram when the instruction is accompanied by a sub-operation code. Subject to restrictions.

[Prior Art] Operations such as reading, decoding, and execution of instructions in an information processing apparatus are performed by basic operations such as access to main memory, data loading into registers, data shifting, and input / output to adders. It is realized by the combination.

The processing of decomposing an instruction into such basic operations and executing them can also be realized by a logic circuit, but can be performed by a program (microprogram) specializing in basic operations. And
Many types of information processing apparatuses of this type are made because it is easy to take measures such as changing operations.

On the other hand, in recent years, in order to increase the processing speed and functionality of the information processing apparatus, realization of multifunctional instructions is required, and the number of instructions is required to be increased.

When the number of instructions increases in this way, the number of bits allocated to the conventional instruction (operation code) becomes insufficient. Therefore, in the case of a specific instruction code, a sub-operation code is added to this and the instruction code is further added. A plurality of different instructions are newly created.

[Problems to be Solved by the Invention] Conventionally, regarding an instruction having a sub-operation code, an instruction having a sub-operation code or an instruction having a sub-operation code is divided into groups and a start address of a microprogram is determined and arranged. The method of executing the operation from each top address was adopted. Regarding the processing of an instruction having a sub-operation code, there are quite a few parts which perform the same micro-steps even if they are different sub-operations. For example, as shown in FIG. 4, #A, #B, The microsteps of the instruction having each sub-operation code indicated by #C are exactly the same between M-00, M-01, and M-02, and different microsteps (M-A0, M-B) are performed after these processes.
0, M-C0).

Conventionally, even in such a case, the start address of the microprogram is determined for each sub-operation code and placed on the control storage.

According to the present invention, it is possible for instructions having different sub-operation codes to commonly use a portion for performing processing by the same microprogram as described above, and the same microprogram is duplicately present in the control storage. It is an object of the present invention to provide a microprogram control method that can effectively use the control storage area while avoiding the above.

[Means for Solving the Problems] According to the present invention, the above-mentioned object is achieved by the means described in the claims. That is, the present invention is
In an information processing device configured to perform control related to execution of instructions by a microprogram and having an instruction code accompanied by a sub-operation code, a branch is instructed corresponding to each microprogram step of a control storage for storing the microprogram. And a means for processing a part of the control relating to the execution of instructions having different sub-operation codes by a common micro-program, and corresponding to the sub-operation code of the instruction when the information is detected. This is a micro-program branching control system provided with means for branching to an address on the control storage.

[Operation] FIG. 1 is a diagram for explaining the principle of the present invention. Reference numeral 1 denotes a register for setting an instruction code. The instruction code is set in 1a and the sub-operation code is set in 1b.

Further, 2 is a selector, 3 is a CS address selection control unit, 4
Is a CS address register, 5 is a control storage (hereinafter, also referred to as CS), 6 is an area for displaying a branch instruction, and 7 is a CS data register of an instruction execution unit.

In the figure, when the instruction code and sub-operation code are first set in the register 1, the CS address selection controller 3 selects the instruction code by the selector 2 and the corresponding address on the CS is the CS address register. Set to 4.

Then, the control storage (CS) is accessed by the address and the instruction is executed by reading the microprogram. The microsteps constituting the microprogram are read by the next address information of the immediately preceding microstep. At this time, while the microprogram is being read, a branch instruction is displayed in the area 6 corresponding to the read microstep (for example, "1. "), It is transmitted to the CS address selection control unit 3, and the CS address selection control unit 3 instructs the selector 2 to select the sub-operation code 1b.

As a result, the selector 2 causes the sub-operation code
1b is selected, and the address corresponding to the sub-operation code is set in the CS address register 4.

Then, an instruction execution operation peculiar to the sub-operation code is performed by accessing the area of the address of CS.

In the present invention, among the instructions having different sub-operation codes due to the above operation, when there is a common part in the processing of the microprogram, it is not necessary to arrange all of them in CS for each sub-operation, and the same After the common use of the micro programs of, it is possible to branch from the necessary place, so that the CS area can be used effectively.

[Embodiment] FIG. 2 is a block diagram of an embodiment of the present invention, showing a CS address control system of a microprogram control instruction processing device, 8 is an instruction control unit, and 9 is a CS address selection circuit. Section, 10 is a selector, 11 is a CS address register, 12 is a control storage, 13 is a branch display area, 14 is an instruction execution section, 15 is a CS data register, and 16 is a decoder.

In the figure, the instruction control unit 8 fetches an instruction and decodes an instruction code.

The selector 10 is controlled by the CS address selection circuit section to have an instruction code or sub-operation code, or
An address based on the next address information of CS data is selected and set in the CS address register 11. When the processing of one instruction is completed, the address corresponding to the instruction code is always selected as the next first CS address. Then, the microprogram having the address as the leading address is sequentially read from the control storage 12 and processed by the instruction executing unit 14.

When the CS address selection circuit section 9 knows that "1" has been read from the branch display area 13 when reading the microstep, it instructs the selector 10 to select the sub-operation code. As a result, the selector 10 selects the sub-operation code and sets the address corresponding to it in the CS address register 11.

For example, the CS address is 12 bits and the instruction code is X '.
When it is 81, X'081 is set in the CS address register 11 regardless of the sub-operation code even if it is an instruction with the sub-operation code.

As a 1-byte sub-operation code, X '
Since there are 256 patterns from 00 to X'FF, the instruction code is X'8
There are 256 possible 1'instructions, X'8100 to X'81FF. However, even if the sub-operation code is different, if the instruction code is X'81, X'081 is set in the address register and the CS address is X'081.
We will read the micro steps of.

Here, when "0" is displayed in the branch display area for the micro step of X'081, the CS address selection circuit unit 9 controls the selector 10 to set the next address in the CS address register 11. Therefore, the next microstep is read by the next address. After that, while the branch display area is "0", the microstep reading by the next address is repeated.

When it is detected that "1" is displayed in the branch display area of the microstep read from the control storage 12, the CS address selection circuit unit 9 is thereby detected.
Instructs selector 10 to select a sub-operation code.

At this time, if the sub-operation code is X'83 (that is, the code of the entire instruction is X'8183), it is stored in the CS address register, for example, X'83 to X'800.
It operates so that X'883, which is a value obtained by adding, is set.

FIG. 3 is a diagram for explaining the state of such operation.
#B and #C indicate instructions having different sub-operation codes.

In the figure, since the instruction codes are the same for #A, #B, and #C, and the microsteps between M-00 to M-02 are common, the microsteps of M-00 are always first. Is selected and processing starts. And the M shown with numeral 17
At step -02, "1" is set in the branch display area 13 of the control storage 12.

As a result, the instruction #A is microstep M-A0.
Instruction #B branches to microstep M-B0, and instruction #C branches to microstep M-C0.

In the conventional method, in such a case, the microsteps M-00 to M-02 need to have the instructions #A, #B, and #C on the CS, respectively. If
As described above, since it is sufficient to have one set of micro steps M-00 to M-02, the required area of the control storage can be reduced.

Although FIG. 3 illustrates a case where three instructions share three-step micro-instructions for ease of explanation, in reality, more instructions share many micro-steps. Therefore, it is possible to significantly improve the use efficiency of the control storage area.

[Effects of the Invention] As described above, according to the present invention, in the processing related to the execution of the instruction having the sub-operation code,
Effective use of the area of the control storage because it is not necessary to have a part of the microprogram that performs a common operation in the control storage for each different instruction, and different instructions can easily use one set of microprograms. There is an advantage that can be.

[Brief description of drawings]

FIG. 1 is a diagram for explaining the principle of the present invention, FIG. 2 is a block diagram of an embodiment of the present invention, FIG. 3 is a diagram for explaining the operation of the embodiment, and FIG. 4 is an instruction by a conventional microprogram. It is a figure explaining execution of. 1 ... Register, 2,10 ... Selector, 3 ... CS address selection controller, 4,11 ... CS address register, 5,12 ... Control storage, 6,13 ... Branch display area, 7,15 …
... CS data register, 8 ... instruction control section, 9 ... CS address selection circuit section, 14 ... instruction execution section, 16 ... decoder,
17 ... Micro step

Front page continuation (72) Inventor Masato Tanaka 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa, Fujitsu Limited (72) Inventor Yoshihiro Mizushima 1015, Kamedotachu, Nakahara-ku, Kawasaki, Kanagawa (56) Reference Reference JP-A-60-105044 (JP, A)

Claims (1)

[Claims] 1. An information processing apparatus having an instruction code accompanied by a sub-operation code, which is configured to control an instruction execution by a micro program, and corresponds to each micro program step of a control storage for storing the micro program. An area for storing information for instructing branching is provided at least, and a means for causing a common microprogram to process a part of the control relating to the execution of instructions having different sub-operation codes, and a sub-command of the instruction when the information is detected. A micro-program branching control method comprising means for branching to an address on a control storage corresponding to an operation code.