JPH087743B2 - Command controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] The present invention relates to an access pipeline of a vector processing device,
Or, in the instruction control of the operation pipeline, in order to reduce the empty timing of the pipeline, the number of stages of the management register is set to the number of cycles from the time the pipeline is activated to the writing to the vector register and the access to the bank of the vector register. It is configured with an optimum number of stages obtained from the timing cycle, which enables effective use of the pipeline.

[Industrial application field]

The present invention relates to an instruction control device in a pipeline of a vector processing device.

The vector processing device is a processing device capable of executing a large amount of scientific and technological calculations, particularly matrix operations at high speed, and uses a pipeline method in which processing units are finely divided and sequentially processed in a flow work method.

The vector processing device is required to increase the processing speed more and more, first of all, it is necessary to operate each pipeline without interruption. For that purpose, an instruction control device that supplies instructions to the pipeline without interruption is required.

[Conventional technology]

FIG. 3 is a block diagram showing a configuration of a conventional example, in which parts relevant to the present invention are extracted and shown from the vector processing device and the main memory.

In the figure, reference numeral 1 denotes an access pipeline having one or a plurality of access pipelines, a main memory unit including a main memory unit (MSU) and a main memory control unit (MCU), and a high-speed operation vector register for storing vector data. Transfers data to and from (VR) 2.

Reference numeral 3 denotes an operation pipeline having one or a plurality of operations, which performs an operation while reading data from the vector register (VR) 2 and writes the result in the vector register (VR) 2.

Reference numeral 4 is a management register for the access pipeline 1, and 5 is a management register for the operation pipeline 3.

These management registers 4 and 5 are provided in an instruction control unit (not shown), and correctly grasp the state of each pipeline 1 and 3 corresponding to each, and optimize the instruction input and execution in each pipeline 1 and 3. Used to The arrow from the management register 4 to the access pipeline 1 and the arrow from the management register 5 to the operation pipeline 3 in FIG. 3 show the corresponding relationships.

Conventionally, the management registers 4 and 5 include an R stage indicating that the pipeline is reading data, an S stage indicating that data is being transferred or an operation is being performed, and a data or operation result vector register. It was composed of three stages, the W stage indicating that (VR) 2 was being written.

In the R stage, the value is held after the instruction is input to the management register until at least the reading of the data is completed, and the value is kept held until the value transits to the S stage.

In the S stage, the value received from the R stage is held until the writing of the vector register is started.

When writing to the vector register is started, the instruction of the S stage transits to the W stage, and the S stage is in a state of accepting a new instruction.

In the W stage, the value is kept held until the writing to the vector register is completed.

FIG. 4 is a time chart showing the operation status of the management register according to the conventional example. The operation of the pipeline and management register is as follows.

First, when the first instruction A is input to the R stage, data is read out, and in the initial state, the S stage is empty, so the data is immediately moved to the S stage and held until the operation or the data transfer with the main memory is completed. To be done. The instruction B is input to the R stage in the next cycle.

In the S stage, when the operation of the instruction A or the data transfer is completed, the instruction A is transited to the W stage, the S stage can accept the next instruction B, and the instruction B moves from the R stage to the S stage.
Transition to the stage.

At the W stage, the data of the instruction A is written to the vector register, and when this is finished, the instruction B can be accepted, the instruction B is transited, and the data of the instruction B is written.

In the S stage, the instruction C is transited after the instruction B is transited, the arithmetic operation or data transfer of the instruction C is performed, and the operation is held until the end. That is, the instruction C is put into the S stage only after the writing of the data of the instruction A is finished and the instruction B is transited from the S stage to the W stage to start the operation or data transfer, and is held until the end.

Therefore, the instruction C is transitioned to the W stage and the data is written only after the operation or the data transfer in the S stage is completed, so that the instruction that may be continuously executed is intermittently executed as shown in the figure. To be done.

[Problems to be solved by the invention]

As described above, in the conventional configuration, the instructions that may be continuously executed may have a vacancy in the pipeline due to the limitation of the number of stages of the management register, and the pipeline may not be effectively used. Was there.

The present invention is intended to provide a novel instruction control device which solves the above-mentioned conventional problems.

[Means for solving problems]

FIG. 1 shows a principle block diagram of the instruction control device of the present invention.

In FIG. 1, the same symbols as those in FIG. 3 indicate the same objects.

The management registers 4 and 5 in FIG. 1 are also in the instruction control unit (not shown) as in FIG. 3 used in the description of the conventional example, and the states in the corresponding pipelines 1 and 3 are correctly grasped. Then, it is used to optimize the input and execution of instructions in each pipeline 1, 3. The arrow from the management register 4 to the access pipeline 1 and the arrow from the management register 5 to the operation pipeline 3 in FIG.
Similar to the figure, the respective correspondences are shown.

The management register 4 for the access pipeline 1 has a cycle of the access timing of the bank of the vector register 2 as T, and from the start time of the access pipeline 1 determined by a plurality of instructions of the same type to the start of writing to the vector register 2. When the access timing time is N ₁ , the number of stages P ₁ is expressed by the following equation (1) or (2).

P ₁ = N ₁ / T + 1 (1) (when N ₁ / T is an integer) P ₁ = [N ₁ / T] +2 (2) (When N ₁ / T is not an integer, here [ ] Is a Gaussian symbol and indicates the nearest integer that does not exceed the quotient in [].) Regarding the management register 5 for the arithmetic pipeline 3,
Similarly, the access timing time from the activation of the arithmetic pipeline 3 to the start of writing to the vector register 2 is
When N ₂ is set, the number of stages P ₂ is expressed by the following formula (3) or formula (4).

P ₂ = N ₂ / T + 1 (3) (when N ₂ / T is an integer) P ₂ = [N ₂ / T] +1 (4) (when N ₂ / T is not an integer) Vector processing device In general, the time N ₁ from the activation of the access pipeline 1 to the start of writing to the vector register is not necessarily constant, but is fixed for each of a plurality of instructions of the same type, and the operation pipeline The time N ₂ from the start time of 3 to the start time of writing to the vector register 2 is also a fixed time determined by a plurality of instructions of the same type.

When the time N from the start of the access pipeline (1) and the operation pipeline (3) to the start of writing to the vector register (2) differs depending on a plurality of instructions of the same type, and the number of stages P calculated from this differs. Configures the management registers (4 and 5) with the number of stages P calculated from the time N according to the instruction type that is most frequently used among the instruction types.

[Work]

When the read operation for one instruction is completed within the cycle T of the access timing of the bank of the vector register 2, the access pipeline 1 executes N ₁ + T, operation from the start of the read operation to the completion of the instruction. Pipeline 3 takes N ₂ + T time.

At this time, the start of execution of the instruction is performed every cycle T during the busy hour.

Therefore, the management register 4 of the access pipeline 1, when N ₁ + T is divisible by T prepares a number of stages of the value of the quotient obtained by dividing the N ₁ + T in T, when N ₁ + T is not divisible by T is , [(N ₁ + T) / T] + 2 stages can be prepared.

For the management register 5 of the arithmetic pipeline 3, for the same reason, when N ₂ + T is divisible by T, N ₂ + T
If the number of stages is equal to the value of the quotient obtained by dividing T by T, and N ₂ + T is not divisible by T, then [(N ₂ + T) / T] +2 stages can be prepared.

As described above, according to the instruction control device of the present invention, the number of stages of the management registers 4 and 5 is set to the number of cycles from the pipeline start time to the write start time to the vector register 2 and the bank access timing of the vector register 2. Since it is a value obtained from the cycle of, the instruction management register can be configured with the minimum number of stages, that is, the optimal number of stages for using the pipeline without any space.

〔Example〕

The present invention will be described in more detail with reference to the embodiment shown in FIG.

FIG. 2 is a time chart showing the operation status of the management register according to the embodiment of the present invention.

In this embodiment, the number of cycles from the start of the access pipeline to the start of writing data to the vector register is 3.5, that is, N ₁ = 3.5T.

Therefore, according to the equation (2), P ₁ = 5, and the management register has five stages.

The five stages will be referred to as R, S ₁ , S ₂ , S ₃ , and W, respectively.

The operation of the pipeline and the management register will be described below with reference to FIG.

(1) The first instruction A is input to the R stage.

(2) Since each stage is empty in the initial state, instruction A
Is transited to the S ₁ stage 1 clock later, further transited to the S ₂ stage 1 clock later, further transited to the S ₃ stage 1 clock later and held. The data transfer by the instruction A is started.

(3) In the next cycle, the second instruction B is input to the R stage, and the S ₁ and S ₂ stages are empty, so it transits to the S ₁ stage one clock later, and further 1 clock S ₂ later.
The stage is transited to and held, and the data transfer by the instruction B is started.

(4) In the next cycle, since the third instruction C is input to the R stage and the S ₁ stage is empty, the third instruction C is immediately transited to the S ₁ stage and the data transfer by the instruction C is started.

(5) In the next cycle, the fourth instruction D is input to the R stage, and the writing by the instruction A starts in the middle of the cycle, so the instruction A of the S ₃ stage is transited to the W stage,
Writing to the vector register is performed. Since it is recognized that the S ₃ stage is empty, the instruction B is transited to the S ₃ stage, the instruction C is transited to the S ₂ stage, and the instruction D is transited to S ₁
Transition to the stage.

(6) In the next cycle, the fifth instruction E is input to the R stage, and in the middle of the cycle, the data writing to the vector register by the instruction A ends and at the same time, the data writing to the vector register by the instruction B starts. So
The instruction B of the S ₃ stage is transited to the W stage. Since it is recognized that the S ₃ stage is empty, the instruction C is transited to the S ₃ stage, the instruction D is transited to the S ₂ stage, and the instruction E is
Transition to S ₁ stage.

(7) In the next cycle, the data writing to the vector register by the instruction B is completed in the middle of the cycle, the instruction C at the S ₃ stage is transited to the W stage, and the writing to the vector register is performed. The instruction D is transited to the S ₃ stage, and the instruction E is transited to the S ₂ stage.

As described above, an instruction can be input to the R stage every cycle T, and the pipeline operates effectively without interruption.

The access pipeline management register has been described above, but the operation pipeline management register can also operate similarly without interruption by setting P ₂ = [N ₂ / T] +2 stages. You can

[Effects of the Invention] As described above, according to the present invention, the number of stages of the management register of the pipeline is optimized, the waiting of the S stage does not affect the R stage, and the instruction processing efficiency is improved. , Its practical effect is extremely large.

[Brief description of drawings]

1 is a block diagram showing the principle of the present invention, FIG. 2 is a time chart showing the operation of a management register according to an embodiment of the present invention, FIG. 3 is a block diagram showing the configuration of a conventional example, and FIG. 4 is a conventional example. 5 is a time chart showing the operation of the management register according to the above. In the drawings, 1 is an access pipeline, 2 is a vector register (VR), 3 is an operation pipeline, 4 is an access pipeline management register, 5 is an operation pipeline management register, MCU is a main memory control unit, and MSU is a main Storage device, respectively.

Claims (1)

[Claims] 1. A vector register (2) divided into a plurality of banks capable of simultaneously accessing one or a plurality of data elements, and one for performing data transfer between the vector register (2) and a storage device. To a plurality of access pipelines (1), and one to a plurality of operation pipelines (3) that read data from the vector register (2) and perform an operation and write the result to the vector register (2) In a pipeline instruction control device in a vector processing device equipped with, a write start to a vector register (2) is started from the activation time point of the access pipeline (1) and the operation pipeline (3) determined by a plurality of instructions of the same type. The time up to the time point is N, and each instruction is the cycle of the access timing of the vector register (2). A management register (4) for managing the states of the instructions in the access pipeline (1) and the operation pipeline (3), where T is the cycle of sequential reading.
An instruction control device characterized in that the total number of read stages, transfer or operation stages, and write stages of 5) is set to P represented by the following formula. P = N / T + 1 (when N / T is an integer) P = [N / T] +2 (when N / T is not an integer) (where [] is a Gaussian symbol.)