JPH0878956A - Signal generator - Google Patents

Abstract

(57) [Summary] [Object] An object of the present invention is to generate an ideal signal in a signal generator that generates a signal of a second frequency using a signal of a first frequency as a reference signal. [Configuration] The comparison circuit 107 and the detection circuit 108 detect that the phase information is equal to or more than a predetermined value. Depending on the detection result, the switching circuit 109 switches the inputs from the first addition circuit 104, the second addition circuit 105, and the subtraction circuit 106 to output the same, and inputs the output to the first addition circuit 104. The conversion circuit 110 calculates the output of the switching circuit 109 to generate a signal, thereby generating an ideal output signal without phase fluctuation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generator for the purpose of accurately generating a signal of a second frequency by using a signal of a first frequency in digital signal processing.

[0002]

2. Description of the Related Art Generally, a signal generator by digital signal processing calculates a phase by integrating the increasing phase of a signal to be generated in one cycle of a frequency used for processing, and generates the phase at the calculated phase. This is performed by a method of converting the amplitude value of the signal by calculation.

At this time, especially the calculation of the phase is basically performed by an integer operation. For example, when the generated frequency is a and the frequency used for processing is b (where a <
The signal generation processing of b) will be described.

The frequency relationship between a and b is expressed as a ratio, a: b. This ratio is equal to the frequency a in one cycle of the frequency b.
Means that the phase for a / b period changes. Regarding the above ratio, let b1: be a1: b1 when it is expressed using the number b1 expressed by a power of two. Further, when a1 is approximated by a2, which is an integer, the frequency ratio between a and b is a2:
It is approximated by b1.

In the case of realizing a concrete signal generator using this approximated ratio, a2 is set for each cycle of the frequency a.
According to the phase calculation result by the integration processing of a2, which is increased by one, the amplitude value of the frequency b is generated on the phase obtained by dividing one cycle by b1.

However, at this time, a phase error from the original phase occurs due to the error g caused by approximating a1 to a2. This means that when the error g is expressed by a fraction M / m, a
This means that when the integration of 2 is performed m times, only M phase errors occur.

Therefore, the correction of this phase error is conventionally performed by
Only once in every m times of integration, the integrated value a2 is set to d obtained by subtracting M from a2.

The operation of the conventional signal generator will be described in detail with reference to FIGS. 2 and 3. FIG. 2 is a block diagram showing the configuration of a conventional signal generator.

Reference numeral 201 denotes a counter in which one cycle is m, 2
02 is a matching circuit, 203 is a first constant generation circuit that generates a constant c, 204 is a second constant generation circuit that is generated a constant a, 205 is a third constant generation circuit that is generated a constant d, 206 is a switching circuit, 207 is an integrating circuit, 208 is a converting circuit, and 209 is an output terminal.

The matching circuit 202 is a matching circuit which compares the output of the counter 201 with the output of the first constant generating circuit 203 and generates a control signal when they match. Matching circuit 2
The control signal output from 02 is input to the switching circuit 206, and in the switching circuit 206, the control signal inputs the second constant generating circuit 204 and the third constant generating circuit 20.
The input from 5 is switched and output. The output of the switching circuit 206 is input to the integrating circuit 207, and the integrating circuit 207 integrates the input with the output being n bits. The n-bit integration result output from the integration circuit 207 is input to the conversion circuit 208, and the conversion circuit 208 converts the input as phase information into the corresponding amplitude value, and the output terminal 20.
Output to 9.

FIG. 3 is a waveform diagram showing an example of the output signal of each block in FIG. Reference numeral 301 denotes an output waveform of the counter 201, which counts m times in one cycle. 30
2 indicates the output waveform of the matching circuit 202, and the counter 201
The control signal is generated once in one cycle. Reference numeral 303 denotes an output waveform of the integrating circuit 207, integrating the constant a for each count of the counter 201, switching the constant a to the constant d only when the control signal indicated by 302 is generated,
Performs integration with the error due to integer conversion corrected. Since the waveform of 303 limits the output of the integrating circuit 207 to n bits, an overflow occurs and the waveform becomes such a waveform. In 304, 305 shows the waveform of an ideal signal in which no error is generated due to integer conversion, and 306 shows the waveform of the output signal of the conversion circuit 208 generated by the integer conversion operation.

[0012]

However, since the above-described conventional signal generator is configured to correct the error by integerization, phase fluctuation occurs before and after the error correction process, and the frequency accuracy is increased. However, it has a drawback that the signal has poor continuity.

The present invention solves the problems of the conventional method as described above, and eliminates the occurrence of a phase error and corrects the signal that becomes the phase information, so that an ideal signal without phase fluctuation is obtained. It is an object of the present invention to provide a signal generator capable of generating a signal.

[0014]

In order to solve the above-mentioned conventional problems, the signal generator of the present invention uses a constant a (a
Is a positive integer), and a constant b
Second constant generating means for generating (b is a positive integer), third constant generating means for generating a constant c (c is a positive integer), first adding means and second adding means The subtracting means, the detecting means, the comparing means, the switching means and the converting means are provided, and the first adding means adds the output of the first constant generating means and the output of the switching means from 0 to 2 ⁿ −1. (N is a positive integer)
The second adding means adds the output of the first adding means and the output of the second constant generating means, and the subtracting means adds the output of the first adding means to the output of the first adding means. 2, the output of the constant generating means is subtracted, the comparing means compares the output of the first adding means with the output of the third constant generating means, and outputs the magnitude relationship, and the detecting means The switching means detects the overflow of the output of the first adding means, and the switching means detects the input from the first adding means and the second adding means by the output of the detecting means and the output of the comparing means. And the input from the subtracting means are switched and output, and the converting means is configured to convert the phase information into an amplitude value by using the output of the switching means as an input as phase information.

[0015]

According to the present invention, with the above-described structure, the cause of the phase error is eliminated and the signal serving as the phase information is corrected, so that an ideal signal without phase fluctuation can be generated.

[0016]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the signal generating circuit of the present invention. In FIG. 1, 101 is a first constant generation circuit that generates a constant a (a is a positive integer),
102 is a second constant generation circuit that generates a constant b (b is a positive integer), 103 is a third constant generation circuit that generates a constant c (c is a positive integer), 104 is a first addition circuit, 105
Is a second addition circuit, 106 is a subtraction circuit, 107 is a comparison circuit, 108 is a detection circuit, 109 is a switching circuit, 110 is a conversion circuit, 111 is an output terminal, and the first addition circuit 104 is the first The output of the constant generating circuit 101 and the output of the switching circuit 109 are repeatedly added from 0 to 2 ⁿ −1 (n is a positive integer), and the second adding circuit 105
The output of the first adding circuit 104 and the output of the second constant generating circuit 102 are added, and the subtracting circuit 106 outputs the output of the first adding circuit 104 to the output of the third constant generating circuit 103. And the comparison circuit 107 compares the output of the first addition circuit 104 with the output 103 of the third constant generation circuit, and outputs the magnitude relation, and the detection circuit 108 uses the first Of the output of the adder circuit 104, the switching circuit 109 detects the overflow of the input from the first adder circuit 104 and the second output by the output of the comparison circuit 107 and the output of the detection circuit 108.
The input from the adding circuit 105 and the input from the subtracting circuit 106 are switched and output, and the conversion circuit 110
The output of the switching circuit 109 is input as phase information, and the phase information is converted into an amplitude value.

Below, the frequency ratio of the two signals is 999: 4.
A signal represented by a constant 4000 (hereinafter abbreviated as signal 4000) that can be represented by a constant 999.
A case of a signal generator that generates a signal represented by (hereinafter, abbreviated as signal 999) will be described.

In this case, the frequency ratio 999: 4000 between the signal 999 and the signal 4000 is equal to the signal 999 to be generated.
Of one of the signals 4000 to be used, when one division is obtained by equally dividing one cycle into 4000
It means that the period corresponds to the 999 unit phase portion of the signal 999.

In FIG. 1, 101 is a first constant generating circuit for generating a constant 999, 102 is a second constant generating circuit for generating a constant 96, 103 is a third constant generating circuit for generating a constant 4000, 104. Is a first addition circuit, 105
Is a second addition circuit, 106 is a subtraction circuit, 107 is a comparison circuit, 108 is a detection circuit, 109 is a switching circuit, 110 is a conversion circuit, 111 is an output terminal, and the first addition circuit 104 is the first The output of the constant generating circuit 101 and the output of the switching circuit 109 are repeatedly added from 0 to 4095, and the second adding circuit 105 outputs the output of the first adding circuit 104 and the second constant generating circuit. 102, the subtraction circuit 106 subtracts the output of the third constant generation circuit 103 from the output of the first addition circuit 104, and the comparison circuit 107 causes the comparison circuit 107 to output the first addition circuit 104. Is compared with the output of the third constant generation circuit 103, and the magnitude relationship is output, and the detection circuit 108
Detects an overflow of the output of the first adder circuit 104, and the switching circuit 109 causes the comparison circuit 107 to operate.
Of the first circuit and the output of the detection circuit 108.
From the adder circuit 104 and the second adder circuit 10
5 and the input from the subtraction circuit 106 are switched and output, and the conversion circuit 110 outputs the switching circuit 1
The output of 09 is input as phase information, and the phase information is converted into an amplitude value.

In digital signal processing, the processing is performed in binary. Therefore, for example, the first adder circuit 104
Has a length of 12 bits because it needs to represent 4000.

When the first adder circuit 104 has 12 bits, the state of its adder output is 0 to 4095 (409).
There are 6 states, and in the case of more than that, overflow occurs.

Therefore, the output of the first adder circuit 104 is as in the column of the added value in (Table 1) in the case of no correction.

[0024]

[Table 1]

However, the condition originally required in this case is 0.
Since there are 4000 states from 1 to 3999, a difference occurs between the added output value and the original value.

Therefore, it is necessary to correct the 4096 state to the 4000 state (see the required value column in (Table 1)).

With respect to this correction, for example, when the output of the first adder circuit 104 increases by one, when the output becomes 3999, the adder circuit 10
The operation of resetting 4 to 0 may be performed.

However, this time, the output increase is not 1 but 999, which is not a continuous increase. Therefore, the reset determination value and the reset value are not unique, and a simple reset operation cannot be performed.

Therefore, in this embodiment, the first adder circuit 10
4 and the output of the first adding circuit 104 and the output of the second constant generating circuit 102 are added to the second adding circuit 105.
And the output of the subtraction circuit 106, which subtracts the output of the third constant generation circuit 103 from the output of the first addition circuit 104, by the output of the comparison circuit 107 and the output of the detection circuit 108. This is done by switching with and outputting.

The operation will be described below. The output of the first addition circuit 104 can be used as it is without conversion in the case of 0 to 3999, but if it is a value larger than that, correction is required.

First, when the value is 4000 to 4095, the originally necessary value corresponds to 0 to 95. Therefore, 4000 which is the output of the third constant generation circuit 103 is subtracted from the output of the first addition circuit 104 by the subtraction circuit 106, and the output of the first addition circuit 104 becomes the output value of the third constant generation circuit. Only when the output of the comparison circuit 107 for discriminating whether it is 4000 or more is 4000 or more, the output of the subtraction circuit 106 is selectively output by the switching circuit 109.

Next, there is a case where the output of the first addition circuit 104 causes an overflow due to the limitation of the number of bits, that is, 4096 or more. In this case, the output value of the first addition circuit 104 is apparently 409.
It is the value obtained by subtracting 6 minutes.

The output value when the adder circuit 104 overflows is smaller than the originally required value by 96 minutes. Therefore, the output 96 of the second constant generation circuit 102 is added to the output of the first addition circuit 104 as the second output.
Of the first adder circuit 104
The output of the second adder circuit 105 is selectively output by the switching circuit 109 only when the output of the detection circuit 108 for identifying whether or not the output has overflowed.

As described above, according to the present embodiment, the output of the first adder circuit 104 is corrected according to its state, and the result is switched by the switching circuit 109, so that the signal serving as the phase information is accurately obtained. It is possible to output, and it is possible to generate an ideal generated signal.

[0035]

As described above, according to the present invention, it becomes possible to obtain an accurate phase information signal by correcting the signal which becomes the phase information of the generated signal according to the state thereof, and ideally It is possible to generate various generation signals.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a signal generator according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional signal generator.

FIG. 3 is a waveform diagram showing the operation contents of a conventional signal generator.

[Explanation of symbols]

 101 First Constant Generation Circuit 102 Second Constant Generation Circuit 103 Third Constant Generation Circuit 104 First Addition Circuit 105 Second Addition Circuit 106 Subtraction Circuit 107 Comparison Circuit 108 Detection Circuit 109 Switching Circuit 110 Conversion Circuit 111 Output Terminal

Claims (1)

[Claims] 1. A first for generating a constant a (a is a positive integer)
Constant generating means, a second constant generating means for generating a constant b (b is a positive integer), a third constant generating means for generating a constant c (c is a positive integer), and a first addition Means, second adding means, subtracting means, detecting means, comparing means, switching means, and converting means, wherein the first adding means is the output of the first constant generating means. The output of the switching means is added, the second adding means adds the output of the first adding means and the output of the second constant generating means, and the subtracting means adds the output of the first adding means. The output of the second constant generating means is subtracted from the output of the means, and the comparing means outputs the output of the first adding means and the third adding means.
Comparing the outputs of the constant generating means and outputting the magnitude relation, the detecting means detects an overflow of the output of the first adding means, and the switching means outputs the output of the detecting means and the comparing means. The output from the first adding means, the input from the second adding means, and the input from the subtracting means are switched and output, and the converting means outputs the output of the switching means in phase. A signal generator characterized in that, as input as information, the phase information is converted into an amplitude value.