JPH0879042A - Clock control circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] Noise Nn and Np are mixed in the clock start / stop command Sc when the output clock Co that controls the start / stop of the input clock Ci according to the specification by the logic state of the clock start / stop command Sc is taken out. Is also not mixed in the output clock Co. [Structure] Controlling the transmission of a clock start / stop command Sc to be given to the other input of a logic gate means 10 such as an AND gate which receives an input clock Ci to one input using an electronic switch means 20 such as a transmission gate. , Input clock that noise Nn and Np are easily mixed in output clock Co
The electronic switch means 20 is kept in the non-conducting state only during the period in which Ci is in the high state for opening the AND gate as the logic gate means 10, and during this period, the logic state of the other input of the logic gate means 10 becomes the previous conducting state. While maintaining the period, the transmission of the clock start / stop command Sc to the logic gate means 10 is temporarily interrupted so that the mixed noise Nn or Np does not appear in the output clock Co.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control circuit for controlling start / stop of clocks used in various electronic circuits.

[0002]

2. Description of the Related Art As is well known, a clock, to be exact, a clock pulse is widely used as a reference for operation of various electronic circuits. There is a case where it is desired to control by starting and stopping, and a conventional example of a circuit and operation therefor will be described with reference to FIG. 3 in the case where the electronic circuit is a counter.

The counter 1 of FIG. 3 (a) is this electronic circuit, and the AND gate 10 is used as a clock control circuit for controlling the start / stop of the clock Co to be given to it.
This AND gate 10 receives a clock Ci having a repetitive pulse waveform as shown in FIG. 3 (b) at one of its inputs, and receives at the other input a clock start / stop command Sc as shown in FIG. Only in the case of the state, the clock Co shown in FIG. For example, the clock start / stop command Sc is a signal indicating the time to maintain the high logic state,
If the counter 1 is cleared by the reset pulse RP, at the same time it is set to high to enable the AND gate 10, and then to be set to low to disable the AND gate 10, and then the count value Q0 to Qn is read from the counter 1, the clock is stopped. A digital value obtained by engraving the time indicated by the command Sc with the clock Co is obtained.

[0004]

Although the conventional clock control circuit as described above can be easily constructed by a single AND gate 10, for example, if noise is mixed in the clock start / stop command Sc for some reason, There is a problem that it malfunctions very easily. Figure 3 shows how this malfunction occurs.
Shown in (e) and Figure 3 (f). FIG. 3 (e) shows a state in which short pulse noise is mixed with the clock start / stop command Sc of the normal waveform shown in FIG. 3 (c).
Negative pulse noises Nn and nn are mixed in when is high, and positive pulse noises Np and np are mixed in when is low.

First, when the clock start / stop command Sc is in the high state, when the input clock Ci of the AND gate 10 shown in FIG.
No malfunction occurs even if nn is mixed, but it should be high if negative noise Nn is mixed in when input clock Ci is high. False negative pulse to output clock Co in Figure 3 (f). Fn is coming. Similarly, when the clock start / stop command Sc is in the low state, a malfunction cannot occur even if the positive noise np indicated by the broken line is mixed when the input clock Ci is in the low state, but the input clock Ci When the positive noise Np is mixed in when is high, a false positive pulse Fp is generated in the output clock Co which should be low. In this way, when the false negative pulse Fn is mixed in the output clock Co by the AND gate 10 in FIG. 1A, the count values Q0 to Qn of the counter 1 are distorted,
If the false positive pulse Fp is mixed, its value may be further changed during reading.

An object of the present invention is to solve such a problem and to provide a clock control circuit which does not malfunction even when noise is mixed in the clock start / stop command Sc.

[0007]

In the clock control circuit of the present invention, a logic gate means for receiving a repetitive pulsed clock at one input and outputting a clock whose start / stop is controlled, and a clock to be given to the other input. The above-mentioned object is achieved by using an electronic switch means for transmitting a start / stop command and making the electronic switch means non-conductive only during a period in which the electronic switch means is in a logic state which causes the logic gate means to open.

Incidentally, it is desirable that the logic gate means in the above structure is constituted by an insulated gate control transistor such as a MOS transistor. Further, for example, an AND gate or a NAND gate is used for this logic gate means, and it is preferable to put the electronic switch means in a non-conducting state when the input clock is in a high logic state, or a NOR gate is used as this logic gate means. The electronic switch means may be placed in a non-conducting state when its input clock is in a low logic state. It is preferable to use a transmission gate for the electronic switch means, but it is also simplest to use a single field effect transistor.

[0009]

The present invention focuses on the fact that when the electronic switch means is turned off or turned off, the output to the logic gate means is maintained at the logic state of the clock start / stop command in the previous turn on or turn on state. Then, the electronic switch means is kept in the non-conducting state only during the period when the input clock is in the logic state for opening the logic gate means, thereby preventing the malfunction due to the intrusion noise of the clock control circuit.

That is, for example, when the logic gate means is an AND gate, if noise is mixed in the clock start / stop signal within the period in which the input clock is in the high logic state for opening it, the malfunction occurs as described above. However, in the present invention, the high logic state of the input clock makes the electronic switch means non-conductive so that noise is not transmitted to the logic gate means. Of course, the logic state of the input clock for keeping the electronic switch means in the non-conducting state differs depending on the type of the logic gate means, and is the high logic state in the case of the AND gate and the NAND gate, and the low state in the case of the NOR gate.

Since the high and low logic states of the input clock are of course sequentially changed, the electronic switch means is rendered conductive at one of them, and the logic state of the output is changed to the clock start / stop command at that time. It is updated or maintained according to the logic state of and the logic state is maintained during the next non-conduction state. When the logic state of the clock start / stop command changes when the electronic switch means is in the non-conducting state, the electronic switch means changes the logic state of its output the next time it becomes the conducting state. Therefore, the logic state designated by the clock start / stop command is always correctly transmitted to the logic gate means except for a slight delay time when the electronic switch means changes during the non-conduction state.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 is a circuit diagram of an embodiment of a clock control circuit according to the present invention and a related waveform diagram, and FIG. 2 is a circuit diagram of two different embodiments of the device of the present invention. Since the parts corresponding to those in FIG. 3 described before these figures are denoted by the same reference numerals, the description of the overlapping parts will be appropriately omitted. In these embodiments, the logic gate means 10
Clocks Co output from ~ 12 are given to the counter 1 of FIG. 3, for example.

In the embodiment shown in FIG. 1A, logic gate means
An AND gate is used as 10, and in the present invention, the clock Ci having the repetitive pulse waveform shown in FIG. 1 (b) is received at one input of the logic gate means 10 to start / stop the clock shown in FIG. 1 (c). The point that the clock Co, which controls the start and stop of the command Sc according to the logic state of high and low, is output from the logic gate means 10 is the same as in FIG. 3 of the related art, but the clock control circuit according to the present invention uses the clock It differs from the conventional one in that the start / stop command Sc is transmitted to the other input of the logic gate means 10 via the electronic switch means 20.

In the embodiment shown in FIG. 1 (a), a transmission gate is used as the electronic switch means 20, and a complementary signal from the inverter 20a attached to the input clock Ci is input to its complementary control input as its control input. By applying the respective clocks Ci, the transmission gate is placed in the conductive state when the input clock Ci is in the low logic state and the clock start / stop command Sc is transmitted to the logic gate means 10 as it is. means
The AND gate as 10 is controlled to be placed in the non-conducting or off state in the high logic state for opening the AND gate.

In the non-conducting state of the electronic switch means 20, the other input of the logic gate means 10 maintains the logic state in the previous conducting state. That is, if the previous logic state was low, the clock start / stop command
Even if Sc changes to the high logic state, it is not transmitted in the non-conduction state, so that the logic state of the other input of the logic gate means 10 is kept low. If the previous logic state is, on the contrary, high, even if the clock start / stop command Sc changes to the low logic state, it is not transmitted in the non-conducting state, and the transistor forming the electronic switch means 20. The other input of the logic gate means 10 is maintained in the high logic state of being charged while the pn junction which always exists in the circuit is reverse-biased.

As described above, when the electronic switch means 20 is in the non-conductive state, the logic state of the input of the logic gate means 10 which receives the clock start / stop command Sc is maintained as it was in the previous conductive state, which is shown in FIG. The clock control circuit according to the present invention does not change in the clock start / stop command Sc in c) even if the above-mentioned noises Nn and Np, which have caused the conventional malfunction, are mixed in when the input clock Ci is high. The clock Co can be output with the correct waveform as shown in FIG. 1 (d) without being disturbed by noise, and the malfunction due to the conventional mixed noise can be almost completely prevented. When the logic state of the clock start / stop signal Sc changes in the conductive state of the electronic switch means 20, the output clock Co is immediately stopped / started according to the designation, and the non-conductive state is shown as shown by the broken line in FIG. 1 (c). When the state changes, the output clock Co is stopped and started after waiting for the next conductive state.

Further, maintaining the input of the logic gate means 10 in the logic state of low or high in the non-conducting state described above is physically placing the input in the state of discharging or charging, respectively. Although the discharge state can be maintained by the leakage capacitance of the input side wiring, it is desirable that the logic gate means 10 is composed of an insulated gate control transistor such as a MOS transistor and the capacitance of the gate is used for charging and discharging. , This gate capacitance is 1pF
Even with a very small amount, the effect of preventing malfunction due to noise can be further ensured. If the capacitance of the gate is used, the period during which the charge / discharge state of the input of the logic gate means 10 can be maintained while the electronic switch means 20 is in the non-conduction state is set to 1 second or more, and the cycle of the input clock Ci is Even if it is quite long, you can have enough room.

In the next embodiment shown in FIG. 2 (a), the NAND gate 11 is used as the logic gate means, and the electronic switch means is composed of a single p-channel type MOS transistor 21 and its gate is supplied with the input clock Ci. give. The output clock Co of this embodiment has a phase opposite to that of the input clock Ci, but the logic state of the input clock Ci for opening the logic gate means which is the NAND gate 11 is high, which is the same as the previous embodiment, and the p-channel The electronic switch means, which is the transistor 21, is placed in the non-conducting state in this high logic state of the input clock Ci and in the reverse conducting state in the low logic state. Therefore, even in the embodiment of FIG. 2A, the same effect as the embodiment of FIG. 1 against the malfunction caused by the noise mixed in the clock start / stop command Sc can be obtained, and the reliability of the operation is slightly deteriorated. The overall configuration of can be considerably simplified.

In the embodiment of FIG. 2 (b), the NOR gate 12 is used as the logic gate means and the electronic switch means is constituted by a single n-channel MOS transistor 22 and the input clock Ci is given to its gate. In this embodiment, the output clock Co has a phase opposite to that of the input clock Ci, and the NOR gate
The logic state of the input clock Ci for opening the logic gate means, which is 12, becomes low, and the n-channel transistor 22 as the electronic switch means becomes non-conductive in this low state of the input clock Ci and conductive in the high state. To each. The effect of preventing malfunction due to noise mixed in the clock start / stop command Sc and the effect of simplifying the overall configuration of the clock control circuit in the embodiment of FIG. 2 (b) are the same as those of the embodiment of FIG. 2 (a). is there.

In the embodiment shown in FIGS. 2 (a) and 2 (b) above,
Since the logic state of the clock start / stop command Sc input of the NAND gate 11 and NOR gate 12 in the non-conducting state of the electronic switch means is maintained mainly in the state where the internal pn junction of the MOS transistors 21 and 22 is reverse biased. In order to stabilize this sustaining state, it is preferable to use these transistors in a state where the substrate is not connected to the source or drain as shown in the figure.

The present invention is not limited to the embodiments described above, and can be implemented in various modes. For example, any kind of logic gate other than the embodiment can be appropriately used as the logic gate means, and the same applies to the electronic switch means. Further, in the embodiment, the input clock has a repetitive pulse shape having a constant cycle, but the clock control circuit of the present invention can be applied as it is even when the clock has a variable cycle.

[0022]

As described above, according to the clock control circuit of the present invention, the logic gate means for receiving the repetitive pulsed clock at one input and issuing the output clock controlled to start and stop, and the clock start / stop for the other input. The electronic switch means for transmitting and controlling the command is used, and the electronic switch means is in the non-conduction state only during the period in which the input clock causes the logic gate means to open the logic state, that is, during the period when noise may be mixed in the output clock. By keeping the other input of the logic gate means in the previous conductive state and keeping its operation normally, the transmission of the clock start / stop command via the electronic switch means is temporarily interrupted, and therefore it is mixed in it. To prevent the transmission of noise, and eliminate the possibility of noise being mixed in the output clock with a very simple circuit configuration. Door can be.

In the embodiment of the present invention in which the logic gate means is composed of an insulated gate control transistor, the logic state of the clock start / stop command input of the logic gate means in the non-conducting state of the electronic switch means is stably maintained. This has the effect of ensuring the operation of the clock control circuit. The embodiment using a NAND gate or a NOR gate as the logic gate means has an advantage that it can be constituted by the smallest number of transistors.

Further, the mode in which the transmission gate is used as the electronic switch means is advantageous in ensuring the transmission control operation for the clock start / stop command most surely,
In the mode in which a single field effect transistor is used as the electronic switch means, the circuit configuration of the clock control circuit can be simplified.

[Brief description of drawings]

FIG. 1 shows an embodiment of a clock control circuit according to the present invention and main signals associated therewith, FIG. 1 (a) is a circuit diagram thereof,
FIG. 2B is a waveform diagram of the input clock, FIG. 1C is a waveform diagram of the clock start / stop command, and FIG. 1D is a waveform diagram of the output clock.

2A and 2B show some embodiments of the present invention, FIG. 2A is a circuit diagram of a different embodiment, and FIG. 2B is a circuit diagram of a further embodiment.

3A and 3B show main signals related to a conventional clock control circuit. FIG. 3A is a circuit diagram thereof, FIG. 3B is a waveform diagram of an input clock, and FIG. 3C is a clock start / stop command. Waveform diagram of the same figure
(d) is a waveform diagram of the output clock, (e) is a waveform diagram of the clock start / stop command in which noise is mixed, and (f) is a waveform diagram of the corresponding output clock.

[Explanation of symbols]

10 AND gate as logic gate means 11 NAND gate as logic gate means 12 NOR gate as logic gate means 20 Transmission gate as electronic switching means 21 P-channel transistor as electronic switching means 22 N-channel transistor as electronic switching means Ci input Clock Co Output clock Nn Negative pulse noise Np Positive pulse noise Sc Clock start / stop command

Claims (6)

[Claims] 1. A logic gate means for receiving a repetitive pulsed clock at one input and controlling the start / stop of the clock, and an electronic switch means for transmitting a clock start / stop command to be given to the other input of the logic gate means. A clock control circuit, characterized in that the electronic switch means is made non-conductive only during a period in which the electronic switch means is in a logic state in which it opens the logic gate means. 2. A clock control circuit according to claim 1, wherein the logic gate means comprises an insulated gate control transistor. 3. The circuit according to claim 1, wherein an AND gate or a NAND gate is used as the logic gate means, and the electronic switch means is kept in a non-conducting state in the high logic state of the clock. Clock control circuit. 4. The clock control circuit according to claim 1, wherein a NOR gate is used as the logic gate means, and the electronic switch means is kept in a non-conducting state when the clock is in a low logic state. . 5. The clock control circuit according to claim 1, wherein the electronic switch means is a transmission gate. 6. The clock control circuit according to claim 1, wherein the electronic switch means is a field effect transistor.