JPH088225A - Method for inspecting dimension of conductor pattern of semiconductor device - Google Patents

Abstract

PURPOSE:To inspect the finished width of the second conductor pattern accurately only with the visual inspection using a microscope and the like by inspecting the dimensions of conductor patterns based on the position relationship between a dimension inspecting pattern formed at the same time as the first conductor pattern and a second dimension inspecting pattern. CONSTITUTION:On a transparent insulating substrate 110, a first opaque conductor pattern 120, a dimension inspecting pattern 500 for the first conductor pattern 120 and a dimension inspecting pattern 50 for inspecting the second conductor pattern are formed. Then, the opaque conductor pattern 120 and the dimension inspecting pattern 50 are used as the photomasks, second conductor pattern 130 and a dimension inspecting pattern 60 for the second conductor pattern 130 are formed by the exposure from the side of the substrate 110. The dimension of the second conductor pattern 130 is inspected based on the position relationship between the dimension inspecting pattern 50 formed at the formation of the first conductor pattern 120 and the dimension inspecting pattern 60 formed at the formation of the second conductor pattern 130.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for inspecting a conductor pattern which requires particularly high dimensional accuracy in manufacturing a semiconductor device, and more particularly to a method for inspecting a second conductor pattern.

[0002]

2. Description of the Related Art In manufacturing a semiconductor device, when a conductor pattern is formed by photo-etching, the exposure conditions thereof
The size of the formed pattern varies depending on etching conditions and the like. Therefore, the actual size of the conductor pattern of the semiconductor device is measured by a micrometer or the like to determine the quality of the formed figure. However, in this measurement method, for example, if the variation of the dimension becomes the specification such that the design center value is 1.0 μm or less, the mechanical accuracy of the measurement jig, the difference in the skill of the measurer, and the like become problems, and the measurement is performed. Was very difficult. However, it is known that variations in pattern dimensions after photoetching have a great influence on characteristics such as power consumption and breakdown voltage of semiconductors.

Therefore, in order to eliminate the problems such as the mechanical accuracy of the measuring jig and the skill difference of the measurer, the Japanese Patent Publication No. 59-4850.
In the publication, a method for manufacturing a semiconductor has been proposed in which, when a pattern is formed by photoetching, at least one pair of dimensional inspection patterns (graphics) forming a pair are photoetched at the same time. This semiconductor manufacturing method will be described with reference to the drawings. FIG. 7 shows a pair of dimensional inspection figures proposed in Japanese Patent Publication No. 59-4850. Rectangle 10 and rectangle 20
Is a pair of dimensional inspection figures. Here, assuming that the dimensions m and n are the maximum deviation value of the dimension variation and the minimum deviation value of the dimension variation, the acceptance criteria (within the dimension variation allowable range) of the dimension inspection of the figure formed by etching is one figure 10 in the y direction.
The extension line of the line segment 10x on one side penetrates the other figure 20, and the line segment 20x of the figure 20 penetrates the figure 10.
In addition, it is necessary that the line segment 10y of the graphic 10 does not penetrate the graphic 20 in the x direction and the line segment 20y of the graphic 20 does not penetrate the graphic 10. That is, when the pattern for dimension inspection satisfies the above conditions, it is determined that the pattern (conductor pattern) etched at the same time is within the dimensional variation allowable range.

[0004]

An example of determining the quality of the dimension of the figure (pattern) when the first conductor pattern and the second conductor pattern are formed by etching using this inspection figure is shown below. FIG. 8 is a cross-sectional view of an actual device, in which an opaque conductor film is deposited on a transparent insulating substrate 1 and the first photolithographic etching is performed, and the first conductor pattern 2 of the actual device is simultaneously exposed. A set of first conductive pattern inspection dimension inspection figures 10 (20),
Figure 1 for dimensional inspection of a pair of second conductor patterns
The figure shows that 01 and 201 are formed. Further, in FIG. 9, the transparent second layer 3, the transparent third layer 4, and the fourth layer are continuously deposited on the first conductor pattern 2, and after applying a resist (not shown), they are already formed. A second step including an exposure process from the side of the substrate 1 using the opaque conductor pattern 2 and the figure 10 (20) and the figure 101 (201) as photomasks.
The second photolithographic etching is performed, and the second conductor pattern 5 and the dimension inspection figures 105 and 205 of the second conductor pattern are formed on the fourth layer. FIG.
Reference numerals 0, 11, and 12 are plan views of the dimension inspection graphic formed at that time.

FIG. 10 is a plan view of the dimension inspection figures 10 and 20 for the first conductor pattern, in which the dimensions m1 and n1 are the minimum dimension variation value and the maximum dimension variation value of the first conductor pattern 2, respectively. As shown in the figure, for example, when the dimensional variation of the first conductor pattern is e1, the pattern 10 in the y direction is
Since the extension line of the line segment 10x on one side penetrates the figure 20, and the extension line of the line segment 20y on one side of the figure 20 does not penetrate the figure 20 in the x direction, the wiring pattern 2 of the first conductor 2
Is within the dimensional fluctuation allowable range (0∠e1∠m1, 0∠e1∠n
It is determined to be 1). At this point, when the dimension variation maximum deviation value and the dimension variation minimum deviation value are m2 and n2, the dimension inspection figures 101 and 201 of the second conductor pattern are changed to m2-e1 and n2-e1 as shown in FIG. It is had. Then, after forming the first conductor pattern 2, a transparent second layer 3, a transparent third layer 4, and a transparent fourth layer are continuously deposited, and a resist (not shown) is applied. One conductor pattern 2, and dimensional inspection figure 1
By using 01 and 201 as photomasks, photolithography is performed from the back surface with an exposure step to form the second conductor pattern 5 of the fourth layer and the second dimension inspection figures 105 and 205.

When the second conductor pattern 5 of the fourth layer is formed in FIG. 12, second dimension inspection patterns 105 and 205 for the second conductor pattern are formed using the dimension inspection patterns 101 and 201 as photomasks. Here is the result. For example, during the second photolithographic etching, the dimensional fluctuation of the second conductor pattern is allowed within the allowable range e2 (0∠e2∠m2, 0∠e
2∠n2), the extension line of the line segment 205x of the figure 205 in the y direction is the figure 105 as shown in the figure.
Does not penetrate. Since the extension line of the line segment 105y of the graphic 105 does not penetrate the graphic 205 in the x direction, it is determined that the wiring pattern 2 of the first conductor is out of the dimensional variation allowable range. Therefore, it is not possible to judge whether the dimensions of the second conductor pattern 5 of the fourth layer are good or bad. Therefore, the dimension inspection figure proposed in Japanese Patent Publication No. 59-4850 can be applied to the dimension inspection of the wiring pattern formed in the first layer, but has a disadvantage that it cannot be applied to the wiring pattern of a multilayer or a layer in a later step. Was.

Therefore, according to the present invention, an opaque first conductor is deposited on a transparent insulating substrate, a first photolitho etching is performed to form a first conductor pattern, and then a second photolitho etching is performed. When the second conductor pattern is formed by performing the above, the finished width of the second conductor pattern can be determined by visual inspection only with a microscope without measuring the actual dimension of the finished pattern with a micrometer or the like. Provide a dimension inspection method that can be reliably determined.

[0008]

A method for inspecting a conductor pattern of a semiconductor device according to the present invention comprises a dimension inspection pattern (graphic) formed simultaneously with an opaque first conductor pattern formed on a transparent insulating substrate. A second conductor pattern including an opaque first conductor pattern and a second conductor pattern formed by exposure from the substrate side using a dimensional conductor pattern as a photomask and a second conductor pattern (graphic) formed at the same time. The dimensional inspection of the conductor pattern is basically performed by a configuration in which the dimensional inspection of the conductor pattern is determined by the positional relationship between the dimensional inspection pattern formed simultaneously with the first conductor pattern and the second dimensional inspection pattern. Provide as a configuration.

Further, as a pattern (figure) for inspecting the second conductor pattern, the first figure serving as a reference for the dimension inspection and the dimension in the width direction with respect to the first figure are the maximum dimension variation deviation value. The enlarged second figure and the first figure
And a third figure having a similar shape in which the dimension in the width direction is reduced by the minimum deviation value of the dimensional variation, the first figure, the second figure, and the third figure are parallel to each other. The center line of the first figure, the center line of the second figure,
The third graphic has a configuration using a graphic in which the center line of the graphic is arranged on the same line.

[0010]

According to the method of inspecting a conductor pattern of a semiconductor device of the present invention, the positional relationship between the second conductor pattern inspection figure formed in the fourth layer and the inspection figure formed simultaneously with the first conductor pattern is determined. By visually observing, it is determined whether or not the second conductor pattern inspection figure is within the dimensional variation allowable range, and the quality of the conductor pattern is determined by this determination. Dimension inspection used for pattern inspection method Depending on the photolithographic etching state of the figure, whether the finished width of the conductor pattern of the photolithographically etched film is within the dimensional variation allowable range is determined by the second conductor formed simultaneously with the second conductor pattern. An extension line of two line segments parallel to the center line of the pattern which is the reference of the pattern dimension inspection pattern, and one of the second conductor pattern dimension inspection pattern (graphic) formed at the same time as the first conductor pattern. The determination is made based on the positional relationship with the second largest figure and the positional relationship with the third figure with the smallest width of the dimension inspection figure.

[0011]

EXAMPLES The present invention will be specifically described below based on examples. FIG. 5 is an explanatory view showing the manufacturing process of the actual device. The first conductor pattern and the first conductor pattern dimension inspection pattern
For turn (figure) and second conductor pattern dimension inspection
Formation of pattern (figure) (see FIGS. 5a, 5b, and 5c) The actual device 100 has Ta or C on a glass substrate 110.
a film 112 (100 um to 150 um) such as r is deposited,
The first conductor pattern 120, the dimension inspection pattern 500 for the first conductor pattern 120, and the dimension inspection pattern 50 for the second conductor pattern 50 are simultaneously formed by the photoresist pattern 114 using the photolithography etching technique. Show. The dimension inspection figure 500 of the first conductor pattern formed at this time is a pair of dimension inspection figures described in the prior art.

FIG. 1 shows a dimensional inspection pattern (hereinafter referred to as a second dimensional inspection graphic) 50 of the second conductor pattern formed simultaneously with the formation of the first conductor pattern according to the present invention.
Will be described. A second dimension inspection graphic 50 for dimension inspection of the second conductor pattern is a first reference graphic 55 formed in a central portion serving as a reference and an upper portion of the first reference graphic 55, A second graphic 57 formed to be larger in the width direction than the reference graphic 55 and a third graphic 53 formed below the first reference graphic 55 and smaller in the width direction than the first reference graphic 55 are provided. are doing. Here, if the variation maximum deviation value and the variation minimum deviation value of the dimensions of the second conductor pattern are u and w, the second figure 57 is the first reference figure 5
5, the width dimension is larger by the dimension u, and the third figure 53 is a figure in which the width dimension is smaller by the dimension w than the first reference figure 55. Further, the first reference figure 55, the second figure 57, and the third figure 53 are arranged in parallel with the first reference figure 55 as a center, and the center line of the first reference figure 55, the second line The center line of the graphic 57 and the center line of the third graphic 57 are arranged on the same line O. The distance z between the third figure 53 and the first reference figure 55 and the distance z between the first reference figure 55 and the third figure 57 are approximately 200 μm or less as a range that can be visually inspected by a microscope. Has become.

Second conductor pattern and second conductor pattern
Formation of dimensional inspection figure (see FIGS. 5d and 5e) SiNx thickness 300 after forming the first conductor pattern 120
nm second layer 116, a-Si: H thickness 50 nm third layer 117, SiNx thickness 150 nm fourth layer 11
8 is continuously deposited, and after applying a resist (not shown),
The second wiring pattern 120 is formed on the fourth layer SiNx by performing photolithography etching with exposure from the back surface using the finished wiring pattern 120 of the first layer as a photomask. When the second conductor pattern 130 is formed by photolithographic etching of the fourth layer SiNx, the fourth layer SiNx pattern 505 using the first dimension inspection pattern 500 as a photomask, and the dimension inspection pattern for the second conductor pattern. A fourth layer SiNx pattern 60 using 50 as a photomask is formed.

FIG. 2 shows an example of the dimension inspection graphic 60 of the second conductor pattern 130 formed on the fourth layer SiNx. The second conductor pattern dimension inspection graphic 60 formed by using the second inspection graphic 50 as a photomask includes a second reference inspection graphic 65 formed by using the first reference inspection graphic 55 as a photomask and a second graphic. It has a fourth graphic 67 formed by using 57 as a photomask and a fifth graphic 63 formed by using the third graphic 53 as a photomask. next,
A judgment condition for judging whether or not the finished width of the wiring pattern of the photolithographically-etched film formed by photolithography is within the dimensional variation allowable range will be described using this figure. In the case of this drawing, the extension line A of the line segment of the side 65y _{1 in} the direction y of the reference figure 65 of the dimension inspection figure 60 of the second conductor pattern formed on the fourth layer, and the side 6 of the figure 65.
The extension line B of the line segment of 5y ₂ both penetrates the graphic 57 having the largest width of the second dimension inspection graphic 50 and the graphic 53 having the smallest width of the second dimension inspection graphic 50. Not not. In this state, it is determined that the width of the second conductor pattern 130 of the fourth-layer SiNx is within the dimensional variation allowable range.

Next, a case where it is determined that the width of the second conductor pattern 130 of the fourth layer SiNx is outside the dimensional variation allowable range will be described (see FIGS. 3 and 4). (1) In case of dimension failure due to over-etching ...
Fig. 3 Two sides 65y ₁ and 65 in the direction y of the second reference graphic 65 located in the middle of the dimension inspection graphic 60 formed on the fourth layer
The extension lines A and B of the line segment of y ₂ together with the second figure 57 which is the largest width of the second dimension inspection figure 50 and the smallest dimension 53 of the second dimension inspection figure 50. Penetrates. In such a state, the width of the second conductor pattern 130 of the fourth layer is determined to be outside the dimensional variation allowable range.

(2) In the case of a dimension defect due to insufficient etching: The second reference pattern 65 located in the center of the second pattern 60 of the second conductor pattern formed in the fourth layer in the direction y in FIG. The extension lines A and B of the line segments of the sides 65y ₁ and 65y _{2 have} the widths of the second figure 57, which is the largest width of the second dimension inspection figure 50, and the second dimension inspection figure 50 equal to each other. Do not penetrate through the smallest figure 53. In such a state, the width of the second conductor pattern 130 of the fourth layer is determined to be outside the dimensional variation allowable range. As described above, by using the inspection figure shown in this embodiment, the second conductor pattern 13 formed on the fourth layer is formed.
Whether the dimension of 0 is good or bad can be determined and judged only by visual inspection with a microscope or the like without measuring the actual dimension with a micrometer or the like.

Further, in this embodiment, the second graphic and the third graphic are arranged at a predetermined interval with respect to the central graphic based on the shape of the graphic. The inspection figure 70 may have the shape shown. Inspection figure 70
The second graphic 77 has its width dimension increased by the maximum dimension variation deviation value u from the reference graphic 75 serving as a reference, and the third graphic 73 has its width dimension reduced by the maximum dimension variation deviation value with respect to the reference graphic 75. It is made smaller by w and the second figure 77
And the reference graphic 75 are arranged without a gap, and the third graphic 73 and the reference graphic 75 are also arranged without a gap. Also in this case, the method for determining whether the width of the second conductor pattern of the fourth layer SiNx is within the allowable width dimension variation range or outside the allowable width dimension variation range is the same as in the above case. Also,
Although a rectangular shape is shown as the dimension inspection figure in the above embodiment,
It can be implemented with other shapes such as a circle.

[0018]

As described above, according to the present invention,
Even when an opaque first conductor pattern is formed on a transparent insulating substrate and the second conductor pattern is formed by exposure from the back surface using this opaque pattern as a photomask, the dimension inspection pattern (figure) is used. Since the size of the second conductor pattern is inspected, the quality of the finished conductor pattern can be checked only by visual inspection with a microscope without measuring the actual size of the finished width of the second conductor pattern with a micrometer. There is an effect that can be determined.

Further, by using the inspection pattern (figure) for the finished dimension of the second conductor pattern, the opaque first conductor pattern formed on the transparent insulating substrate is used as a photomask to expose the second conductor pattern from the second surface by exposure. Even when the dimension inspection pattern (figure) for the second conductor pattern and the second conductor pattern is formed to judge the quality of the width dimension of the conductor pattern, it is not necessary to measure the actual dimension of the conductor pattern. Therefore, the quality of the pattern dimension can be visually judged, and the judgment error is small, and the accuracy of the pattern dimension is improved.

[Brief description of drawings]

FIG. 1 is a plan view of an inspection figure according to the present invention.

FIG. 2 is an explanatory diagram of a method for inspecting a conductor pattern of a semiconductor device according to the present invention.

FIG. 3 is an explanatory diagram of a method for inspecting a conductor pattern.

FIG. 4 is an explanatory diagram of a method for inspecting a conductor pattern.

FIG. 5 is an explanatory diagram of a process for forming an actual device.

FIG. 6 is a plan view showing another example of the inspection graphic.

FIG. 7 is a plan view showing a conventional example of an inspection figure.

FIG. 8 is a sectional view showing a part of a conventional example of an actual device.

FIG. 9 is a sectional view showing a part of a conventional example of an actual device.

FIG. 10 is an explanatory diagram of a conventional conductor pattern inspection method using an inspection pattern.

FIG. 11 is an explanatory diagram of a conventional conductor pattern inspection method using an inspection pattern.

FIG. 12 is an explanatory diagram of a conventional conductor pattern inspection method using an inspection pattern.

[Explanation of symbols]

50 Dimension inspection pattern of second conductor pattern, 53 Third pattern, 55 First reference pattern, 57 Second pattern, 60 Dimension inspection pattern formed simultaneously with formation of second conductor pattern, 63 Fifth Figure of the 65th second
Standard figure, 67 third figure, 100 actual device, 110 glass substrate, 112 second layer, 11
4 Third Layer, 120 First Conductor Pattern, 13
0 Second conductor pattern.

Claims (2)

[Claims] 1. A step of forming an opaque first conductor pattern, a dimension inspection pattern of the first conductor pattern, and a dimension inspection pattern of the second conductor pattern on a transparent insulating substrate, and the opaque first A step of forming a second conductor pattern and a second conductor pattern dimension inspection pattern by exposure from the substrate side using the first conductor pattern and the second conductor pattern dimension inspection pattern as a photomask; And a step of inspecting the dimension of the second conductor pattern using a pattern for dimension inspection of the conductor pattern, wherein the dimension inspection of the second conductor pattern is performed by the dimension inspection of the second conductor pattern formed at the time of forming the first conductor pattern. And the second conductor pattern dimension inspection pattern formed when the second conductor pattern is formed. Dimensional inspection method of the conductor patterns of the body device. 2. A pattern for dimensional inspection of a second conductor pattern has a first figure serving as a reference for dimensional inspection and a dimension in the width direction which is larger than that of the first figure by a maximum deviation value of dimensional variation. The first figure, the second figure having a similar shape, and the third figure having a similar shape in which the dimension in the width direction is reduced by the minimum deviation value of the dimensional variation with respect to the first figure. And the third figure are arranged in parallel with each other, and the center line of the first figure, the center line of the second figure, and the center line of the third figure are arranged on the same line. 2. The method for inspecting the size of a conductor pattern of a semiconductor device according to claim 1.