JPH088268B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH088268B2
JPH088268B2 JP24249786A JP24249786A JPH088268B2 JP H088268 B2 JPH088268 B2 JP H088268B2 JP 24249786 A JP24249786 A JP 24249786A JP 24249786 A JP24249786 A JP 24249786A JP H088268 B2 JPH088268 B2 JP H088268B2
Authority
JP
Japan
Prior art keywords
bonding pad
land
insulating substrate
semiconductor device
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP24249786A
Other languages
Japanese (ja)
Other versions
JPS6396931A (en
Inventor
邦昭 内海
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP24249786A priority Critical patent/JPH088268B2/en
Publication of JPS6396931A publication Critical patent/JPS6396931A/en
Publication of JPH088268B2 publication Critical patent/JPH088268B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68Shapes or dispositions thereof
    • H10W70/682Shapes or dispositions thereof comprising holes having chips therein
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置に関し、特に半導体チップを搭載
する絶縁性基板における配線及び半田付け用ランドに関
する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a wiring and a soldering land in an insulating substrate on which a semiconductor chip is mounted.

従来の技術 第2図は従来例における外部端子が絶縁性基板の側壁
に設けられたLCC(Leadless Chip Carrier)形の半導体
装置の断面図であり、1は絶縁性基板、2は絶縁性基板
1に搭載された半導体チップ、3は絶縁性基板1のボン
ディングパッド4と半導体チップ2の電極を結線するボ
ンディングワイヤ、5は外部端子、6はボンディングパ
ッド4と外部端子5を結線する金属配線である。
2. Description of the Related Art FIG. 2 is a cross-sectional view of an LCC (Leadless Chip Carrier) type semiconductor device in which an external terminal is provided on a side wall of an insulating substrate in the conventional example, where 1 is an insulating substrate and 2 is an insulating substrate 1. A semiconductor chip mounted on the substrate 3, a bonding wire 4 for connecting the bonding pad 4 of the insulating substrate 1 and an electrode of the semiconductor chip 2, 5 is an external terminal, and 6 is a metal wiring for connecting the bonding pad 4 and the external terminal 5. .

高周波信号を扱う電気回路の場合、信号の流れる伝送
路の特性インピーダンスと同じ値の抵抗で伝送路の最後
が終端されていないと正常な信号の伝送は行われない。
そこで半導体装置をプリント基板に搭載して使用する場
合、信号が入力する半導体装置の外部端子5近傍で信号
伝送路を抵抗で終端することが行われている。しかしな
がら外部端子5の間隔が0.5mmや0.25mmのように狭くな
ってくると抵抗の大きさがそれらに比較して大きいた
め、複数の入力用の外部端子5同士が接近している場
合、抵抗の位置を半導体装置からかなり離さないと抵抗
を接続できない。したがってこのような場合、抵抗で終
端された位置から外部端子5までの配線部分と、半導体
装置内部における外部端子5とボンディングパッド4及
びその間の金属配線6の部分は特性インピーダンス不整
合の状態で信号が伝送することになり正常な伝送は行わ
れなくなる。
In the case of an electric circuit that handles high-frequency signals, normal signal transmission is not possible unless the end of the transmission line is terminated with a resistor having the same value as the characteristic impedance of the transmission line through which the signal flows.
Therefore, when the semiconductor device is mounted on a printed circuit board and used, the signal transmission path is terminated with a resistor near the external terminal 5 of the semiconductor device to which a signal is input. However, when the distance between the external terminals 5 becomes narrower, such as 0.5 mm or 0.25 mm, the resistance is larger than those, so if the external terminals 5 for input are close to each other, the resistance The resistor cannot be connected unless the position of is considerably separated from the semiconductor device. Therefore, in such a case, the wiring portion from the position terminated by the resistor to the external terminal 5, the external terminal 5 inside the semiconductor device, the bonding pad 4 and the portion of the metal wiring 6 between them are signaled in a state of characteristic impedance mismatch. Will be transmitted and normal transmission will not be performed.

また、電源用バイパスコンデンサを接続する場合も上
記と同様にコンデンサの位置から半導体装置内部のボン
ディングパッド4までが長くなり、そのインピーダンス
の影響で電源用バイパスコンデンサの電源の安定化の効
果が弱くなる。
Also, when a bypass capacitor for power supply is connected, the distance from the position of the capacitor to the bonding pad 4 inside the semiconductor device becomes long, and the effect of stabilizing the power supply of the bypass capacitor for power supply becomes weak due to the impedance thereof. .

発明が解決しようとする問題点 上記のように半導体装置をプリント基板に搭載してプ
リント基板上において抵抗で信号の終端を行う場合、終
端位置から半導体装置内部のボンディングパッドまでの
距離が長くなり正常な信号伝送が行われなくなる。ま
た、電源用バイパスコンデンサの場合も同様にその効果
が弱くなる。
Problems to be Solved by the Invention As described above, when a semiconductor device is mounted on a printed circuit board and a signal is terminated by a resistor on the printed circuit board, the distance from the termination position to the bonding pad inside the semiconductor device becomes long and normal. Signal transmission is stopped. Also, in the case of a power supply bypass capacitor, the effect is similarly weakened.

本発明は上記欠点に鑑みなされたものであり、ボンデ
ィングパッドの近くで終端用抵抗や電源用バイパスコン
デンサの接点が可能な半導体装置を提供することを目的
とする。
The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a semiconductor device capable of contacting a terminating resistor and a power supply bypass capacitor near a bonding pad.

問題点を解決するための手段 本発明は上記問題点を解決するためになされたもので
あり、半導体装置裏面で終端用抵抗及び電源用バイパス
コンデンサ等を接続するために半田付け用ランドを設
け、それらに対応するボンディングパッドにスルーホー
ルを介して結線するものである。
Means for Solving the Problems The present invention has been made to solve the above problems, and a soldering land is provided on the rear surface of a semiconductor device to connect a terminating resistor, a power supply bypass capacitor, and the like. The bonding pads corresponding to these are connected through through holes.

作用 ボンディングパッドをスルーホールを介して半導体装
置裏面の半田付け用ランドに結線し、半導体装置裏面に
おいてバイアス電源用の半田付け用ランドとの間に終端
用抵抗または電源用バイパスコンデンサを接続すること
により、上記部品接続位置とボンディングパッドとの距
離を短かくすることができる。また抵抗終端の場合、ボ
ンディングパッドまで特性インピーダンスを保つことが
できる。
By connecting the bonding pad to the soldering land on the back side of the semiconductor device through the through hole and connecting the termination resistor or power supply bypass capacitor between the soldering land for bias power supply on the back side of the semiconductor device. The distance between the component connection position and the bonding pad can be shortened. Further, in the case of resistance termination, the characteristic impedance can be maintained up to the bonding pad.

実施例 以下図面を参照して本発明の実施例を説明する。Embodiments Embodiments of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例におけるLCC形半導体装置
の図面であり、同図aは断面図、同bは裏面から見た平
面図である。但しし、実装された部品を含む。従来例と
同一番号のものは同じものを示す。
FIG. 1 is a drawing of an LCC type semiconductor device in one embodiment of the present invention, FIG. 1A is a sectional view, and FIG. 1B is a plan view seen from the back surface. However, the mounted parts are included. The same numbers as in the conventional example indicate the same.

7,71,72は終端抵抗及びバイパスコンデンサを半田付
けするための部品用ランド、8は部品用ランド7,71,72
との間に上記部品を半田付けするための電源用ランド、
9はスルーホール、10,11は終端用抵抗、12はバイパス
コンデンサである。
7,71,72 are component lands for soldering terminating resistors and bypass capacitors, and 8 are component lands 7,71,72
Power supply land for soldering the above parts between
Reference numeral 9 is a through hole, 10 and 11 are termination resistors, and 12 is a bypass capacitor.

本例においては部品用ランド7、及び71は信号入力の
端子に対応し、部品用ランド72は電源の端子に対応す
る。その他の出力端子等には必ずしもこれらのスルーホ
ール9や部品用ランド7,71,72を設ける必要はなく、終
端を必要とする入力端子及び電源端子にのみ設ければよ
い。電源用ランド8には外部から電源を供給する。本例
の場合、同一のランドとなっているが複数の電源を必要
とする場合はそれに対応して複数個の電源用ランドを設
ければよい。
In this example, the component lands 7 and 71 correspond to signal input terminals, and the component lands 72 correspond to power supply terminals. It is not always necessary to provide these through holes 9 and component lands 7, 71, 72 for other output terminals and the like, and they may be provided only for input terminals and power supply terminals that require termination. Power is supplied to the power land 8 from the outside. In the case of this example, although the land is the same, if a plurality of power supplies are required, a plurality of power supply lands may be provided correspondingly.

たとえばECLレベルの入力の場合、入力端はバイアス
電圧−2V、終端抵抗50Ωが接続されるが、このような場
合、電源用ランド8には外部から−2Vを供給し、終端用
抵抗10,11を50Ωの抵抗にすればよい。
For example, in the case of an ECL level input, a bias voltage of −2V and a terminating resistor of 50Ω are connected to the input end. In such a case, −2V is externally supplied to the power supply land 8 and the terminating resistors 10 and 11 are connected. Should be a resistance of 50Ω.

また、外部端子5、金属配線6、スルーホール9が所
望の特性インピーダンスを有するようにしておく、つま
り本実施例におけるように終端用抵抗が50Ωであれば、
当然それに合わせて上記3者の特性インピーダンスを50
Ωとしておけば、ほぼボンディングパッド4まで正常な
信号伝送ができる。終端抵抗10,11は裏面にあるので、
半導体装置の外側のプリント基板上で終端する場合より
はるかにボンディングパッド4の近くで終端できること
になる。
Further, the external terminal 5, the metal wiring 6, and the through hole 9 are set to have a desired characteristic impedance, that is, if the termination resistance is 50Ω as in the present embodiment,
Naturally, the characteristic impedances of the above three parties are set to 50 according to it.
If Ω is set, normal signal transmission up to the bonding pad 4 can be performed. Since the terminating resistors 10 and 11 are on the back side,
It is possible to terminate much closer to the bonding pad 4 than when terminating on the printed circuit board outside the semiconductor device.

終端の場合と同様にバイパスコンデンサ12を接続する
場合、できるだけボンディングパッド4に近いほうがよ
い。近ければ近いほど電源の安定化に効果がある。した
がってプリント基板上で接続するよりも本例のように半
導体装置裏面で接続するほうが効果が大きくなる。
When connecting the bypass capacitor 12 as in the case of the termination, it is better to be as close to the bonding pad 4 as possible. The closer it is, the more effective it is in stabilizing the power supply. Therefore, it is more effective to connect on the back surface of the semiconductor device as in this example than to connect on the printed circuit board.

発明の効果 以上述べてきたように、本発明によれば、ボンディン
グパッドまで正常な高周波の信号が伝送でき、また電源
のバイパスによる安定化の効果を大きくでき、その実用
的効果は大なるものがある。
EFFECTS OF THE INVENTION As described above, according to the present invention, a normal high-frequency signal can be transmitted to the bonding pad, and the stabilization effect by bypassing the power supply can be increased, and its practical effect is large. is there.

【図面の簡単な説明】[Brief description of drawings]

第1図aは本発明の一実施例におけるLCC形半導体装置
の断面図、第1図bは同装置を裏面からみた平面図、第
2図は従来におけるLCC形半導体装置の断面図である。 1……絶縁性基板、2……半導体チップ、3……ボンデ
ィングワイヤ、4……ボンディングパッド、5……外部
端子、6……金属配線、7……部品用ランド、8……電
源用ランド、9……スルーホール、10……終端用抵抗、
12……バイパスコンデンサ。
1A is a sectional view of an LCC type semiconductor device according to an embodiment of the present invention, FIG. 1B is a plan view of the same device seen from the back side, and FIG. 2 is a sectional view of a conventional LCC type semiconductor device. 1 ... Insulating substrate, 2 ... Semiconductor chip, 3 ... Bonding wire, 4 ... Bonding pad, 5 ... External terminal, 6 ... Metal wiring, 7 ... Component land, 8 ... Power supply land , 9 ... Through hole, 10 ... Termination resistor,
12 ... Bypass capacitor.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁性基板及びこの基板に搭載された半導
体チップからなり、それぞれのボンディングパッドと対
応する電極とが金属線により結線されており、前記ボン
ディングパッドは前記絶縁性基板の側面の外部端子へ金
属配線で結線され、かつ前記ボンディングパッドの近傍
に設けられたスルーホールを介して前記絶縁性基板裏面
の半田付け用ランドに結線されており、前記絶縁性基板
の裏面には前記半田付け用ランドとの間に終端用抵抗が
半田付けでき、また外部からの電源線が接続可能な別の
半田付け用ランドが設けられ、前記終端用抵抗に接続さ
れるべき信号伝搬側の前記スルーホール、前記金属配線
および前記外部端子が前記終端用抵抗と同一の値の特性
インピーダンスを有することを特徴とする半導体装置。
1. An insulating substrate and a semiconductor chip mounted on the substrate, each bonding pad and a corresponding electrode being connected by a metal wire, and the bonding pad is provided outside a side surface of the insulating substrate. It is connected to a terminal with a metal wiring and is connected to a soldering land on the back surface of the insulating substrate through a through hole provided in the vicinity of the bonding pad. The through-hole on the signal propagation side that should be connected to the termination resistor is provided with another termination land that can be soldered to the termination land and can be connected to an external power supply line. The semiconductor device, wherein the metal wiring and the external terminal have a characteristic impedance of the same value as the terminating resistor.
【請求項2】絶縁性基板及びこの基板に搭載された半導
体チップからなり、それぞれのボンディングパッドと対
応する電極とが金属線により結線されており、前記ボン
ディングパッドは前記絶縁性基板の側面の外部端子へ金
属配線で結線され、かつ前記ボンディングパッドの近傍
に設けられたスルーホールを介して前記絶縁性基板裏面
の半田付け用ランドに結線されており、前記絶縁性基板
の裏面には前記半田付け用ランドとの間にバイパス用コ
ンデンサが半田付けでき、また外部からの電源線が接続
可能な別の半田付け用ランドが設けられたことを特徴と
する半導体装置。
2. An insulating substrate and a semiconductor chip mounted on the substrate, each bonding pad and a corresponding electrode being connected by a metal wire, the bonding pad being outside the side surface of the insulating substrate. It is connected to a terminal with a metal wiring and is connected to a soldering land on the back surface of the insulating substrate through a through hole provided in the vicinity of the bonding pad. A semiconductor device, wherein a bypass capacitor can be soldered to the use land, and another solder land to which a power line from the outside can be connected is provided.
JP24249786A 1986-10-13 1986-10-13 Semiconductor device Expired - Lifetime JPH088268B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24249786A JPH088268B2 (en) 1986-10-13 1986-10-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24249786A JPH088268B2 (en) 1986-10-13 1986-10-13 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6396931A JPS6396931A (en) 1988-04-27
JPH088268B2 true JPH088268B2 (en) 1996-01-29

Family

ID=17089968

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24249786A Expired - Lifetime JPH088268B2 (en) 1986-10-13 1986-10-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH088268B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2979930B2 (en) * 1993-10-28 1999-11-22 富士電機株式会社 Power semiconductor device package
US5600175A (en) * 1994-07-27 1997-02-04 Texas Instruments Incorporated Apparatus and method for flat circuit assembly
US5608261A (en) * 1994-12-28 1997-03-04 Intel Corporation High performance and high capacitance package with improved thermal dissipation

Also Published As

Publication number Publication date
JPS6396931A (en) 1988-04-27

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