JPH088271A - Bipolar transistor emitter structure and manufacturing method thereof - Google Patents

Abstract

(57) [Summary] [Object] The present invention improves the junction breakdown voltage at the junction between the emitter layer and the base layer in the vicinity of the surface of the substrate to suppress the occurrence of junction leakage and the occurrence of crystal defects.
To improve the transistor characteristics of the bipolar transistor. [Structure] A high-concentration diffusion layer 22 formed in a part of the upper layer of the base layer 21, and a side junction of the high-concentration diffusion layer 22 in the base layer 21 are formed with a junction shallower than the high-concentration diffusion layer 22 The emitter layer 24 has a structure including the low-concentration diffusion layer 23.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an emitter structure of a bipolar transistor and a manufacturing method thereof.

[0002]

2. Description of the Related Art An emitter structure of a bipolar transistor will be described with reference to a schematic sectional view shown in FIG. The figure shows a vertical NPN bipolar transistor 101.

As shown in the figure, a base layer 112 made of a P ⁺ -type diffusion layer is formed on the upper layer of the semiconductor substrate 111. On a part of the upper layer of the base layer 112, an emitter layer 113 made of an N ⁺ type diffusion layer is formed. An interlayer insulating film 121 is formed on the surface of the semiconductor substrate 111. Further, on the interlayer insulating film 121,
An emitter electrode 131 and a base electrode 132, which are connected to the emitter layer 113 and the base layer 112, are formed.

The impurity concentration distribution in the emitter layer 113 and the base layer 112 of the bipolar transistor will be described with reference to FIG. The vertical axis of this figure shows the impurity concentration, and the horizontal axis shows the diffusion depth from the surface level of the base layer 112 and the emitter layer 113 (the interface level between the emitter layer 113 and the emitter electrode 131).

As shown in the figure, the concentration curve Dp of the P-type impurity forming the base layer (112) becomes lower as the diffusion depth becomes deeper. This is the base layer (11
This is because by forming an internal electric field in 2), the carrier mobility is increased and the operating speed of the transistor is increased.
The diffusion depth of the base layer (112) is about 0.5 μm.
It has become m.

Further, N forming the emitter layer (113)
The concentration curve Dn of the type impurities becomes lower as the diffusion depth becomes deeper like the concentration curve Dp, but the diffusion depth becomes shallower than the concentration curve Dp. The diffusion depth of the emitter layer (113) is about 0.3 μm.

The junction between the emitter layer (113) and the base layer (112) near the substrate surface is such that the concentration of N-type impurities forming the emitter layer (113) is 10 ²⁰ cm.
^-3 , and the concentration of the P-type diffusion layer forming the base layer 112 is 10 ¹⁸ cm ^-3 . Therefore, high concentration PN
It is a joint.

[0008]

However, in the conventional bipolar transistor, since the PN junction between the emitter layer and the base layer in the vicinity of the surface of the substrate is a high-concentration junction, the junction breakdown voltage is, for example, about 3. It is 7V. When the junction breakdown voltage is small as described above, a tunneling leak current occurs even at an applied voltage equal to or lower than the breakdown voltage. Further, since the PN junction is formed in a state where two types of high-concentration impurities are mixed, crystal defects are likely to be induced at the junction or in the vicinity thereof. When a crystal defect occurs, for example, a leak current occurs due to the crystal defect, and the electrical characteristics of the bipolar transistor deteriorate.

The present invention has been made in order to solve the above-mentioned problems, and "decreases junction breakdown voltage" at a junction between an emitter layer and a base layer in a bipolar transistor,
An object of the present invention is to provide an emitter structure of a bipolar transistor and a manufacturing method thereof, which are excellent in solving the disadvantages such as "generation of junction leak" and "generation of crystal defect".

[0010]

SUMMARY OF THE INVENTION The present invention is an emitter structure of a bipolar transistor and a method of manufacturing the same for achieving the above object.

That is, in the emitter structure of the bipolar transistor, the high-concentration diffusion layer is formed in a part of the upper layer of the base layer, and the side periphery of the high-concentration diffusion layer in the base layer is higher than the high-concentration diffusion layer. A low-concentration diffusion layer having a shallow junction is provided.

The method of manufacturing the emitter of the bipolar transistor is performed as follows. That is, in the first step,
After forming the first film on the semiconductor substrate, an opening is formed in the first film on the emitter formation planned region in the base layer formation region of the semiconductor substrate. Next, in a second step, a first impurity for forming a low concentration diffusion layer is introduced into the emitter formation planned region exposed in the opening. Then, in a third step, sidewalls are formed on the inner wall of the opening. Then, in a fourth step, a second impurity having the same conductivity type as the first impurity is introduced into the emitter formation region exposed inside the sidewall at a concentration higher than the doping concentration of the first impurity.
After that, in a fifth step, the first impurity is diffused more widely than the second impurity in the surface direction of the semiconductor substrate, and the second impurity is diffused deeper than the first impurity in the depth direction of the semiconductor substrate. A low concentration diffusion layer formed by diffusing the first impurity and a high concentration diffusion layer formed by diffusing the second impurity are formed in the upper layer portion.

[0013]

In the emitter structure of the bipolar transistor having the above structure, the high-concentration diffusion layer is formed in a part of the upper layer of the base layer, and the high-concentration diffusion layer is formed on the side periphery of the high-concentration diffusion layer in the base layer. A low-concentration diffusion layer having a shallow junction is also provided. Therefore, in the vicinity of the surface of the semiconductor substrate, the low concentration diffusion layer of the emitter layer and the high concentration diffusion layer of the base layer are joined. In this way, since the impurity concentration at the junction between the emitter layer and the base layer changes gently, the concentration of the electric field at the junction is relieved. Further, since the junction between the emitter layer and the base layer is the junction between the low concentration diffusion layer and the high concentration diffusion layer, crystal defects at the junction are reduced.

In the method of manufacturing the emitter of the bipolar transistor described above, after the first film is formed on the semiconductor substrate,
An opening is formed in the first film on the emitter formation planned region in the base layer formation region, and then the first impurity is introduced from the opening to the emitter formation planned region. For this reason,
The junction between the emitter layer and the base layer near the surface of the semiconductor substrate is a junction between the low-concentration diffusion layer formed by diffusing the introduced first impurity and the base layer. In addition, after forming the sidewall on the inner wall of the opening, the second impurity is introduced into the emitter formation region exposed inside the sidewall at a higher concentration than the doping concentration of the first impurity.
Therefore, the second impurity is blocked by the sidewall and is not introduced below the sidewall.
The impurities are introduced in a narrower range than the region where the first impurities are introduced. Therefore, the low-concentration diffusion layer formed by diffusing the first impurity is formed on the side periphery of the high-concentration diffusion layer formed by diffusing the second impurity in a junction state shallower than the high-concentration diffusion layer. As a result, the change in the impurity concentration at the junction between the emitter layer and the base layer becomes gentle.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the schematic sectional view of FIG. In the figure, the vertical NPN bipolar transistor 1 is shown as an example.

As shown in the figure, the semiconductor substrate 11 is composed of, for example, a P-type silicon substrate (hereinafter referred to as a silicon substrate) 12 and an N-type epitaxial layer (hereinafter referred to as an epitaxial layer) 13 formed on the upper surface thereof. An N type buried diffusion layer (hereinafter referred to as a buried layer) 14 is formed between the silicon substrate 12 and the epitaxial layer 13. Furthermore, the base layer formation scheduled region 1 is formed on the epitaxial layer 13.
An element isolation region 17 that separates the region 5 from the region 16 where the collector extraction diffusion layer is to be formed is formed.

A base layer 21 made of a P ⁺ type diffusion layer is formed on the upper layer portion of the epitaxial layer 13. The surface concentration of the base layer 21 is about 10 ¹⁸ cm ^-3.
Is set to

N ⁺ is formed on a part of the upper layer of the base layer 21.
A high-concentration diffusion layer 22 composed of a mold diffusion layer is formed.
The high-concentration diffusion layer 22 is formed of N-type impurities such as arsenic (A
s) is doped. The impurity concentration on the surface side of the high concentration diffusion layer 22 is set to, for example, about 10 ²⁰ cm ^-3 . Therefore, this impurity concentration is almost equal to the value of the impurity concentration on the surface side in the emitter layer of the conventional NPN bipolar transistor. The impurity concentration on the bottom surface side of the high concentration diffusion layer 22 is set to, for example, about 10 ¹⁷ cm ^-3 .

Further, on the side periphery of the high-concentration diffusion layer 22 in the base layer 21, a low-concentration diffusion layer 23 composed of an N ^-- type diffusion layer having a junction shallower than the high-concentration diffusion layer 22.
Are formed. The low-concentration diffusion layer 23 is formed by doping N-type impurities such as phosphorus (P). The impurity concentration on the surface side of the low concentration diffusion layer 23 is set to, for example, about 5 × 10 ¹⁸ cm ⁻³ . Therefore, this impurity concentration is about two orders of magnitude lower than the value of the impurity concentration on the surface side in the emitter layer of the conventional NPN bipolar transistor.

As described above, the high-concentration diffusion layer 22 and the low-concentration diffusion layer 23 constitute the emitter layer 24.

Further, the epitaxial layer 13 is provided with a plug diffusion layer 25 formed of an N ⁺ type diffusion layer which is joined to the buried layer 14 without joining to the base layer 21. A collector extraction diffusion layer 26 is formed thereabove. Further, an interlayer insulating film 18 is formed on the epitaxial layer 13.
Are formed. The interlayer insulating film 18 has contact holes 27, 28, 29 communicating with the base layer 21, the emitter layer 24, and the collector extraction diffusion layer 25. Then, a base electrode 30, an emitter electrode 31 and a collector electrode 32 are sequentially formed in each of the contact holes 27, 28 and 29.

As described above, the emitter layer 24 of the vertical NPN bipolar transistor 1 is composed of the high concentration diffusion layer 22 and the low concentration diffusion layer 23.

In the emitter structure of the bipolar transistor 1 having the above structure, the high-concentration diffusion layer 22 is formed in a part of the upper layer of the base layer 21, and the base layer 21 is further formed.
A low-concentration diffusion layer 23 having a junction shallower than the high-concentration diffusion layer 22 is provided on the side periphery of the high-concentration diffusion layer 22 inside. Therefore, in the vicinity of the surface of the epitaxial layer 13 of the semiconductor substrate 11, the low-concentration diffusion layer 23 of the emitter layer 24 and the base layer 21 are bonded, so that the impurity concentration at the junction of the emitter layer 24 and the base layer 21 is gentle. Has changed to. Therefore, the concentration of the electric field on the junction is relieved. The junction breakdown voltage between the emitter and the base is about 11.6 V, which is about 3.1 times higher than that of the conventional bipolar transistor. Further, even if the applied voltage is lower than the breakdown voltage, almost no leak current is generated (1 pA or less).

Further, since the emitter layer 24 is joined to the base layer 21 by the low-concentration diffusion layer 23, crystal defects at the joint portion are reduced.

The basic characteristics and performance of the bipolar transistor are determined by the vertical structure immediately below the emitter. In the bipolar transistor 1, the junction between the bottom of the emitter layer 24 and the base layer 21 has a high concentration diffusion. Layer 2
2 and the base layer 21 are joined. Therefore, since the junction is similar to that of the conventional bipolar transistor, the basic characteristics and performance are equivalent to those of the conventional bipolar transistor.

Next, a method of manufacturing the emitter of the bipolar transistor 1 will be described with reference to manufacturing process diagrams (No. 1) and (No. 2) of FIGS. 2 and 3 show, as an example, a method of manufacturing an emitter of a vertical NPN bipolar transistor. Further, in the drawing, the same components as those described in FIG. 1 are designated by the same reference numerals.

As shown in FIG. 2A, an N-type buried diffusion layer (hereinafter referred to as a buried layer) is formed on a part of an upper layer of a P-type silicon substrate (hereinafter referred to as a silicon substrate) 12 by a normal process. ) 14 is formed. Then, an N-type epitaxial layer (hereinafter referred to as an epitaxial layer) 13 is formed on the upper surface of the silicon substrate 12. At that time, the buried layer 14 is also diffused into the lower layer of the epitaxial layer 13. In this way, the semiconductor substrate 11 is formed.

Next, a plug diffusion layer 25, which is an N ⁺ diffusion layer and is joined to the buried layer 14, is formed on a part of the epitaxial layer 13. Further, for example, by the LOCOS method, an element isolation region 17 for partitioning the base layer formation planned region 15 and the plug diffusion layer 25 is formed in the upper layer of the epitaxial layer 13. Then, an impurity 51 for forming the base layer (21) is introduced into a part of the upper layer of the epitaxial layer 13 which is the base layer formation scheduled region 15. Since the manufacturing method up to this point is the same as the manufacturing method of a normal bipolar transistor, it will be briefly described.

After that, an oxide film 41 having a thickness of, for example, 30 nm is formed on the surface of the epitaxial layer 13 of the semiconductor substrate 11 by, for example, a thermal oxidation method.

Then, the first step is performed. In this process,
For example, the first film 42 is formed on the oxide film 41 and the element isolation region 17 by the CVD method. The first film 42 is, for example, polycrystalline silicon or polycrystalline silicon containing impurities used for doping, and has a thickness of, for example, 400 nm.
To the thickness of.

After that, as shown in FIG. 2B, the first film 42 is formed by lithography and etching.
The portion indicated by the two-dot chain line is removed to form an opening 43 in the first film 42 on the emitter formation scheduled region 19 in the base layer formation scheduled region 15. At this time, the first film 42 on the plug diffusion layer 25 is also removed. Incidentally. In (2) and subsequent figures, the illustration of the first impurity (51) is omitted.

Next, the second step is performed. In this step, for example, by ion implantation, the first impurity 52 forming a low-concentration diffusion layer is exposed in the emitter formation planned region 19 exposed in the opening 43 by using the first film 42 as a mask. Doping consistently. As the first impurity 52, for example, phosphorus is used. The dose amount at this time is 10 ¹⁸ cm which is the surface concentration of the base layer to be formed.
^It is set to be about 5 × 10 ¹⁸ cm ⁻³ , which is slightly higher than ⁻³ .

Subsequently, the third step shown in FIG. 2C is performed. In this step, the second film 44 is formed on the entire surface on the side of the first film 42 together with the inner wall of the opening 43 by, for example, the CVD method. The second film 44 is made of, for example, a silicon oxide film and has a film thickness of, for example, 300 nm.

Then, as shown in FIG. 2D, anisotropic etching is performed to etch back the entire surface of the second film 44. Then, the portion of the second film 44 indicated by the two-dot chain line in the drawing is removed, and the side wall 45 is formed by the second film (44) left on the inner wall of the opening 43.

Thereafter, the fourth step shown in FIG. 3 (5) is performed. In this step, for example, by ion implantation, a second impurity 53 having the same conductivity type as the first impurity 52 and the first impurity 52 are formed in the emitter formation planned region 19 exposed inside the sidewall 45 of the opening 43. The film 42 and the sidewall 45 are used as a mask to dope in a self-aligned manner at a concentration higher than the doping concentration of the first impurity 52.
Arsenic is used as the second impurity 52, and the dose amount of the second impurity 53 is set to, for example, about 10 ¹⁶ cm ⁻² . In the above ion implantation method, the sidewall 45 blocks the doping of the second impurity 53. For this reason,
The second impurity 53 is not doped in the epitaxial layer 13 below the sidewall 45. Therefore, the epitaxial layer 13 below the sidewall 45 is
Then, only the first impurity 52 is doped. The second impurity 53 is also introduced into the upper layer of the plug diffusion layer 25.

Then, the fifth step shown in FIG. 3 (6) is performed. In this step, the activation annealing process is performed to
The impurities (52) are diffused more widely than the second impurities (53) in the surface direction of the epitaxial layer 13 of the semiconductor substrate 11. At the same time, the second impurity (53) is diffused deeper than the first impurity (52) in the depth direction of the epitaxial layer 13. As a result, the high-concentration diffusion layer 22 in which the second impurities (53) are diffused is formed in the upper layer portion of the epitaxial layer 13, and the first impurities (52) are diffused in the side peripheral side of the high-concentration diffusion layer 22. And the low-concentration diffusion layer 23 is formed. Then, when all the steps are completed, the surface concentration of the low concentration diffusion layer 23 formed by diffusing the first impurity (52) becomes about 5 × 10 ¹⁸ cm ⁻³ . Further, the surface concentration of the high-concentration diffusion layer 22 formed by diffusing the second impurity (52) becomes about 10 ²⁰ cm ⁻³ . In this way,
The emitter layer 24 including the high concentration diffusion layer 22 and the low concentration diffusion layer 23 is manufactured. At the same time, a collector extraction diffusion layer 26 is formed on the plug diffusion layer 25.

Then, by etching, the first film 4 is formed.
Remove 2. Then, as shown in (7) of FIG. 3, a silicon oxide-based insulating film 46 such as boron phosphorus silicate glass (BPSG) or phosphorus silicate glass (PSG) is formed on the entire surface on the epitaxial layer 13 side by, for example, the CVD method. To do. Then, contact holes 27, 28 and 29 are formed to reach the base layer 21, the emitter layer 24 and the collector extraction diffusion layer 26 by lithography and etching. After that, each contact hole 27, 28, 29 is formed by a normal wiring forming technique.
A base electrode 30, an emitter electrode 31, and a collector electrode 32 connected to the base layer 21, the emitter layer 24, and the collector extraction diffusion layer 26 are formed through. The bipolar transistor 1 is formed as described above.

In the above manufacturing method, first, the first impurity 52 is introduced from the opening 43 on the emitter formation planned region 19, so that the first impurity 52 is diffused into the junction region with the base layer 21. The concentration diffusion layer 23 is formed. Further, after forming the sidewall 45 on the inner wall of the opening 43, the second impurity 53 is introduced into the emitter formation region 19 inside the sidewall 45 at a concentration higher than that of the first impurity. Therefore, the second impurity 53 is shielded by the sidewall 45 and is not introduced below the sidewall 45. Therefore, the second impurity 53 is introduced in a range narrower than the region where the first impurity 52 is introduced. Moreover, since the second impurity is introduced deeper than the first impurity, the low-concentration diffusion layer 23 formed by diffusing the first impurity 52 is formed on the side periphery of the high-concentration diffusion layer 22 formed by diffusing the second impurity 53. , The high-concentration diffusion layer 22 is shallower than the high-concentration diffusion layer 22. As a result, the change in the impurity concentration at the junction between the emitter layer 24 and the base layer 21 becomes gentle.

Next, an example in which the method for manufacturing the above bipolar transistor is applied to the BiCMOS process will be described with reference to the manufacturing process diagrams of FIGS. Figures 4 and 5
Now, in the normal Bi-CMOS process, only the process to which the present invention is applied will be described, and the description of the other processes will be omitted. Further, the same components as those described with reference to FIGS. 2 and 3 are designated by the same reference numerals. Bi-CMOS
Of these, the NPN bipolar transistor and the NMOS transistor are shown, and the PMOS transistor is not shown.

In order to apply the emitter manufacturing method of the present invention to the conventional Bi-CMOS process, the conventional Bi-CMO method is used.
In S process, NMOS transistor and PMOS
It is applied from the step of forming each gate electrode with a transistor to the step of forming each source / drain. Here, since the method of forming the PMOS transistor is the same as the conventional process, the description will be simplified and the NMOS transistor and the bipolar transistor will be described.

That is, as shown in FIG. 4A, the exposed surface layer of the epitaxial layer 13 of the semiconductor substrate 11 is oxidized by, for example, a thermal oxidation method to form a region where an NMOS transistor is to be formed (hereinafter referred to as an NMOS region). 2)
Then, a gate oxide film 61 is formed. At the same time, an oxide film 41 is formed on the surface layer of the epitaxial layer 13 in the area where the bipolar transistor is to be formed (hereinafter referred to as the bipolar area) 3.
To form. At the same time, a gate oxide film (not shown) of the PMOS transistor is formed. The gate oxide film 61 and the oxide film 41 are formed to have a film thickness of, for example, about 30 nm.

Then, a first film 42 is deposited on the entire surface on the side of the gate oxide film 61 and the oxide film 41 by the CVD method. The first film 42 is, for example, polycrystalline silicon containing phosphorus as an impurity with a concentration of about 10 ²¹ cm ⁻³ , and is formed with a thickness of 400 nm, for example.

Subsequently, as shown in FIG. 4B, the portion indicated by the chain double-dashed line of the first film 42 is removed by the lithography technique and etching, and the gate oxide film 61 is formed.
A gate electrode 62 is formed of the first film (42) at a predetermined position above. At the same time, the opening 43 is formed in the first film 42 on the emitter formation planned region 19 of the bipolar region 3, and the first film 42 on the plug diffusion layer 25 is removed. At the same time, a gate electrode (not shown) is formed at a predetermined position on the gate oxide film in the region where the PMOS transistor is to be formed (hereinafter referred to as the PMOS region).

Next, as shown in FIG. 4C, a resist is applied to the entire surface on the epitaxial layer 13 side to form a resist film 81. Subsequently, the NMOS region 2 and the opening 43 are formed in the resist film 81 by the lithography technique.
Openings 82 and 83 exposing and are formed.

Then, the first impurity 5 is added to the NMOS region 2 by an ion implantation method using the gate electrode 62, the first film 42, the element isolation region 17, and the resist film 81 as a mask.
Introduce 2. At the same time, the first impurity 52 is introduced into the emitter formation planned region 19 exposed in the opening 43. As the first impurity 52, for example, phosphorus is used. The dose amount at this time is set so that the surface concentration when all the steps are completed becomes the surface concentration of the LDD layer of the NMOS transistor (for example, 5 × 10 ¹⁸ cm ⁻³ ). This surface concentration is the base layer (21) to be formed later.
Slightly higher than the surface concentration of 10 ¹⁸ cm ^-3 . After removing the resist film 81, P-type impurities are selectively introduced into the PMOS region (not shown) at a low concentration.

Then, as shown in FIG. 4 (4), the inner wall of the opening 43, the surface of the first film 42, the gate electrode 62 and the gate electrode 62 are formed by the CVD method, for example.
The second film 44 is formed so as to cover the gate electrode (not shown) of the MOS transistor. The second film 44 is made of, for example, a silicon oxide film and has a film thickness of, for example, 300 nm.

Then, as shown in FIG. 5 (5), anisotropic etching is performed to etch back the entire surface of the second film 44. Then, the portion of the second film 44 shown by the chain double-dashed line in the drawing is removed, and the side wall 63 is formed by the second film (44) left on both side walls of the gate electrode 62. A side wall (not shown) is formed by the second film (44) left on both side walls of the gate electrode of the PMOS transistor. At the same time, the side wall 45 is formed by the second film (44) left on the inner wall of the opening 43.
To form.

After that, the PMOS region (not shown) is covered.
In this state, a mask (not shown) is formed using, for example, a resist
It Then, for example, by ion implantation, the side
In the emitter formation planned region 19 inside the wall 45,
The second impurity 53 of the same conductivity type as the first impurity 52 is
The doping concentration is higher than the doping concentration of the pure substance 52 in a self-aligned manner.
To rape. At the same time, the gate electrode 62 and the side
Of the NMOS region 2 with the mask 63 as a mask.
The second impurity 53 is introduced into the rule layer 13. The second impurity
53 is arsenic, for example, and its dose is
So 10 ¹⁶cm^-2Set to. For this reason, complete the entire process
The high-concentration diffusion layer (22) and saw, which will be described later.
The surface concentration of the drain (73,74) is about 10.²⁰
cm^-3become.

In the above ion implantation method, the sidewall 4
The doping of the second impurity 53 is blocked by 5, 63. Therefore, the epitaxial layer 13 below the sidewalls 45 and 63 is not doped with the second impurity 53. Therefore, the first impurity 5 is formed in the epitaxial layer 13 and the P well layer 91 below the sidewall 45.
Only 2 is in the doped state. During the ion implantation, the second impurity 5 is also added to the upper layer of the plug diffusion layer 25.
3 is introduced. Then, after removing the mask (not shown), P-type impurities are selectively introduced into the PMOS region (not shown) at a high concentration.

Then, the fifth step shown in FIG. 5 (6) is performed. In this step, the activation annealing process is performed to
The impurities (52) are diffused more widely in the surface direction of the epitaxial layer 13 than the second impurities (53). At the same time, the second impurity (53) is diffused deeper than the first impurity (52) in the depth direction of the epitaxial layer 13. As a result, a low concentration diffusion layer 23 formed by diffusing the first impurity (52) and a high concentration diffusion layer 22 formed by diffusing the second impurity (53) are formed in the upper layer portion of the epitaxial layer 13 in the bipolar region 3. To be done. In this way, the high concentration diffusion layer 2
An emitter layer 24 composed of 2 and a low concentration diffusion layer 23 is formed. At the same time, impurities forming the base layer (not shown)
Are diffused to form the base layer 21.

At the same time, the first impurity (52) is diffused on both sides of the gate electrode 62 in the NMOS region 2 to form LDD layers 71 and 72 made of low concentration diffusion layers. At the same time, the second impurity (53) is diffused to form the source / drain 73, 74 made of the high concentration diffusion layer via the LDD layers 71, 72.

When forming the high-concentration diffusion layer 22, a collector extraction diffusion layer 26 made of an N ⁺ type diffusion layer is formed on the plug diffusion layer 25. Furthermore, PMO
An LDD layer (not shown) and a source / drain (not shown) of the PMOS transistor are formed in the S region.

Although not shown, the first film (42) is thereafter removed by etching. Then, an interlayer insulating film and each electrode are formed by a normal process.

In the above Bi-CMOS manufacturing method, the first method is used.
An ion implantation mask for introducing the impurities 52 is used as NMO.
The gate electrodes 62 of the S transistor and the PMOS transistor are simultaneously formed with the first film 42 forming the gate electrodes 62 (not shown). Therefore, changing the mask does not increase the process load. In addition, the low concentration diffusion layer 2 of the emitter 24
The formation process of the side wall 45 for leaving 3 is NM
The process of forming the LDD layers 71 and 72 of the OS transistor can be applied as it is. Therefore, since the number of steps is not increased as compared with the conventional BiCMOS manufacturing method, the productivity is not reduced as compared with the conventional process.

[0055]

As described above, according to the present invention as set forth in claim 1, the low-concentration diffusion layer having a junction shallower than the high-concentration diffusion layer is formed on the side periphery of the high-concentration diffusion layer in the base layer. Since it is provided, the low-concentration diffusion layer of the emitter layer and the base layer are bonded in the vicinity of the surface of the semiconductor substrate, and the impurity concentration at the bonding portion changes gently. Therefore, the concentration of the electric field on the junction can be alleviated, so that the junction breakdown voltage can be improved. In addition, the occurrence of leak current due to the tunnel effect can be reduced. Furthermore, since the difference in the junction concentration between the emitter layer and the base layer near the surface of the substrate becomes small, it becomes difficult to induce crystal defects at the junction.
Therefore, the transistor characteristics are not deteriorated due to the generation of crystal defects, and the generation of leakage current due to crystal defects can be reduced. Therefore, the transistor characteristics can be improved.

According to the second aspect of the present invention, after the opening is formed in the first film formed on the semiconductor substrate in the emitter formation planned region in the base formation planned region, the emitter is formed from the opening. Since the first impurity is introduced into the formation planned region, the emitter layer joined to the base layer near the surface can be a low concentration diffusion layer in which the first impurity is diffused. In addition, since the sidewall is formed on the inner wall of the opening and the second impurity is introduced at a higher concentration than the first impurity into the emitter formation planned region exposed inside the sidewall, the second impurity is formed below the sidewall. Can leave a region into which only the first impurity is introduced. Therefore, it is possible to form a low-concentration diffusion layer formed by diffusing the first impurity on the side periphery of the high-concentration diffusion layer formed by diffusing the second impurity near the surface in a junction state shallower than the high-concentration diffusion layer. It will be possible. As a result, the change in impurity concentration at the junction between the emitter layer and the base layer can be made gentle.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of an embodiment of the present invention.

FIG. 2 is a manufacturing process diagram (1) of the embodiment of the present invention.

FIG. 3 is a manufacturing process diagram (2) of the embodiment of the present invention.

FIG. 4 is an explanatory diagram of an application example to Bi-CMOS (No. 1).
Is.

FIG. 5 is an explanatory diagram of an application example to Bi-CMOS (Part 2).
Is.

FIG. 6 is a schematic cross-sectional view of a conventional emitter structure.

FIG. 7 is an impurity concentration distribution diagram of an emitter layer and a base layer.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Bipolar transistor 11 Semiconductor substrate 15 Base layer formation planned region 19 Emitter formation planned region 21 Base layer 22 High concentration diffusion layer 23 Low concentration diffusion layer 24 Emitter layer 42 First film 43 Opening 45 Sidewall 52 First impurity 53 2 impurities

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical indication H01L 27/06

Claims (2)

[Claims] 1. A bipolar transistor having a high-concentration diffusion layer formed in a part of an upper layer of a base layer, and a junction shallower than the high-concentration diffusion layer, the side periphery of the high-concentration diffusion layer in the base layer. An emitter structure for a bipolar transistor, characterized in that it comprises a provided low-concentration diffusion layer. 2. A method of manufacturing an emitter of a bipolar transistor, which comprises forming a first film on a semiconductor substrate and then forming the first film on an emitter formation region in a base layer formation region of the semiconductor substrate. A first step of forming an opening in the film; a second step of introducing a first impurity forming a low-concentration diffusion layer into an emitter formation planned region exposed in the opening; and an inner wall of the opening. A third step of forming a sidewall; and a step of introducing a second impurity of the same conductivity type as the first impurity into the emitter formation region exposed inside the sidewall at a concentration higher than a doping concentration of the first impurity. Four
And diffusing the first impurity more widely than the second impurity in the surface direction of the semiconductor substrate, and diffusing the second impurity deeper than the first impurity in the depth direction of the semiconductor substrate. A bipolar transistor comprising a fifth step of forming a low concentration diffusion layer formed by diffusing the first impurity and a high concentration diffusion layer formed by diffusing the second impurity in an upper layer portion of a semiconductor substrate. Of manufacturing the emitter of.