JPH0883235A - CPU system - Google Patents

Abstract

(57) [Summary] (Modified) [Purpose] To provide a CPU system that can efficiently access multiple I / O units. [Configuration] A CPU unit 1 and a plurality of I / O units 11, 12, 21, and 22 are a common bus 100 of a system.
And a plurality of I / O addresses in the I / O address space are grouped by a common group address, and each I / O unit matches the group address sent from the CPU unit and The I / O access is activated when both the address and the common address match are detected.
Alternatively, the address bit information of m + n bits forming the I / O address space is made to correspond to each I / O unit consisting of a matrix array of m rows and n columns, and each I / O unit is sent to the i row ( Both the i = 1 to m) and the jth column (j = 1 to n) address bit information are active to activate the I / O access.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CPU system,
More specifically, a CPU unit and a plurality of I / O units are connected to each other via a common bus of the system, and the CPU unit uses the I / O address information to access the I / O unit. Regarding the system.

Today, this type of CPU system has become a basic structure of general computer systems and computer application equipment. In recent years, with the increase in size and complexity of CPU systems, I
The number of / O units tends to increase more and more. Since each of these I / O units has its own I / O address, it is desirable to provide a CPU system that can efficiently access each I / O unit.

[0003]

2. Description of the Related Art FIG. 5 is a block diagram of a conventional CPU system. In the figure, reference numeral 1 is a CPU unit for performing main control of the system, and 2 to 5 are, for example, a plurality of I / O units (printed board units) in a rack device. Shelves (1) to (4) for accommodating 11 to 14, 21 to 24, 31 to 3
4, 41 to 44 are I / O units respectively, and 100 is a system common bus.

The common bus 100 is, for example, a data bus "D _{7 to} D ₀ " consisting of 8 bits for transferring data, commands, status information, etc., an I / O address, and other address information. an address bus of 8-bit "a ₇ to a _0", is made a parallel bus control and a bus (several bits) for transferring read / write control signal data, and other control signals.

Each I / O unit is configured as a device interface for connecting to, for example, a plurality of terminal devices (not shown). Or in the data transmission device,
It is configured as a channel unit responsible for each channel communication. Alternatively, a device monitoring device or the like is configured as a monitoring interface for collecting status information and the like from a plurality of connection devices (not shown). CP
The U unit 1 performs the control suitable for each case.

In the conventional CPU system, the CPU unit 1 individually accesses each I / O unit using an I / O address unique to each I / O unit. That is, when the bit "A ₃ to A _0" of the address bus allocated to I / O address space, using the "0000" I / O address = 0 for example I / O unit 11, I / O I / O address = 5 for unit 22
“0101” is used, and I / O address = 15 “1111” is used for the I / O unit 44 to individually access each.

[0007]

However, in the conventional method of individually accessing each I / O unit,
When the same data is set in a plurality of I / O units, the setting takes time and is not efficient. Further, even when status data is collected from a plurality of I / O units all at once, the collection takes time and real-time data collection cannot be performed.

An object of the present invention is to provide a CPU system capable of efficiently accessing a plurality of I / O units.

[0009]

The above-mentioned problems can be solved by the structure shown in FIG. That is, in the CPU system of the present invention (1), the CPU unit and the plurality of I / O units are connected to each other via a common bus of the system,
In the CPU system in which the U unit uses the I / O address information to access the I / O unit,
A plurality of I / O addresses in the O address space are grouped by a common group address, and each I / O unit uniquely identifies itself in the group address detection unit that detects the match of the group address to which it belongs. Unit address detector for detecting a match of unit addresses and a common address detector for detecting a match of a predetermined common address, and each I / O unit matches the group address sent from the CPU unit and the unit address. Alternatively, the I / O access is activated when the coincidence of the common address is detected.

The above problem can be solved by the configuration of FIG. That is, the CPU system of the present invention (2) is a CPU
In a CPU system in which a unit and a plurality of I / O units are connected to each other via a common bus of the system, and the CPU unit uses the I / O address information to access the I / O unit, The address bit information of m + n bits forming the I / O address space is made to correspond to each I / O unit composed of a matrix array of m rows and n columns, and each I / O unit is sent to the i row (i = 1 .About.m) and the address bit information of the jth column (j = 1 to n) are both active, so that the I / O access is activated.

[0011]

FIG. 1 shows a specific example of the present invention (1), and its operation will be described. However, the present invention (1) is not limited to FIG. In the figure, the CPU unit 1 and a plurality of I / O units 11, 12, 21, 22 are connected to each other via a common bus 100 of the system, and the CPU unit 1 uses I / O addresses to Access the I / O unit.

In this case, for example, the upper 3 bits "A ₆ -A ₄ " of the I / O address space "A ₆ -A ₀ " are the group address GA and the lower 3 bits "A ₂ -A ₀ " are the unit. Address UA and, for example, the middle 1 bit "A
₃ ”is assigned to the common address CA. In each I / O unit, the group address detector 11 ₂ detects the match of the group address GA to which it belongs. The unit address detection unit 11 ₃ detects the unit address UA unique to itself within the group. Common address detection unit 11 ₄ performs coincidence detection of a predetermined common address CA. Then, each I / O unit is activated for I / O access when both the match of the group address GA sent from the CPU unit 1 and the match of the unit address UA or the common address CA are detected. Hereinafter, this will be described in detail.

For example, the CPU unit 1 has GA = 0, U
When I / O access is performed with A = 0 and CA = 0, only the coincidence detection signals G ₀ and U ₀ of the I / O unit 11 become active in the system, and in this case, the I / O unit 11 accesses independently. To be done. When the CPU unit 1 makes an I / O access with GA = 0, UA = 1, CA = 0, only the coincidence detection signals G ₀ and U ₁ of the I / O unit 12 become active in the system. In this case, I
The / O unit 12 is accessed independently. Other I / O
The same applies to the units 21 and 22.

Next, the CPU unit 1 has GA = 0, UA
= × (however, x means that anything is acceptable), when I / O access is performed with CA = 1, the coincidence detection signals G ₀ and C ₁ of the I / O units 11 and 12 are both active in the system, In this case, all I / O units 11 and 12 of group (0) are simultaneously accessed. If the CPU unit 1 makes an I / O access with GA = 1, UA = ×, CA = 1, the system will have I / O units 21, 2
Both the match detection signals G ₁ and C _{1 of} 2 become active, and in this case, all the I / O units 2 of the group (1)
1 and 22 are simultaneously accessed.

Therefore, according to the present invention (1), the same data can be simultaneously set in a plurality of I / O units in the same group, and the statuses of the plurality of I / O units in the same group can be simultaneously set. Data can also be collected, and multiple I / O units can be efficiently accessed. FIG. 2 shows a specific example of the present invention (2), and its operation will be described. However, the present invention (2) is not limited to FIG.

In the figure, a CPU unit 1 and a plurality of I / O units 11, 12, 21, 22 are connected to each other via a system common bus 100, and a CPU
The unit 1 uses the I / O address information to access the I / O unit. In this case, m + n bits forming the I / O address space (however, in this example, m = n
2, n = 2) of the row address bit information LNA
“A ₃ , A ₂ ” and column address bit information CLA
“A ₁ , A ₀ ” are made to correspond to the respective I / O units 11, 12, 21, 22 each having a matrix array of m rows and n columns. Each I / O unit is assigned an I / O access because the address bit information of the i-th row (i = 1 to m) and the j-th column (j = 1 to n) sent from the CPU unit 1 is active. Energized. Hereinafter, this will be described in detail.

For example, if the CPU unit 1 is "A ₃ ,
A ₂ ”=“ 0,1 ”,“ A ₁ , A ₀ ”=“ 0,1 ”and I
When I / O access is made, the system displays I in the first row and first column.
/ Only match detection signal I ₁₁ of O unit 11 is active, in this case the I / O unit 11 is accessed by itself. In addition, the CPU unit 1 is "A ₃ , A ₂ " =
When I / O access is made with “0,1”, “A ₁ , A ₀ ” = “1,0”, only the coincidence detection signal I ₁₂ of the I / O unit 12 in the first row and second column is active in the system. Next to
In this case, the I / O unit 12 is independently accessed. The same applies to the other I / O units 21 and 22.

Next, the CPU unit 1 is set to "A₃, A₂"
= "0, 1", "A₁, A₀= “1,1” means I / O
Access, the system will use the I / O unit of the first row.
Matching detection signals I of₁₁, I₁₂Together with
In this case, the I / O units 11 and 12 are the same.
Sometimes accessed. In addition, the CPU unit 1₃,
A₂= “1,1”, “A₁, A₀= “0,1” and I
When I / O access is made, I / O of the first column in the system
Each match detection signal I of the units 11 and 21₁₁, I _{twenty one}Together
Active, in this case I / O units 11,2
1 are accessed at the same time.

Further, the CPU unit 1 is "A ₃ , A ₂ "
= "1,1", "A _1, A _0" = multiplied by I / O access "1,1", the system all the I / O unit 1
1, ₁₂ , 21, and 22 match detection signals I ₁₁ , I ₁₂ , and I
₂₁ and I ₂₂ are both active, and in this case all I / O
The units 11, 12, 21, 22 are accessed simultaneously. In addition to this, the address bit information "A ₃ , A ₂ ,
Various combinations of “A ₁ , A ₀ ” allow simultaneous access of various combinations of I / O units.

Therefore, according to the present invention (2), it is possible to set the same data to a plurality of I / O units of arbitrary rows / columns at the same time, or to simultaneously set the same data from the plurality of I / O units. It is also possible to collect status data and efficiently access a plurality of I / O units.
Further, in the above-mentioned present invention (1) or (2), preferably, each I / O unit transmits the status bit information to be read by the I / O access of the CPU unit 1 to the same or mutually on the common bus 100 of the system. It is configured to output to different bit information lines.

When the CPU unit 1 makes a read access of status bit information to a plurality of I / O units, if each I / O unit sends each status bit information to the same bit information line on the common bus 100. If it is configured to output to the
Since it is 0 (non-active), the CPU unit 1 can know that the status of all I / O units that have made the access is 0 (non-active) by one access. Further, since the signal on the bit information line = 1 (active), it is possible to know that the status of any one or more I / O units is 1 (active) by one access. This means that multiple I / O
It is extremely useful for quickly monitoring the presence / absence of a specific error status common to the units.

Further, when each I / O unit is configured to output each status bit information to different bit information lines on the common bus 100, according to 1/0 of the signal on each bit information line. The CPU unit 1 can know which I / O unit the status bit is 1 (active) by one access. This means that the status bit for each I / O unit
It is extremely effective for quickly monitoring nothing.

[0023]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. The same reference numerals denote the same or corresponding parts throughout the drawings. FIG. 3 shows C of the first embodiment.
In the block diagram of the PU system, in the figure, 1 is a CPU unit that performs main control of the system, and 2-9 are groups (groups) each of which is a shelf or a stand-alone type constituent device (not shown). 0) ~
(7) 11 to 17 to 81 to 87 are I / O units belonging to groups (0) to (7), respectively, and 100 is a system common bus.

The common bus 100 is, for example, an 8-bit data bus "D _{7 to} D ₀ " for transferring data, commands, status information, etc., and an I / O address and other address information. an address bus of 8-bit "a ₇ to a _0", consists a parallel bus and a control bus (several bits) for transferring data read / write control signal RE / WP, the other control signals such as There is.

In the I / O unit 11, 11
₁Is a data input / output unit (DI
O), D is a 3-state driver circuit, R is a receiver circuit
, A is AND gate circuit, WR is CPU unit 1
Temporarily stores various data and command information sent from
Write register, RR to send to CPU unit 1
A read register for temporarily storing various data, 11₂Is
Group to which it belongs by AND gate circuit (A) etc.
Decoder configured to perform address GA match detection
(Group address detection unit 11 in FIG.₂Equivalent to), 11
₃Belongs to the same by AND gate circuit (A) etc.
Unit address U unique to itself within the group
A decoder configured to perform the match detection of A (the unit of FIG.
Knit address detection unit 11₃Equivalent to), 11_FourIs also
Predetermined common address C by AND gate circuit (A), etc.
A decoder configured to perform A match detection (see FIG. 1).
Communication address detector 11_FourEquivalent to), O is the OR gate times
, A is an AND gate circuit, 11 _FiveIs 3 states (or
It is a driver circuit (of open collector type) (D)
It Regarding the other I / O units 12 to 87,
I / O unit 1 except for the part that detects the I / O address
The same configuration as that of No. 1 is provided.

Each such I / O unit is configured as a device interface for connecting to a plurality of terminal devices (not shown), for example. Alternatively, in a data transmission device or the like, it is configured as a channel unit responsible for each channel communication. Alternatively, a device monitoring device or the like is configured as a monitoring interface for collecting status information and the like from a plurality of connection devices (not shown). The CPU unit 1 performs control suitable for each case.

In the CPU system of the first embodiment, I / O
A plurality of I / O addresses coded on the address space “A _{6 to} A ₀ ” are grouped into a group (0) to a group (7) by a common group address GA of the upper 3 bits “A _{6 to} A ₄ ”. It is divided. The lower 3 bits "A
_{2 to} A ₀ ”represent unit address UA = 0 to 6. The unit address UA = 7 is the common address CA =
Functions as 7.

With this configuration, the CPU unit 1 is GA =
When I / O access is performed with 0 and UA = 0, only the coincidence detection signals G ₀ and U _{0 of} the I / O unit 11 are active in the system, and the I / O unit 11 is accessed alone. In this case, when the CPU unit 1 makes a normal data write access, the write data WD “D _{7 to} D ₀ ” from the CPU unit 1 is written by the write pulse signal WP generated at the same time. Written to register WR. Further, when the CPU unit 1 makes a normal data read access, the read enable signal RE simultaneously generated causes the read data RD of the read register RR to be read.
“D _{7 to} D ₀ ” are taken into the CPU unit 1 via the driver circuit D and the data bus. When the CPU unit 1 makes a read access to the status data, the status bit information S ₀₀ of the I / O unit 11 is transferred to the data via the driver circuit D 11 ₅ by the read enable signal SE of the status data which is generated at the same time. It is output to bit D ₀ of the bus.

The CPU unit 1 has GA = 0, UA =
When I / O access is made at _6, only the coincidence detection signals G ₀ and U _{6 of} the I / O unit 17 become active in the system, and the I / O unit 17 is independently accessed. In this case, CPU unit 1 can
The operation when accessing a book is the same as above.
However, when the CPU unit 1 makes a read access to the status data, the I / O unit 1 is read by the status data read enable signal SE that occurs at the same time.
The status bit information S ₀₆ of 7 is the driver circuit D 17 ₅
To the bit D ₆ of the data bus.

Next, the CPU unit 1 sets GA = 0, UA
= 7 when I / O access is made, the system I / O
The coincidence detection signals G ₀ and C _{7 of the} units 11 to 17 are activated simultaneously (simultaneously), and all the I / O signals of the group (0) are
The O units 11 to 17 are simultaneously accessed. In this case, when the CPU unit 1 makes a data write access, the common write data WD “D” from the CPU unit 1 is generated by the write pulse signal WP simultaneously generated in the I / O units 11 to 17. _7- D ₀ "is I / O unit 1
The data are simultaneously written in the write registers WR of 1 to 17.
Therefore, when common data is set for a plurality of I / O units, extremely efficient setting can be performed.

Further, the CPU unit 1 has status data
Read access to the I / O unit 11
Status data read enable that occurs at
Bull signal SE causes each switch of I / O units 11 to 17 to
Status bit information S₀₀~ S ₀₆Is each driver circuit D
11_Five~ 17_FiveBit D on the data bus via₀~ D
₆Are output all at once. Therefore, the space for each I / O unit
Extremely effective even when collecting status information at once
You can collect data at a good rate.

Although the unit address UA = 7 functions as the common address CA = 7 in the first embodiment, it is not limited to this. Alternatively, the address bit “A ₃ ” may be used as the common address CA as described with reference to FIG. FIG. 4 shows the CPU of the second embodiment.
In the block diagram of the system, in the figure, 1 is a CPU unit 11-14, 21-24, which performs the main control of the system.
31 to 34, 41 to 44 are I / O units arranged in a matrix of 4 rows and 4 columns, and 100 is a system common bus.

[0033] In the I / O unit 11, 11 ₁ data input-output unit (DIO), the driver circuit 11 ₅ 3 states (or open collector type) (D), 11
_Reference numeral ₆ is an AND gate circuit (A) for detecting its own I / O address. The other I / O units 12 to 44 have the same configuration as that of the I / O unit 11 except for the portion that detects its own I / O address. Although the illustration is not accurate, it is sufficient to understand the concept.

In the CPU system of the second embodiment, for example, the upper 4 bits "A" of the I / O address space "A ₇ -A ₀ ".
_{7 to} A ₄ "is assigned to the row address bit information LNA and the lower 4 bits" A _{3 to} A ₀ "is assigned to the column address bit information CLA, respectively, and these are assigned to each I / O unit composed of a matrix array of 4 rows and 4 columns. It corresponds to the I / O address information.

The I / O units may be arranged in a matrix form as long as the I / O address distribution relationship is in a matrix form. With such a configuration, the CPU unit 1 has “A ₇ , A ₆ , A ₅ ,
A ₄ "=" 0, 0, 0, 1 "," _{A 3, A 2, A 1} , A
₀ "= multiplied by I / O access" 0,0,0,1 ", only the match detection signal I ₁₁ of the first row and first column of I / O unit 11 becomes active in the system, I / O unit 11 Is accessed by itself.

In this case, the operation when the CPU unit 1 makes a normal data read / write access is the same as that described in the first embodiment. However, when the CPU unit 1 makes a read access to the status data, the status bit information S ₁₁ of the I / O unit ₁₁ is transferred to the driver circuit D 11 ₅ by the read enable signal SE (not shown) of the status data which is generated at the same time. To the bit D ₀ of the data bus. The same applies when the other I / O units 12 to 44 are individually accessed.

Next, the CPU unit 1 displays "A ₇ , A ₆ ,
"A ₅ , A ₄ " = "0, 0, 0, 1", "A ₃ , A ₂ , A"
_When I / O access is performed with “ ₁ , A ₀ ” = “ ₁ , ₁ , ₁ , ₁ ”, the coincidence detection signals I _{11 to} I ₁₄ of all the I / O units 11 to 14 in the first row become active. , I / O units 11-14 are accessed simultaneously. In this case, when the CPU unit 1 accesses to write data, the same data is stored in the write registers WR of the I / O units 11 to 14 all at once. When the CPU unit 1 makes a read access to the status data, the status bit information S _{11 to} S ₁₄ of the I / O units 11 to ₁₄ is transmitted to the bit D ₀ on the data bus via the respective driver circuits D. is output to the to D _3.

Therefore, the CPU unit 1 can set common data to any of a plurality of I / O units in a possible combination all at once, or can take in each status data bit for each I / O unit at once. Similarly, CP
U unit 1 has "A ₇ , A ₆ , A ₅ , A ₄ " = "1,
1, 1, 1 ”,“ A ₃ , A ₂ , A ₁ , A ₀ ”=“ 0,
When I / O access is made with "0, 0, 1", the match detection signals I ₁₁ , I ₂₁ , I ₃₁ , I ₄₁ of all the I / O units ₁₁ , ₂₁ , ₃₁ , _{41 of} the first column are all active. And I
The / O units 11, 21, 31, 41 are simultaneously accessed.

Further, the CPU unit 1 has a function of "A ₇ , A ₆ ,
“A ₅ , A ₄ ” = “1, 1, 1, 1”, “A ₃ , A ₂ , A
_When I / O access is performed with “ ₁ , A ₀ ” = “ ₁ , ₁ , ₁ , ₁ ”, all the match detection signals I _{11 to} I ₄₄ of all I / O units _{11 to 44} of the system become active, and I /
The O units 11 to 44 are simultaneously accessed. It is particularly efficient to write common data or read status data in this access mode. In addition to the above, each I
Simultaneous access is possible with various combinations of / O units.

In the first embodiment described above, each of the address detection units 11 _{2 to} 11 ₄ is realized by a decoder composed of an AND gate circuit or the like, but the present invention is not limited to this. For example, it may be realized by using a comparator circuit. Further, in each of the above embodiments, the case where the common bus 100 of the system has the address bus has been described, but the present invention is not limited to this. I / O address information can be obtained by any method (for example, by dividing the data bus by time division).
The present invention can be applied even when it is transferred by transmitting O address information).

In each of the above embodiments, the status bit information is output on a different data bus line for each I / O unit, but the present invention is not limited to this. Even if each I / O unit outputs status bit information on a common data bus line, the presence / absence of an error state can be detected quickly. Although a plurality of preferred embodiments of the present invention have been described above, it goes without saying that various changes in configuration and control can be made without departing from the spirit of the present invention.

[0042]

As described above, according to the present invention (1),
Each I / O unit is configured to be activated for I / O access when a match of the group address sent from the CPU unit and a match of the unit address or the common address are both detected. I / O unit of the same setting data at the same time,
The status data can be efficiently fetched from the plurality of I / O units, which greatly contributes to the efficiency and speed of the processing of this type of CPU system.

According to the present invention (2), the address bit information of m + n bits forming the I / O address space is made to correspond to each I / O unit having a matrix array of m rows and n columns, and each I / O unit is The O unit is an i row (i = 1 to m) and a j column (j = 1 to 1) sent from the CPU unit.
Since the I / O access is activated when both the address bit information of n) are active, the same setting data is simultaneously set for a plurality of I / O units in an arbitrary combination. That I
The status data can be efficiently fetched from the / O unit, which greatly contributes to the efficiency and speed of the processing of this type of CPU system.

[Brief description of drawings]

FIG. 1 is a diagram (1) for explaining the principle of the present invention.

FIG. 2 is a diagram (2) explaining the principle of the present invention.

FIG. 3 is a block diagram of a CPU system according to a first embodiment.

FIG. 4 is a block diagram of a CPU system according to a second embodiment.

FIG. 5 is a block diagram of a conventional CPU system.

[Explanation of symbols]

1 CPU unit 11, 12, 21, 22 I / O unit 100 Common bus 11 ₂ Group address detection unit 11 ₃ Unit address detection unit 11 ₄ Common address detection unit

Claims (3)

[Claims] 1. A CPU unit and a plurality of I / O units are mutually connected via a common bus of a system, and the CPU unit uses I / O address information to access the I / O unit. In the CPU system to perform, a plurality of I / O addresses in the I / O address space are grouped by a common group address, and each I / O unit includes a group address detection unit that detects a match of the group address to which the I / O unit belongs. Each I / O unit is provided with a unit address detection unit that detects a unit address that is unique to itself within the group and a common address detection unit that detects a match of a predetermined common address. I / O when both address match and unit address or common address match are detected CPU, characterized in that it is configured to bias the access
system. 2. A CPU unit and a plurality of I / O units are connected to each other via a common bus of the system, and the CPU unit uses I / O address information to access the I / O unit. In the CPU system to perform, I / O address space is composed of m / n bits of address bit information for each I / O in a matrix array of m rows and n columns.
Corresponding to O unit, each I / O unit is C
The I / O access is activated when the address bit information of the i-th row (i = 1 to m) and the j-th column (j = 1 to n) sent from the PU unit are both active. A CPU system characterized by the above. 3. Each I / O unit is an I / O unit of a CPU unit.
3. The CPU system according to claim 1, wherein each status bit information to be read by / O access is output to the same or different bit information line on the common bus of the system.