JPH088323B2 - Pushback method for chip carrier substrates with multiple surfaces - Google Patents
Pushback method for chip carrier substrates with multiple surfacesInfo
- Publication number
- JPH088323B2 JPH088323B2 JP2224613A JP22461390A JPH088323B2 JP H088323 B2 JPH088323 B2 JP H088323B2 JP 2224613 A JP2224613 A JP 2224613A JP 22461390 A JP22461390 A JP 22461390A JP H088323 B2 JPH088323 B2 JP H088323B2
- Authority
- JP
- Japan
- Prior art keywords
- chip carrier
- substrate
- chip
- multiple surfaces
- pushback
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0097—Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing of the conductive pattern
- H05K3/241—Reinforcing of the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、複数のチップキャリアを保持し、該チップ
キャリアにIC素子を搭載、更にワイヤボンド等の一連の
製造工程を、複数のチップキャリアについて同時に行え
る多面付チップキャリア基板のプッシュバック工法に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention holds a plurality of chip carriers, mounts IC elements on the chip carriers, and further performs a series of manufacturing processes such as wire bonding. The present invention relates to a pushback construction method for a chip carrier substrate with multiple surfaces, which can be performed simultaneously.
［従来の技術］ チップキャリアにICを搭載する工法として、チップキ
ャリアをプッシュバック工法により、第２図、第３図に
示される様に、多面付チップキャリア基板１に複数保持
させ、複数のチップキャリアについて併行してICの搭載
を行うものがある。[Prior Art] As a method of mounting an IC on a chip carrier, a plurality of chip carriers are held by a push-back method on a chip carrier substrate 1 with multiple faces as shown in FIGS. 2 and 3. Some carriers carry ICs in parallel.
ここで、前記プッシュバック工法とは、複数のチップ
キャリア２を基板（多面付チップキャリア基板）１より
１度型抜きしたものを、型抜きした箇所に圧入して保持
させ、チップキャリア２が基板圧入された状態のもの
を、後の工程では１枚の基板として製造工程の作業を一
括して行うものである。Here, the push-back method means that a plurality of chip carriers 2 that have been die-cut from a substrate (chip carrier substrate with multiple surfaces) 1 once are press-fitted and held in the die-cut portions so that the chip carrier 2 is a substrate. In the subsequent process, the press-fitted state is used as one substrate to collectively perform the manufacturing process.
第２図、第３図中、３はスルーホール、４はワイヤ接
続用リード、５はIC素子搭載部、６は電解メッキ用リー
ドを示す。In FIGS. 2 and 3, 3 is a through hole, 4 is a wire connecting lead, 5 is an IC element mounting portion, and 6 is an electrolytic plating lead.
チップキャリアに、ICを搭載する工程を略述する。 The process of mounting an IC on a chip carrier will be outlined.
チップキャリアにICを装填、ワイヤボンド、樹
脂封止、電気的試験の順に行われる。The IC is loaded into the chip carrier, wire bonding, resin encapsulation, and electrical testing are performed in that order.
前記ワイヤボンドには金ワイヤが使用されており、確
実な接合を行うため、多面付チップキャリア基板の前記
ワイヤ接続用リード４には電解金メッキが施される。こ
の為、該ワイヤ接続用リード４は、前記電解メッキ用リ
ード６によって全て接続している状態となっている。従
って、チップキャリアが多面付チップキャリア基板に保
持されている状態では、チップキャリアは電気的に単体
でないので、多面付チップキャリア基板よりチップキャ
リアを外し、１個ずつ電気的試験を行っていた。Gold wires are used for the wire bonds, and in order to ensure reliable bonding, the wire connection leads 4 of the chip carrier substrate with multiple surfaces are subjected to electrolytic gold plating. Therefore, the wire connecting leads 4 are all connected by the electrolytic plating leads 6. Therefore, in the state where the chip carrier is held on the chip carrier substrate with multiple surfaces, the chip carrier is not an electric single body, so the chip carriers were removed from the chip carrier substrate with multiple surfaces and an electrical test was performed one by one.
［発明が解決しようとする課題］ 上記した様に、電気的試験は多面付チップキャリア基
板よりチップキャリアを外し、１個ずつ行わなければな
らないので、チップキャリアの多面付一括処理工程は、
前記〜までしか行えず、生産効率は充分には向上し
なかった。[Problems to be Solved by the Invention] As described above, since the electrical test must be performed one by one by removing the chip carriers from the multi-sided chip carrier substrate, the multi-sided batch processing step of the chip carrier is
Only the above-mentioned steps could be performed, and the production efficiency was not sufficiently improved.
本発明は、斯かる実情を鑑み、電気的試験迄多面付一
括処理を行える様にしようとするものである。In view of such a situation, the present invention aims to enable multi-sided batch processing up to an electrical test.
［課題を解決する為の手段］ 本発明は、複数のチップキャリアを基板より型抜きし
た後、基板にプッシュバックし、複数のチップキャリア
について同時に集積回路の製造を行うプッシュバック工
法に於いて、プッシュバック工程と同時、前後のいずれ
かで電界メッキ用リードとワイヤ接続用リードとの交点
を含む分断用の孔を穿設することを特徴とするものであ
る。[Means for Solving the Problems] The present invention provides a pushback method in which a plurality of chip carriers are die-cut from a substrate and then pushed back to the substrate to simultaneously manufacture integrated circuits for the plurality of chip carriers, At the same time as or before or after the pushback process, a dividing hole including an intersection of the electric field plating lead and the wire connecting lead is formed.
［作用］ 孔の穿設により、電解メッキ用リードと前記ワイヤ接
続用リードとが分断され、チップキャリアがプッシュバ
ックされた状態で、チップキャリアの電気的独立が得ら
れ、IC素子搭載後の電気的試験を多面付チップキャリア
基板にチップキャリアを保持させたままで行うことがで
きる。[Operation] By forming the hole, the electroplating lead and the wire connecting lead are separated from each other, and the chip carrier is pushed back, so that the chip carrier can be electrically isolated. The physical test can be performed with the chip carrier held on the chip carrier substrate with multiple faces.
［実 施 例］ 以下、図面を参照しつつ本発明の一実施例を説明す
る。[Example] An example of the present invention will be described below with reference to the drawings.
尚、第１図中、第２図、第３図中で示したものと同一
のものには同符号で示してある。In FIG. 1, the same parts as those shown in FIGS. 2 and 3 are designated by the same reference numerals.
多面付チップキャリア基板１は、多数列、多数行のチ
ップキャリアが面付けされるが、第１図では多面付一括
処理の便宜上、２列に切断してある。この切断時に、切
断線と平行に設けられた電解メッキ用リードは切除して
ある。The chip carrier substrate 1 with multiple surfaces is provided with multiple columns and multiple rows of chip carriers, but in FIG. 1 it is cut into two columns for convenience of batch processing with multiple surfaces. At the time of this cutting, the electrolytic plating lead provided parallel to the cutting line is cut off.
多面付チップキャリア基板１の製作過程、具体的には
前記電解メッキ用リード６のメッキ工程後、前記チップ
キャリア２をプッシュバックする工程と同時に、或は前
後して前記電解メッキ用リード６と前記ワイヤ接続用リ
ード４との交点を含む長孔７を穿設する。該長孔７の穿
設により、全てのワイヤ接続用リード４は分断され、前
記チップキャリア２は電気的に独立したものとなる。After the step of manufacturing the chip carrier substrate 1 with multiple surfaces, specifically, the step of plating the leads 6 for electroplating, the step of pushing back the chip carrier 2 is performed simultaneously with, or before or after, the leads 6 for electroplating. A long hole 7 including an intersection with the wire connecting lead 4 is formed. By forming the elongated hole 7, all the wire connecting leads 4 are divided, and the chip carrier 2 becomes electrically independent.
而して、IC素子搭載後の電気的試験は、前記チップキ
ャリア２を前記多面付チップキャリア基板１に保持させ
たままの状態で一括して行うことができる。Thus, the electrical test after mounting the IC element can be collectively performed while the chip carrier 2 is held on the multi-faceted chip carrier substrate 1.
尚、チップキャリア２の周囲に長孔を穿設したこと
で、チップキャリア２を多面付チップキャリア基板１に
嵌戻す際の歪みが前記長孔で吸収される。従って、チッ
プキャリア２を多面付チップキャリア基板１が保持した
状態での、該多面付チップキャリア基板１の反りの発生
が防止され、又後の加熱工程での反りの発生を防止する
ことができ、処理工程中での反りの修正が不要となり作
業能率が向上すると共に、処理工程の精度、信頼性が向
上する。By forming a long hole around the chip carrier 2, the long hole absorbs the strain when the chip carrier 2 is fitted back to the chip carrier substrate 1 with multiple faces. Therefore, it is possible to prevent the occurrence of warpage of the chip carrier substrate 1 with multiple surfaces while the chip carrier 2 is held by the chip carrier substrate 1 with multiple surfaces, and it is possible to prevent the occurrence of warpage in the subsequent heating step. As a result, it is not necessary to correct the warp during the processing process, which improves the work efficiency and improves the accuracy and reliability of the processing process.
尚、上記実施例に於いては、前記電解メッキ用リード
と前記ワイヤ接続用リードとの交点に長孔を穿設した
が、個々の交点に丸孔を穿設しても良いことは勿論であ
る。In the above-mentioned embodiment, the elongated hole is formed at the intersection of the electrolytic plating lead and the wire connecting lead, but it goes without saying that a round hole may be formed at each intersection. is there.
［発明の効果］ 以上述べた如く本発明によれば、チップキャリアを多
面付けした状態で、IC素子の搭載から電気的試験迄一括
して行うことができると共に、チップキャリア保持状態
での基板の反りを防止することができる。[Effects of the Invention] As described above, according to the present invention, it is possible to collectively carry out from the mounting of the IC element to the electrical test in a state in which the chip carriers are mounted on multiple sides, and the substrate in the chip carrier holding state Warp can be prevented.
第１図は本発明の一実施例を示す説明図、第２図は従来
例の説明図、第３図はチップキャリア部分の拡大図であ
る。 １は多面付チップキャリア基板、２はチップキャリア、
３はスルーホール、４はワイヤ接続用リード、５はIC搭
載部、６は電解メッキ用リード、７は長孔を示す。FIG. 1 is an explanatory view showing an embodiment of the present invention, FIG. 2 is an explanatory view of a conventional example, and FIG. 3 is an enlarged view of a chip carrier portion. 1 is a multi-sided chip carrier substrate, 2 is a chip carrier,
Reference numeral 3 is a through hole, 4 is a wire connecting lead, 5 is an IC mounting portion, 6 is an electrolytic plating lead, and 7 is a long hole.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭58−86748（ＪＰ，Ａ) 特開 平２−82594（ＪＰ，Ａ) 特開 平３−60091（ＪＰ，Ａ) 特開 平４−96290（ＪＰ，Ａ) 実公 平３−51987（ＪＰ，Ｙ２) ─────────────────────────────────────────────────── ─── Continuation of the front page (56) Reference JP-A-58-86748 (JP, A) JP-A-2-82594 (JP, A) JP-A-3-60091 (JP, A) JP-A-4- 96290 (JP, A) Jikkouhei 3-51987 (JP, Y2)
Claims (1)
た後、基板にプッシュバックし、複数のチップキャリア
について同時に集積回路の製造を行うプッシュバック工
法に於いて、プッシュバック工程と同時、前後のいずれ
かで電界メッキ用リードとワイヤ接続用リードとの交点
を含む分断用の孔を穿設することを特徴とする多面付チ
ップキャリア基板のプッシュバック工法。1. A pushback method in which a plurality of chip carriers are die-cut from a substrate and then pushed back to the substrate to simultaneously manufacture integrated circuits for the plurality of chip carriers, at the same time as the pushback process and before and after the pushback process. A pushback method for a chip carrier substrate with multiple surfaces, characterized in that a dividing hole including an intersection of an electric field plating lead and a wire connecting lead is formed in any one of them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2224613A JPH088323B2 (en) | 1990-08-27 | 1990-08-27 | Pushback method for chip carrier substrates with multiple surfaces |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2224613A JPH088323B2 (en) | 1990-08-27 | 1990-08-27 | Pushback method for chip carrier substrates with multiple surfaces |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04106959A JPH04106959A (en) | 1992-04-08 |
| JPH088323B2 true JPH088323B2 (en) | 1996-01-29 |
Family
ID=16816465
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2224613A Expired - Lifetime JPH088323B2 (en) | 1990-08-27 | 1990-08-27 | Pushback method for chip carrier substrates with multiple surfaces |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH088323B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6177288B1 (en) * | 1998-06-19 | 2001-01-23 | National Semiconductor Corporation | Method of making integrated circuit packages |
| KR20010105732A (en) * | 2000-05-17 | 2001-11-29 | 이중구 | Metal Frame Assembly for IC card and method for manufacturing the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0282594A (en) * | 1988-09-19 | 1990-03-23 | Nec Corp | Manufacture of hybrid integrated circuit device |
-
1990
- 1990-08-27 JP JP2224613A patent/JPH088323B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04106959A (en) | 1992-04-08 |
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