JPH0883242A - Arbiter circuit - Google Patents

Abstract

PURPOSE: To provide an arbiter circuit which adjusts a conflict 4 between >=2 request signals with a smaller circuit scale by constituting a circuit which adjust a conflict among plural input signals without using a delay circuit. CONSTITUTION: This circuit is provided with a gate means 1, a gate control means 2, and a gate fixing means 3. The gate means 1 consists of plural gate elements which are supplied with plural request signals A to D respectively. The gate control means 2 controls the ON and OFF states of the gate elements so that the gate elements turn ON and OFF cyclically. The gate fixing means 3 supplies a gate fixation signal (e) to the gate control means 2 when one of the output signals of the gate elements, i.e., one of acceptance signals (a) to (d) becomes significant to hold the ON and OFF states of the gate elements, and stops supplying the gate fixation signal (e) when none of the output signals of the gate elements is significant.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbiter circuit used in a semiconductor circuit device.

[0002]

2. Description of the Related Art An arbiter circuit is a circuit for adjusting the competition of two or more request signals input synchronously or asynchronously and selecting one of them, and for example, for a semiconductor memory. It is used for adjusting the conflict between the write request, the read request, and the refresh request, and preventing malfunction of the semiconductor memory and data destruction.

An RS flip-flop (hereinafter 3R-RS) having a set input (hereinafter abbreviated as S input) 1 terminal and a reset input (hereinafter abbreviated as R input) 3 terminals used in a conventional arbiter circuit. FIG. 7 shows a flip-flop (abbreviation). In FIG. 7, 101 is a 2-input NOR gate, and 102 is a 4-input NOR gate.

Next, FIG. 6 shows an example in which an arbiter circuit for adjusting the competition of four request signals is constructed by using the above 3R-RS flip-flop. This arbiter circuit
As shown in FIG. 6, 2-input AND gates 111 to 114
, 3R-RS flip-flops 115 to 118, delay elements 119 to 122, a 2-input OR gate 123,
And a 4-input NOR gate 125.

Specifically, the request signal A is supplied to one input terminal of the 2-input AND gate 111, and the output of the 2-input AND gate 111 is supplied to the 3R-RS flip-flop 115.
Connected to the S input of the 3R-RS flip-flop 115
The first latch circuit is configured by supplying the NQ output (inversion of the Q output) of 1 to the R1 input of the 3R-RS flip-flop 115 via the delay element 119.

Similarly for the request signals B to D,
2-input AND gates 112 to 114, 3R-RS flip-flops 116 to 118, and delay elements 120 to 12
2 constitutes a second to a fourth latch circuit. Each of the delay elements 119 to 122 is composed of, for example, a cascade connection circuit of a large number of buffers, or a cascade connection circuit of a large number of buffers and capacitors, and the number thereof is determined according to the magnitude of the delay time. In addition, the delay element 11
The delay times of 9 to 122 are set to be the same.

The Q of the first to fourth latch circuits
The output is supplied to the four input terminals of the 4-input NOR gate 125, and the output of the 2-input NOR gate 125 is supplied to the other input terminals of the 2-input AND gates 111 to 114, respectively. In addition, 3R-R of the fourth latch circuit
The R2 input of the S flip-flop 118 is grounded (fixed at a low level), and the Q output of the third latch circuit 3R-RS of the fourth latch circuit is connected to the 3R- of the third latch circuit.
The R2 input of the RS flip-flop 117 is supplied to the third
Of the 3R-RS flip-flop 117 of the latch circuit of
The output and the Q output of the 3R-RS flip-flop 118 of the fourth latch circuit are supplied to the 2-input OR gate 124, and the output of the 2-input OR gate 124 is supplied to the 3R-RS flip-flop 116 of the second latch circuit. Of the 3R-RS flip-flop 116 of the second latch circuit and the output of the 2-input OR gate 124 are supplied to the 2-input OR gate 123. The output is supplied to the R2 input of the 3R-RS flip-flop 115 of the first latch circuit, and the first to fourth
Latch circuit 3R-RS flip-flops 115-1
A common signal (request-reset signal) is externally supplied to the R3 input of 18.

Finally, the 3R-RS flip-flop 11
The acceptance signals a to d are output from the Q outputs of 5 to 118, respectively. Here, the operation of the arbiter circuit of FIG. 6 will be described. When all the request signals A to D are “L”,
Since all of the reception signals a to d are "L", the output signal of the 4-input NOR gate 125 is "H", and the four 2-input AND gates 111 to 114 are open. In this state, for example, when the request signal A becomes "H", 3R-
The S input is supplied to the RS flip-flop 115, and its Q output, that is, the acceptance signal a becomes "H". Further, since the reception signal a becomes “H”, the output signal of the 4-input NOR gate 125 becomes “L”, and the four 2-input AND gates 111 to 114 are closed to the 3R-RS flip-flop 115. Supply of S input of is stopped, but request signal A
Has changed to "H" because 3R-RS flip-flop 1
15 is held in the set state, and in this state, the 2-input AND gates 112 to 114 are closed even if any of the other request signals B to D subsequently becomes “H”. The S input is not supplied to the 3R-RS flip-flops 116 to 118, and the acceptance signals b to d do not become "H". After that, when the request signal A returns to "L",
Request-Reset signal is temporarily set to "H" and 3R
-Supply R3 input to RS flip-flop 115, and
The R-RS flip-flop 115 is returned to the reset state. Even when the other request signals B to D become “H”, the same operation as described above is performed.

Next, when the request signals A and B simultaneously become "H", the 3R-RS flip-flops 115 and 11 are connected.
Both 6 are set, and their Q outputs, that is, the reception signals a and b become "H". Further, since the reception signals a and b become "H", the output signal of the 4-input NOR gate 125 becomes "L", and the four 2-input AND gates 1
11 to 114 are closed, and 3R-RS flip-flop 1
Although the supply of the set inputs of 15 and 116 is stopped, the fact that the request signal B becomes "H" is held by the 3R-RS flip-flop 116 being in the set state. On the other hand, regarding the 3R-RS flip-flop 115,
Since the Q output of the R-RS flip-flop 116 becomes "H", the Q output is supplied as the R2 input through the 2-input logical sum gate 123, and therefore the reset state is immediately returned. In this circuit, the request signal B has priority over the request signal A. In this state, since the two-input AND gates 113 and 114 are closed even if either of the other request signals C and D subsequently becomes “H”, the S input to the 3R-RS flip-flops 117 and 118 does not occur. It is not supplied and the acceptance signals c and d do not become "H". After that, the request signal B
When it returns to "L", the request-reset signal is temporarily set to "H" and the 3R-RS flip-flop 11
6 is supplied with R3 input, and 3R-RS flip-flop 1
16 is reset. At this time, if the request signal A is still "H", the 3R-RS is processed in the same manner as above.
The flip-flop 115 enters the set state, and the acceptance signal a becomes "H". After that, when the request signal A returns to “L”, the request-reset signal is temporarily set to “H” and the R3 is input to the 3R-RS flip-flop 115.
Supply input and return 3R-RS flip-flop 115 to reset state.

Next, the request signal A becomes "H", and the 3R
-The Q output of the RS flip-flop 115 becomes "H", and the output signal of the 4-input NOR gate 125 becomes "L".
If the request signal B becomes "H" immediately before, the output of the 2-input OR gate 112 becomes a pulsed output.
By setting the delay time of the delay element 120 to be longer than the delay time from the S input to the output being latched in the 3R-RS flip-flop 116, the pulse-shaped input causes the R1 input of the 3R-RS flip-flop 116. Since the NQ output and the NQ output do not become "L" at the same time, the reception signal b does not oscillate due to the pulsed input and operates normally.

When the request signals A to D are combined other than the above, 2
The same operation is performed when two or more simultaneously become "H". In this case, the order of priority is D, C, B, A.

[0012]

However, in the above-mentioned conventional configuration, in order to prevent the oscillation of the circuit, the delay elements 119 to 122 composed of a large number of buffers or a large number of buffers and capacitors are used. The circuit scale becomes large. This invention, compared to the conventional example,
An object of the present invention is to provide an arbiter circuit capable of adjusting the competition of a plurality of request signals with a smaller circuit scale.

[0013]

According to a first aspect of the present invention, there is provided an arbiter circuit in which a plurality of gate elements each of which is supplied with a plurality of input signals and a plurality of gate elements are cyclically conducted one by one. As described above, gate control means for controlling conduction / interruption of a plurality of gate elements, and when any one of the output signals of the plurality of gate elements becomes significant, a gate fixed signal is given to the gate control means to output a plurality of gate elements. And a gate fixing means for holding the conductive / interrupted state and stopping the supply of the gate fixing signal when any output signal of the plurality of gate elements becomes insignificant.

The arbiter circuit according to a second aspect of the present invention is the first aspect.
In the arbiter circuit, the gate means comprises first to fourth two-input AND gates to which the first to fourth input signals are supplied to one input terminal. Further, the gate fixing means outputs a 4-input NOR gate to which the output signals of the first to fourth 2-input AND gates are respectively supplied to the four input terminals, and an output signal of the 4-input NOR gate. An exclusive OR gate supplied to one input terminal,
The output signal of the exclusive OR gate is supplied to the D input terminal, the Q output is supplied to the other input terminal of the exclusive OR gate, and the external clock signal is supplied to the clock terminal. Become.

Further, the gate control means includes a second D-flip-flop whose Q output is supplied to a clock terminal.
And the Q output of the second D flip-flop is supplied to the D input terminal and the first D
A third flip-flop to which the Q output of the flip-flop is supplied to the clock terminal, and a Q output of the third flip-flop to the D input terminal and the first D
The Q output of the flip-flop is supplied to the clock terminal and Q
A fourth flip-flop whose output is supplied to the D input terminal of the first D flip-flop; and second, third and fourth flip-flops.
And a second 3-input AND gate whose NQ output of each D flip-flop is supplied to each of three input terminals and whose output signal is supplied to the other input terminal of the first 2-input AND gate; The Q output of the flip-flop and the NQ outputs of the third and fourth D flip-flops are respectively supplied to the three input terminals, and the output signal is supplied to the other input terminal of the second 2-input AND gate. The 3-input AND gate, the Q outputs of the second and third D flip-flops, and the NQ outputs of the fourth D flip-flops are respectively supplied to the three input terminals, and the output signals are supplied to the third 2-input AND gate. The third 3-input AND gate supplied to the other input terminal and the Q outputs of the second, third, and fourth D flip-flops are supplied to the three input terminals, respectively, and the output signal thereof is the second 2 Consisting of the fourth three-input AND gate which is supplied to the other input terminal of the power AND gate.

[0016]

According to the structure of the present invention, the plurality of gate elements, to which the plurality of input signals are respectively supplied in the gate means, are made conductive one by one, and any one of the plurality of input signals is significant ( For example, when it becomes "H" level, the output signal of the gate element becomes significant at the timing when the gate element to which the input signal is supplied becomes conductive. As a result, a gate fixing signal is supplied from the gate fixing means to the gate control means, and the conduction / interruption state of the plurality of gate elements at that time is held by the gate control means. At this time, even if the other input signal becomes significant, the gate element corresponding to the other signal does not become conductive, so that the output signal of the gate element does not become significant and 2
The output signals of more than one gate element are never significant at the same time.

When the significant input signal becomes insignificant thereafter, the supply of the gate fixing signal is stopped, and the plurality of gate elements are cyclically turned on again one by one by the gate control means. The gate element corresponding to the input signal is turned on to make the output signal of the gate element significant, or next, it waits for any of the plurality of input signals to become significant.

Further, when two or more of the plurality of input signals become significant at the same time, the output signal of the gate element becomes significant at the timing at which the gate element which conducts first thereafter becomes conductive. As a result, a gate fixing signal is supplied from the gate fixing means to the gate control means, and the conduction / interruption state of the plurality of gate elements at that time is held by the gate control means. At this time, even if there is another input signal that becomes significant at the same time, the gate element corresponding to this other signal does not conduct, and therefore the output signal of that gate element does not become significant, and two or more The output signals of the gate elements are never significant at the same time.

When the input signal corresponding to the previously conducted gate element becomes insignificant thereafter, the supply of the gate fixing signal is stopped, and the plurality of gate elements are cyclically conducted one by one again by the gate control means. Therefore, at the same time, the gate element corresponding to the other significant input signal is rendered conductive, and the output signal of the gate element becomes significant.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An arbiter circuit according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of an arbiter circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes first to fourth request signals (input signals) A to
D is a gate means composed of four gate elements, each of which is supplied with first to fourth acceptance signals (output signals).
a to d are taken out.

Reference numeral 2 is a gate control means for controlling conduction / interruption of the four gate elements so that the four gate elements are cyclically conducted one by one, and is composed of a counter 2a and a decoder 2b. Reference numeral 3 gives a gate fixing signal e to the gate control means 2 when any of the output signals of the four gate elements becomes significant (“H”), and holds the conduction / interruption state of the four gate elements. In addition, the gate fixing means stops the supply of the gate fixing signal e when the output signals of all the four gate elements are no longer significant (“H”).

The operation of the arbiter circuit shown in FIG. 1 will be described. In this arbiter circuit, the plurality of gate elements to which the plurality of request signals A to D are respectively supplied in the gate means 1 are made to be conductive one by one, and any one of the plurality of request signals A to D, for example, When the request signal A becomes significant (for example, “H” level), the output signal of the gate element, that is, the acceptance signal a becomes significant at the timing when the gate element to which the request signal A is supplied becomes conductive. As a result, the gate fixing signal e is supplied from the gate fixing means 3 to the gate control means 2, and the conduction / interruption state of the plurality of gate elements at that time is held by the gate control means 2. At this time, even if the other request signals B to D become significant, the gate element corresponding to the other request signals B to D does not conduct, and therefore the output signal of the gate element, that is, the acceptance signals b to d It is never significant, and the output signals of two or more gate elements are never significant at the same time.

When the above-mentioned significant request signal A becomes less significant thereafter, the supply of the gate fixing signal e is stopped, and the gate control means 2 makes the plurality of gate elements cyclically conduct one by one again. Then, the gate element corresponding to the other request signals B to D is made conductive to make the output signal of the gate element, that is, the acceptance signals b to d significant, or one of the plurality of request signals A to D. We will wait until is significant.

Further, when two or more of the plurality of request signals A to D, for example, the request signals A and B become significant at the same time, the output signal of the gate element which is turned on first is turned on. For example, the reception signal b becomes significant. As a result, the gate fixing signal e is supplied from the gate fixing means 3 to the gate control means 2, and the conduction / interruption state of the plurality of gate elements at that time is held by the gate control means 2. At this time, even if there is another request signal A that becomes significant at the same time, the gate element corresponding to this other request signal A does not conduct, and therefore the output signal of that gate element, that is, the acceptance signal a becomes significant. And the output signals of more than one gate element are never significant at the same time.

When the request signal B corresponding to the previously conducted gate element becomes insignificant thereafter, the supply of the gate fixing signal e is stopped, and the gate control means 2 causes the plurality of gate elements to be cyclically again one by one. The gate element corresponding to another request signal A that has become significant at the same time is made conductive, and the output signal of the gate element, that is, the acceptance signal b becomes significant.

FIG. 2 is a circuit diagram showing an example of a concrete circuit configuration of the arbiter circuit of FIG. In FIG. 2, the gate means 1 comprises first to fourth 2-input AND gates 11 to 14 to which the first to fourth request signals A to D are supplied to one input terminal. Further, the gate fixing means 3 includes a 4-input NOR gate 19 to which the outputs of the first to fourth 2-input AND gates 11 to 14 are respectively supplied to the four input terminals, and the 4-input NOR gate. An exclusive OR gate 20 whose output is supplied to one input terminal
And the output of the exclusive OR gate 20 is supplied to the D input terminal, the Q output is supplied to the other input terminal of the exclusive OR gate 20, and the external clock signal OSC is supplied to the clock terminal. And a flip-flop 21.

Further, the gate control means 2 includes a second D flip-flop 22 to which the Q output of the first D flip-flop 21 is supplied to the clock terminal and a Q output of the second D flip-flop 22. The third flip-flop 23 is supplied to the input terminal and the Q output of the first D flip-flop 21 is supplied to the clock terminal, and the Q output of the third flip-flop 23 is supplied to the D input terminal. Together with the Q of the first D flip-flop 21
A fourth flip-flop 24, whose output is supplied to the clock terminal and whose Q output is supplied to the D input terminal of the first D flip-flop 21, and second, third and fourth D flip-flops 22, 23, 24. NQ output is supplied to each of the three input terminals, and the output is the first 2-input AND gate 1
The first 3-input AND gate 15 supplied to the other input terminal of 1 and the Q output of the second D flip-flop 22 and the NQ outputs of the third and fourth D flip-flops 23 and 24 are three. A second 3-input AND gate 16 which is supplied to each of the input terminals and whose output is supplied to the other input terminal of the second 2-input AND gate 12, and second and third
The Q outputs of the D flip-flops 22 and 23 and the NQ output of the fourth D flip-flop 24 are respectively supplied to the three input terminals, and the outputs are output to the third 2-input AND gate 13.
Of the third 3-input AND gate 17 supplied to the other input terminal of the above and the Q outputs of the second, third and fourth D flip-flops 22, 23 and 24 are supplied to the three input terminals and output. Is provided to the other input terminal of the fourth 2-input AND gate 14, and the fourth 3-input AND gate 18 is supplied.

The above-mentioned second, third and fourth D flip-flops 22, 23, 24 constitute a counter 2a whose count is controlled by the gate fixing means 3, and the first, second, third and fourth counters are provided. The 4-input 3-input AND gate 18 constitutes a decoder 2b for decoding the output of the counter 2a. 3, 4 and 5 are timing charts showing the operation of the arbiter circuit according to the embodiment of the present invention. 3 is a timing chart when no request signal is input, FIG. 4 is a timing chart when two or more request signals are not input to the arbiter circuit at the same time, and FIG. 5 is two timing signals when the request signals are simultaneously input to the arbiter circuit. It is a timing chart at the time of being input.

First, the timing chart of FIG. 3 will be described. In a state where all the request signals A to D are insignificant (“L”), the output signal A1 of the 4-input NOR gate 19 is “H”, and the output signals A2 and D of the 2-input exclusive OR gate 20. Q of flip-flop 21
The output A3 alternately repeats "H" and "L" in opposite phases at a frequency of 1/2 of the external clock signal OSC. At this time, the Q output B1 of the D flip-flop 22
Is "H" for three cycles of the Q output A3 of the D flip-flop 21 and "L" is repeated for the next three cycles. The Q output B2 of the D flip-flop 23 has a waveform obtained by delaying the Q output B1 of the D flip-flop 22 by one cycle of the Q output A3 of the D flip-flop 21, and the Q output B3 of the D flip-flop 24 is the D output of the D flip-flop 23. Q output B2 is delayed by one cycle of Q output A3 of D flip-flop 21.

The output signal D1 of the 3-input AND gate 15 becomes "H" for one cycle of the Q output A3 of the D flip-flop 21 for every 6 cycles of the Q output A3 of the D flip-flop 21, and "L" for the remaining 5 cycles. The waveform becomes The output signals D2 to D4 of the 3-input AND gates 16 to 18 have waveforms that are sequentially shifted from the waveform of the output signal D1 of the 3-input AND gate 15 by one cycle of the Q output A3 of the D flip-flop 21, respectively. Become. Reception signals a to d are all "L"
Is.

Next, the timing chart of FIG. 4 will be described when two or more request signals do not become significant ("H") at the same time, for example, when the request signal A becomes significant ("H") alone. . When the request signal A input to the 2-input AND gate 11 becomes "H" and the output signal D1 of the 3-input AND gate 15 becomes "H", the acceptance signal a which is the output signal of the 2-input AND gate 11 Becomes "H", the output signal A1 of the 4-input NOR gate 19 becomes "L", and one input of the 2-input exclusive OR gate 20 becomes "L", so that the 2-input exclusive OR gate Two
The output signal A2 of 0 becomes equal to the Q output A3 of the D flip-flop 21, and even if the rising edge of the external clock signal OSC is input to the clock terminal of the D flip-flop 21, the Q output A3 of the D flip-flop 21 is By holding the result of the Q output of the cycle, the output state of the D flip-flops 22 to 24 holds the result of the previous cycle. Therefore, the output result of the 3-input AND gates 15 to 18 is also the state of the previous cycle, that is, 3-input AND gate 15
Only the output signal D1 of "1" becomes "H", the acceptance signal a becomes "H", and the request signal A is accepted. This is the same operation for the request signals B, C, and D.

Next, the timing chart of FIG. 5 will be described for the case where the two request signals A and B simultaneously become significant ("H"). When the request signal A and the request signal B input to the arbiter circuit simultaneously become “H”,
The output signal D1 of the 3-input AND gate 15 is "L", the output signal D2 of the 3-input AND gate 16 is "H", and the output signals D3 of the 3-input AND gates 17 and 18 are
When D4 is "L", 2-input AND gates 11 and 1
The acceptance signals a, c, d which are the output signals of 3, 14 are "L".
Therefore, the acceptance signal b, which is the output signal of the 2-input AND gate 12, becomes "H", and the output signal A1 of the 4-input NOR gate 19 becomes "L". Since one input of the 2-input exclusive OR gate 20 becomes "L", the output signal A2 of the 2-input exclusive OR gate 20 becomes equal to the Q output A3 of the D flip-flop 21, and the external clock signal O
Even if the rising edge of SC is input to the clock terminal of the D flip-flop 21, the Q output A3 of the D flip-flop 21 holds the result of the Q output of the previous cycle, and the output states of the D flip-flops 22 to 24 are Since the result of the cycle is held, the output results of the 3-input AND gates 15 to 18 are also in the state of the previous cycle, that is, only the output signal D2 of the 3-input AND gate 16 becomes "H" and the acceptance signal b becomes "H". ", Which means that the request signal B has been accepted. After that, when the request signal B becomes "L", the output signal of the 2-input AND gate 12 becomes "L", and the output signal A1 of the 4-input NOR gate 19 becomes "H".
The output signal A2 of the input exclusive OR gate 20 becomes an inverted signal of the Q output A3 of the D flip-flop 21, and when the rising edge of the external clock signal OSC is input to the clock terminal of the D flip-flop 21, The Q output A3 of 21 becomes an inverted signal of the Q output of the previous cycle, and when the Q output A3 of the D flip-flop 21 repeats from "L" to "H", the D flip-flop 2
When the output states of 2 to 24 continue to transition and then the output signal D1 of the 3-input AND gate 15 becomes "H", the acceptance signal a which is the output signal of the 2-input AND gate 11 is "H".
Therefore, the output signal A1 of the 4-input NOR gate 19 becomes "L". Since one input of the 2-input exclusive OR gate 19 becomes "L", the output signal A2 of the 4-input exclusive OR gate 21 is the Q output A3 of the D flip-flop 21.
Even if the rising edge of the external clock signal OSC is input to the clock terminal of the D flip-flop 21, the Q output A3 of the D flip-flop 21 holds the result of the Q output of the previous cycle, and the D flip-flop 22
Since the output states of ~ 24 hold the result of the previous cycle, the output results of the 3-input AND gates 15-18 are also in the state of the previous cycle, that is, only the output signal D1 of the 3-input AND gate 15 is "H". The acceptance signal a becomes "H", and the request signal A is accepted. Below 3
The same operation is performed even if one or more request signals are input at the same time.

As a result, the specifications of the arbiter circuit of adjusting two or more competing request signals A to D and selecting any one of the request signals are satisfied. In the above embodiment, the embodiment of the arbiter circuit that adjusts four request signals has been described. However, the number of request signals to be adjusted is not limited to four, and the specific circuit configuration of the arbiter circuit is adjusted. The number is appropriately changed according to the number of request signals to be processed.

[0034]

According to the arbiter circuit of the present invention, the gate means including the plurality of gate elements to which the plurality of input signals are respectively supplied is provided, and the plurality of gate elements are cyclically conducted one by one. Conduction of the gate element of
A gate control means for controlling interruption is provided, and when the output signal of any of the plurality of gate elements becomes significant, a gate fixing signal is given to the gate control means to maintain the conduction / interruption state of the plurality of gate elements. Since the gate fixing means for stopping the supply of the gate fixing signal when any output signal of the plurality of gate elements becomes insignificant is provided, a circuit for adjusting the competition of the plurality of input signals without using the delay circuit is provided. It is possible to configure, and thus it is possible to adjust the competition of two or more request signals with a smaller circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an arbiter circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of the arbiter circuit shown in FIG.

FIG. 3 is a timing chart showing the operation of FIG.

FIG. 4 is a timing chart showing the operation of FIG.

FIG. 5 is a timing chart showing the operation of FIG.

FIG. 6 is a block diagram showing a configuration of a conventional arbiter circuit.

FIG. 7 is a circuit diagram showing a configuration of a 3R-RS flip-flop used in a conventional arbiter circuit.

[Explanation of symbols]

 1 Gate Means 2 Gate Control Means 3 Gate Fixing Means 11 to 14 2 Input AND Gates 15 to 18 3 Input AND Gates 19 4 Input NOR Gates 20 2 Input Exclusive OR Gates 21 to 24 D Flip-Flops 10 12 Input NOR gate 102 4-input NOR gate 111-114 2-input AND gate 115-118 3R-RS flip-flop 119-122 Delay element 123,124 2-input OR gate 125 4-input NOR gate

Claims (2)

[Claims] 1. A gate means composed of a plurality of gate elements to which a plurality of input signals are respectively supplied, and conduction / interruption of the plurality of gate elements so that the plurality of gate elements are cyclically conducted one by one. Gate control means for controlling, and when the output signal of any of the plurality of gate elements becomes significant, a gate fixing signal is given to the gate control means to maintain the conduction / interruption state of the plurality of gate elements. An arbiter circuit comprising: gate fixing means for stopping the supply of the gate fixing signal when any output signal of the plurality of gate elements becomes insignificant. 2. The gate means comprises first to fourth two-input AND gates to which one of the first to fourth input signals is supplied to one input terminal, and the gate fixing means comprises the first to fourth input gates. A 4-input NOR gate to which the output signal of the 4-input 2-AND gate is supplied to four input terminals respectively, and an exclusive logic in which the output signal of the 4-input NOR gate is supplied to one input terminal The output signal of the OR gate and this exclusive OR gate is D
A first D flip-flop which is supplied to the input terminal, whose Q output is supplied to the other input terminal of the exclusive OR gate, and whose external clock signal is supplied to the clock terminal; Q of D flip-flop
A second D flip-flop whose output is supplied to the clock terminal, and a Q output of the second D flip-flop is supplied to the D input terminal and a Q output of the first D flip-flop is supplied to the clock terminal. And a Q output of the third flip-flop is supplied to a D input terminal, a Q output of the first D flip-flop is supplied to a clock terminal, and a Q output is supplied to the first flip-flop. A fourth flip-flop supplied to the D input terminal of the D flip-flop, and the second, third and fourth flip-flops.
The NQ output (meaning the inversion of the Q output) of the D flip-flop is supplied to each of the three input terminals, and the output signal is supplied to the other input terminal of the first two-input AND gate. An input AND gate, the Q output of the second D flip-flop and the NQ outputs of the third and fourth D flip-flops are supplied to three input terminals, respectively, and the output signal is the second 2-input AND. A second 3-input AND gate supplied to the other input terminal of the gate, Q outputs of the second and third D flip-flops, and NQ outputs of the fourth D flip-flop are provided at three input terminals. The output signal supplied to each of the third two
A third three-input AND gate supplied to the other input terminal of the input AND gate, and the second, third and fourth D
2. A fourth 3-input AND gate, wherein the Q output of the flip-flop is supplied to each of the three input terminals, and the output signal is supplied to the other input terminal of the fourth 2-input AND gate. Arbiter circuit.